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git01.mediatek.com / filogic / uboot / 34f37552896e564c4d8ea11b279441e3b6ccaad0 / . / arch / arm / dts / tegra124-apalis.dts
blob: fe08d3ea7304901d6af33ed57e12571c78d2f0db [file] [log] [blame]
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -0700[diff] [blame]1/*
2 * Copyright 2016 Toradex AG
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * Or, alternatively
19 *
20 * b) Permission is hereby granted, free of charge, to any person
21 * obtaining a copy of this software and associated documentation
22 * files (the "Software"), to deal in the Software without
23 * restriction, including without limitation the rights to use
24 * copy, modify, merge, publish, distribute, sublicense, and/or
25 * sell copies of the Software, and to permit persons to whom the
26 * Software is furnished to do so, subject to the following
27 * conditions:
28 *
29 * The above copyright notice and this permission notice shall be
30 * included in all copies or substantial portions of the Software.
31 *
32 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
33 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
34 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
35 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
36 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
37 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
38 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
39 * OTHER DEALINGS IN THE SOFTWARE.
40 */
41
42/dts-v1/;
43
44#include <dt-bindings/input/input.h>
45#include "tegra124.dtsi"
46
47/ {
48 model = "Toradex Apalis TK1 on Apalis Evaluation Board";
49 compatible = "toradex,apalis-tk1-eval", "toradex,apalis-tk1",
50 "nvidia,tegra124";
51
52 aliases {
53 i2c0 = "/i2c@7000d000";
54 i2c1 = "/i2c@7000c000";
55 i2c2 = "/i2c@7000c400";
56 i2c3 = "/i2c@7000c500";
57 mmc0 = "/sdhci@700b0600";
58 mmc1 = "/sdhci@700b0000";
59 mmc2 = "/sdhci@700b0400";
60 rtc0 = "/i2c@7000c000/rtc@68";
61 rtc1 = "/i2c@7000d000/pmic@40";
62 rtc2 = "/rtc@7000e000";
63 serial0 = &uarta;
64 serial1 = &uartb;
65 serial2 = &uartc;
66 serial3 = &uartd;
67 usb0 = "/usb@7d000000";
68 usb1 = "/usb@7d004000";
69 usb2 = "/usb@7d008000";
70 };
71
72 chosen {
73 stdout-path = "serial0:115200n8";
74 };
75
76 memory {
77 reg = <0x0 0x80000000 0x0 0x80000000>;
78 };
79
80 pcie-controller@01003000 {
81 status = "okay";
82 avddio-pex-supply = <&vdd_1v05>;
83 avdd-pex-pll-supply = <&vdd_1v05>;
84 avdd-pll-erefe-supply = <&avdd_1v05>;
85 dvddio-pex-supply = <&vdd_1v05>;
86 hvdd-pex-pll-e-supply = <&reg_3v3>;
87 hvdd-pex-supply = <&reg_3v3>;
88 vddio-pex-ctl-supply = <&reg_3v3>;
89
90 /* Apalis PCIe (additional lane Apalis type specific) */
91 pci@1,0 {
92 /* PCIE1_RX/TX and TS_DIFF1/2 left disabled */
93 };
94
95 /* I210 Gigabit Ethernet Controller (On-module) */
96 pci@2,0 {
97 status = "okay";
98 };
99 };
100
101 host1x@50000000 {
102 hdmi@54280000 {
103 pll-supply = <&reg_1v05_avdd_hdmi_pll>;
104 vdd-supply = <&reg_3v3_avdd_hdmi>;
105 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
106 nvidia,hpd-gpio =
107 <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
108 status = "okay";
109 };
110 };
111
112 gpu@0,57000000 {
113 /*
114 * Node left disabled on purpose - the bootloader will enable
115 * it after having set the VPR up
116 */
117 vdd-supply = <&vdd_gpu>;
118 };
119
120 pinmux: pinmux@70000868 {
121 pinctrl-names = "default";
122 pinctrl-0 = <&state_default>;
123
124 state_default: pinmux {
125 /* Analogue Audio (On-module) */
126 dap3_fs_pp0 {
127 nvidia,pins = "dap3_fs_pp0";
128 nvidia,function = "i2s2";
129 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
130 nvidia,tristate = <TEGRA_PIN_DISABLE>;
131 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
132 };
133 dap3_din_pp1 {
134 nvidia,pins = "dap3_din_pp1";
135 nvidia,function = "i2s2";
136 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
137 nvidia,tristate = <TEGRA_PIN_ENABLE>;
138 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
139 };
140 dap3_dout_pp2 {
141 nvidia,pins = "dap3_dout_pp2";
142 nvidia,function = "i2s2";
143 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
144 nvidia,tristate = <TEGRA_PIN_DISABLE>;
145 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
146 };
147 dap3_sclk_pp3 {
148 nvidia,pins = "dap3_sclk_pp3";
149 nvidia,function = "i2s2";
150 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
151 nvidia,tristate = <TEGRA_PIN_DISABLE>;
152 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
153 };
154 dap_mclk1_pw4 {
155 nvidia,pins = "dap_mclk1_pw4";
156 nvidia,function = "extperiph1";
157 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
158 nvidia,tristate = <TEGRA_PIN_DISABLE>;
159 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
160 };
161
162 /* Apalis BKL1_ON */
163 pbb5 {
164 nvidia,pins = "pbb5";
165 nvidia,function = "vgp5";
166 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
167 nvidia,tristate = <TEGRA_PIN_DISABLE>;
168 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
169 };
170
171 /* Apalis BKL1_PWM */
172 pu6 {
173 nvidia,pins = "pu6";
174 nvidia,function = "pwm3";
175 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
176 nvidia,tristate = <TEGRA_PIN_DISABLE>;
177 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
178 };
179
180 /* Apalis CAM1_MCLK */
181 cam_mclk_pcc0 {
182 nvidia,pins = "cam_mclk_pcc0";
183 nvidia,function = "vi_alt3";
184 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
185 nvidia,tristate = <TEGRA_PIN_DISABLE>;
186 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
187 };
188
189 /* Apalis Digital Audio */
190 dap2_fs_pa2 {
191 nvidia,pins = "dap2_fs_pa2";
192 nvidia,function = "hda";
193 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
194 nvidia,tristate = <TEGRA_PIN_DISABLE>;
195 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
196 };
197 dap2_sclk_pa3 {
198 nvidia,pins = "dap2_sclk_pa3";
199 nvidia,function = "hda";
200 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
201 nvidia,tristate = <TEGRA_PIN_DISABLE>;
202 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
203 };
204 dap2_din_pa4 {
205 nvidia,pins = "dap2_din_pa4";
206 nvidia,function = "hda";
207 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
208 nvidia,tristate = <TEGRA_PIN_ENABLE>;
209 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
210 };
211 dap2_dout_pa5 {
212 nvidia,pins = "dap2_dout_pa5";
213 nvidia,function = "hda";
214 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
215 nvidia,tristate = <TEGRA_PIN_DISABLE>;
216 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
217 };
218 pbb3 { /* DAP1_RESET */
219 nvidia,pins = "pbb3";
220 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
221 nvidia,tristate = <TEGRA_PIN_DISABLE>;
222 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
223 };
224 clk3_out_pee0 {
225 nvidia,pins = "clk3_out_pee0";
226 nvidia,function = "extperiph3";
227 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
228 nvidia,tristate = <TEGRA_PIN_DISABLE>;
229 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
230 };
231
232 /* Apalis GPIO */
233 ddc_scl_pv4 {
234 nvidia,pins = "ddc_scl_pv4";
235 nvidia,function = "rsvd2";
236 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
237 nvidia,tristate = <TEGRA_PIN_DISABLE>;
238 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
239 };
240 ddc_sda_pv5 {
241 nvidia,pins = "ddc_sda_pv5";
242 nvidia,function = "rsvd2";
243 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
244 nvidia,tristate = <TEGRA_PIN_DISABLE>;
245 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
246 };
247 pex_l0_rst_n_pdd1 {
248 nvidia,pins = "pex_l0_rst_n_pdd1";
249 nvidia,function = "rsvd2";
250 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
251 nvidia,tristate = <TEGRA_PIN_DISABLE>;
252 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
253 };
254 pex_l0_clkreq_n_pdd2 {
255 nvidia,pins = "pex_l0_clkreq_n_pdd2";
256 nvidia,function = "rsvd2";
257 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
258 nvidia,tristate = <TEGRA_PIN_DISABLE>;
259 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
260 };
261 pex_l1_rst_n_pdd5 {
262 nvidia,pins = "pex_l1_rst_n_pdd5";
263 nvidia,function = "rsvd2";
264 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
265 nvidia,tristate = <TEGRA_PIN_DISABLE>;
266 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
267 };
268 pex_l1_clkreq_n_pdd6 {
269 nvidia,pins = "pex_l1_clkreq_n_pdd6";
270 nvidia,function = "rsvd2";
271 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
272 nvidia,tristate = <TEGRA_PIN_DISABLE>;
273 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
274 };
275 dp_hpd_pff0 {
276 nvidia,pins = "dp_hpd_pff0";
277 nvidia,function = "dp";
278 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
279 nvidia,tristate = <TEGRA_PIN_DISABLE>;
280 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
281 };
282 pff2 {
283 nvidia,pins = "pff2";
284 nvidia,function = "rsvd2";
285 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
286 nvidia,tristate = <TEGRA_PIN_DISABLE>;
287 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
288 };
289 owr { /* PEX_L1_CLKREQ_N multiplexed GPIO6 */
290 nvidia,pins = "owr";
291 nvidia,function = "rsvd2";
292 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
293 nvidia,tristate = <TEGRA_PIN_ENABLE>;
294 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
295 nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
296 };
297
298 /* Apalis HDMI1_CEC */
299 hdmi_cec_pee3 {
300 nvidia,pins = "hdmi_cec_pee3";
301 nvidia,function = "cec";
302 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
303 nvidia,tristate = <TEGRA_PIN_DISABLE>;
304 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
305 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
306 };
307
308 /* Apalis HDMI1_HPD */
309 hdmi_int_pn7 {
310 nvidia,pins = "hdmi_int_pn7";
311 nvidia,function = "rsvd1";
312 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
313 nvidia,tristate = <TEGRA_PIN_ENABLE>;
314 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
315 nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
316 };
317
318 /* Apalis I2C1 */
319 gen1_i2c_scl_pc4 {
320 nvidia,pins = "gen1_i2c_scl_pc4";
321 nvidia,function = "i2c1";
322 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
323 nvidia,tristate = <TEGRA_PIN_DISABLE>;
324 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
325 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
326 };
327 gen1_i2c_sda_pc5 {
328 nvidia,pins = "gen1_i2c_sda_pc5";
329 nvidia,function = "i2c1";
330 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
331 nvidia,tristate = <TEGRA_PIN_DISABLE>;
332 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
333 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
334 };
335
336 /* Apalis I2C2 (DDC) */
337 gen2_i2c_scl_pt5 {
338 nvidia,pins = "gen2_i2c_scl_pt5";
339 nvidia,function = "i2c2";
340 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
341 nvidia,tristate = <TEGRA_PIN_DISABLE>;
342 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
343 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
344 };
345 gen2_i2c_sda_pt6 {
346 nvidia,pins = "gen2_i2c_sda_pt6";
347 nvidia,function = "i2c2";
348 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
349 nvidia,tristate = <TEGRA_PIN_DISABLE>;
350 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
351 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
352 };
353
354 /* Apalis I2C3 (CAM) */
355 cam_i2c_scl_pbb1 {
356 nvidia,pins = "cam_i2c_scl_pbb1";
357 nvidia,function = "i2c3";
358 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
359 nvidia,tristate = <TEGRA_PIN_DISABLE>;
360 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
361 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
362 };
363 cam_i2c_sda_pbb2 {
364 nvidia,pins = "cam_i2c_sda_pbb2";
365 nvidia,function = "i2c3";
366 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
367 nvidia,tristate = <TEGRA_PIN_DISABLE>;
368 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
369 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
370 };
371
372 /* Apalis MMC1 */
373 sdmmc1_cd_n_pv3 { /* CD# GPIO */
374 nvidia,pins = "sdmmc1_wp_n_pv3";
375 nvidia,function = "sdmmc1";
376 nvidia,pull = <TEGRA_PIN_PULL_UP>;
377 nvidia,tristate = <TEGRA_PIN_ENABLE>;
378 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
379 };
380 clk2_out_pw5 { /* D5 GPIO */
381 nvidia,pins = "clk2_out_pw5";
382 nvidia,function = "rsvd2";
383 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
384 nvidia,tristate = <TEGRA_PIN_DISABLE>;
385 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
386 };
387 sdmmc1_dat3_py4 {
388 nvidia,pins = "sdmmc1_dat3_py4";
389 nvidia,function = "sdmmc1";
390 nvidia,pull = <TEGRA_PIN_PULL_UP>;
391 nvidia,tristate = <TEGRA_PIN_DISABLE>;
392 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
393 };
394 sdmmc1_dat2_py5 {
395 nvidia,pins = "sdmmc1_dat2_py5";
396 nvidia,function = "sdmmc1";
397 nvidia,pull = <TEGRA_PIN_PULL_UP>;
398 nvidia,tristate = <TEGRA_PIN_DISABLE>;
399 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
400 };
401 sdmmc1_dat1_py6 {
402 nvidia,pins = "sdmmc1_dat1_py6";
403 nvidia,function = "sdmmc1";
404 nvidia,pull = <TEGRA_PIN_PULL_UP>;
405 nvidia,tristate = <TEGRA_PIN_DISABLE>;
406 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
407 };
408 sdmmc1_dat0_py7 {
409 nvidia,pins = "sdmmc1_dat0_py7";
410 nvidia,function = "sdmmc1";
411 nvidia,pull = <TEGRA_PIN_PULL_UP>;
412 nvidia,tristate = <TEGRA_PIN_DISABLE>;
413 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
414 };
415 sdmmc1_clk_pz0 {
416 nvidia,pins = "sdmmc1_clk_pz0";
417 nvidia,function = "sdmmc1";
418 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
419 nvidia,tristate = <TEGRA_PIN_DISABLE>;
420 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
421 };
422 sdmmc1_cmd_pz1 {
423 nvidia,pins = "sdmmc1_cmd_pz1";
424 nvidia,function = "sdmmc1";
425 nvidia,pull = <TEGRA_PIN_PULL_UP>;
426 nvidia,tristate = <TEGRA_PIN_DISABLE>;
427 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
428 };
429 clk2_req_pcc5 { /* D4 GPIO */
430 nvidia,pins = "clk2_req_pcc5";
431 nvidia,function = "rsvd2";
432 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
433 nvidia,tristate = <TEGRA_PIN_DISABLE>;
434 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
435 };
436 sdmmc3_clk_lb_in_pee5 { /* D6 GPIO */
437 nvidia,pins = "sdmmc3_clk_lb_in_pee5";
438 nvidia,function = "rsvd2";
439 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
440 nvidia,tristate = <TEGRA_PIN_DISABLE>;
441 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
442 };
443 usb_vbus_en2_pff1 { /* D7 GPIO */
444 nvidia,pins = "usb_vbus_en2_pff1";
445 nvidia,function = "rsvd2";
446 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
447 nvidia,tristate = <TEGRA_PIN_DISABLE>;
448 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
449 };
450
451 /* Apalis PWM */
452 ph0 {
453 nvidia,pins = "ph0";
454 nvidia,function = "pwm0";
455 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
456 nvidia,tristate = <TEGRA_PIN_DISABLE>;
457 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
458 };
459 ph1 {
460 nvidia,pins = "ph1";
461 nvidia,function = "pwm1";
462 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
463 nvidia,tristate = <TEGRA_PIN_DISABLE>;
464 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
465 };
466 ph2 {
467 nvidia,pins = "ph2";
468 nvidia,function = "pwm2";
469 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
470 nvidia,tristate = <TEGRA_PIN_DISABLE>;
471 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
472 };
473 /* PWM3 active on pu6 being Apalis BKL1_PWM */
474 ph3 {
475 nvidia,pins = "ph3";
476 nvidia,function = "gmi";
477 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
478 nvidia,tristate = <TEGRA_PIN_ENABLE>;
479 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
480 };
481
482 /* Apalis SATA1_ACT# */
483 dap1_dout_pn2 {
484 nvidia,pins = "dap1_dout_pn2";
485 nvidia,function = "gmi";
486 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
487 nvidia,tristate = <TEGRA_PIN_DISABLE>;
488 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
489 };
490
491 /* Apalis SD1 */
492 sdmmc3_clk_pa6 {
493 nvidia,pins = "sdmmc3_clk_pa6";
494 nvidia,function = "sdmmc3";
495 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
496 nvidia,tristate = <TEGRA_PIN_DISABLE>;
497 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
498 };
499 sdmmc3_cmd_pa7 {
500 nvidia,pins = "sdmmc3_cmd_pa7";
501 nvidia,function = "sdmmc3";
502 nvidia,pull = <TEGRA_PIN_PULL_UP>;
503 nvidia,tristate = <TEGRA_PIN_DISABLE>;
504 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
505 };
506 sdmmc3_dat3_pb4 {
507 nvidia,pins = "sdmmc3_dat3_pb4";
508 nvidia,function = "sdmmc3";
509 nvidia,pull = <TEGRA_PIN_PULL_UP>;
510 nvidia,tristate = <TEGRA_PIN_DISABLE>;
511 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
512 };
513 sdmmc3_dat2_pb5 {
514 nvidia,pins = "sdmmc3_dat2_pb5";
515 nvidia,function = "sdmmc3";
516 nvidia,pull = <TEGRA_PIN_PULL_UP>;
517 nvidia,tristate = <TEGRA_PIN_DISABLE>;
518 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
519 };
520 sdmmc3_dat1_pb6 {
521 nvidia,pins = "sdmmc3_dat1_pb6";
522 nvidia,function = "sdmmc3";
523 nvidia,pull = <TEGRA_PIN_PULL_UP>;
524 nvidia,tristate = <TEGRA_PIN_DISABLE>;
525 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
526 };
527 sdmmc3_dat0_pb7 {
528 nvidia,pins = "sdmmc3_dat0_pb7";
529 nvidia,function = "sdmmc3";
530 nvidia,pull = <TEGRA_PIN_PULL_UP>;
531 nvidia,tristate = <TEGRA_PIN_DISABLE>;
532 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
533 };
534 sdmmc3_cd_n_pv2 { /* CD# GPIO */
535 nvidia,pins = "sdmmc3_cd_n_pv2";
536 nvidia,function = "rsvd3";
537 nvidia,pull = <TEGRA_PIN_PULL_UP>;
538 nvidia,tristate = <TEGRA_PIN_ENABLE>;
539 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
540 };
541
542 /* Apalis SPDIF */
543 spdif_out_pk5 {
544 nvidia,pins = "spdif_out_pk5";
545 nvidia,function = "spdif";
546 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
547 nvidia,tristate = <TEGRA_PIN_DISABLE>;
548 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
549 };
550 spdif_in_pk6 {
551 nvidia,pins = "spdif_in_pk6";
552 nvidia,function = "spdif";
553 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
554 nvidia,tristate = <TEGRA_PIN_ENABLE>;
555 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
556 };
557
558 /* Apalis SPI1 */
559 ulpi_clk_py0 {
560 nvidia,pins = "ulpi_clk_py0";
561 nvidia,function = "spi1";
562 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
563 nvidia,tristate = <TEGRA_PIN_DISABLE>;
564 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
565 };
566 ulpi_dir_py1 {
567 nvidia,pins = "ulpi_dir_py1";
568 nvidia,function = "spi1";
569 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
570 nvidia,tristate = <TEGRA_PIN_ENABLE>;
571 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
572 };
573 ulpi_nxt_py2 {
574 nvidia,pins = "ulpi_nxt_py2";
575 nvidia,function = "spi1";
576 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
577 nvidia,tristate = <TEGRA_PIN_DISABLE>;
578 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
579 };
580 ulpi_stp_py3 {
581 nvidia,pins = "ulpi_stp_py3";
582 nvidia,function = "spi1";
583 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
584 nvidia,tristate = <TEGRA_PIN_DISABLE>;
585 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
586 };
587
588 /* Apalis SPI2 */
589 pg5 {
590 nvidia,pins = "pg5";
591 nvidia,function = "spi4";
592 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
593 nvidia,tristate = <TEGRA_PIN_DISABLE>;
594 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
595 };
596 pg6 {
597 nvidia,pins = "pg6";
598 nvidia,function = "spi4";
599 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
600 nvidia,tristate = <TEGRA_PIN_DISABLE>;
601 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
602 };
603 pg7 {
604 nvidia,pins = "pg7";
605 nvidia,function = "spi4";
606 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
607 nvidia,tristate = <TEGRA_PIN_ENABLE>;
608 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
609 };
610 pi3 {
611 nvidia,pins = "pi3";
612 nvidia,function = "spi4";
613 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
614 nvidia,tristate = <TEGRA_PIN_DISABLE>;
615 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
616 };
617
618 /* Apalis UART1 */
619 pb1 { /* DCD GPIO */
620 nvidia,pins = "pb1";
621 nvidia,function = "rsvd2";
622 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
623 nvidia,tristate = <TEGRA_PIN_ENABLE>;
624 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
625 };
626 pk7 { /* RI GPIO */
627 nvidia,pins = "pk7";
628 nvidia,function = "rsvd2";
629 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
630 nvidia,tristate = <TEGRA_PIN_ENABLE>;
631 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
632 };
633 uart1_txd_pu0 {
634 nvidia,pins = "pu0";
635 nvidia,function = "uarta";
636 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
637 nvidia,tristate = <TEGRA_PIN_DISABLE>;
638 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
639 };
640 uart1_rxd_pu1 {
641 nvidia,pins = "pu1";
642 nvidia,function = "uarta";
643 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
644 nvidia,tristate = <TEGRA_PIN_ENABLE>;
645 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
646 };
647 uart1_cts_n_pu2 {
648 nvidia,pins = "pu2";
649 nvidia,function = "uarta";
650 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
651 nvidia,tristate = <TEGRA_PIN_ENABLE>;
652 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
653 };
654 uart1_rts_n_pu3 {
655 nvidia,pins = "pu3";
656 nvidia,function = "uarta";
657 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
658 nvidia,tristate = <TEGRA_PIN_DISABLE>;
659 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
660 };
661 uart3_cts_n_pa1 { /* DSR GPIO */
662 nvidia,pins = "uart3_cts_n_pa1";
663 nvidia,function = "gmi";
664 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
665 nvidia,tristate = <TEGRA_PIN_ENABLE>;
666 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
667 };
668 uart3_rts_n_pc0 { /* DTR GPIO */
669 nvidia,pins = "uart3_rts_n_pc0";
670 nvidia,function = "gmi";
671 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
672 nvidia,tristate = <TEGRA_PIN_DISABLE>;
673 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
674 };
675
676 /* Apalis UART2 */
677 uart2_txd_pc2 {
678 nvidia,pins = "uart2_txd_pc2";
679 nvidia,function = "irda";
680 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
681 nvidia,tristate = <TEGRA_PIN_DISABLE>;
682 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
683 };
684 uart2_rxd_pc3 {
685 nvidia,pins = "uart2_rxd_pc3";
686 nvidia,function = "irda";
687 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
688 nvidia,tristate = <TEGRA_PIN_ENABLE>;
689 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
690 };
691 uart2_cts_n_pj5 {
692 nvidia,pins = "uart2_cts_n_pj5";
693 nvidia,function = "uartb";
694 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
695 nvidia,tristate = <TEGRA_PIN_ENABLE>;
696 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
697 };
698 uart2_rts_n_pj6 {
699 nvidia,pins = "uart2_rts_n_pj6";
700 nvidia,function = "uartb";
701 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
702 nvidia,tristate = <TEGRA_PIN_DISABLE>;
703 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
704 };
705
706 /* Apalis UART3 */
707 uart3_txd_pw6 {
708 nvidia,pins = "uart3_txd_pw6";
709 nvidia,function = "uartc";
710 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
711 nvidia,tristate = <TEGRA_PIN_DISABLE>;
712 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
713 };
714 uart3_rxd_pw7 {
715 nvidia,pins = "uart3_rxd_pw7";
716 nvidia,function = "uartc";
717 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
718 nvidia,tristate = <TEGRA_PIN_ENABLE>;
719 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
720 };
721
722 /* Apalis UART4 */
723 uart4_rxd_pb0 {
724 nvidia,pins = "pb0";
725 nvidia,function = "uartd";
726 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
727 nvidia,tristate = <TEGRA_PIN_ENABLE>;
728 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
729 };
730 uart4_txd_pj7 {
731 nvidia,pins = "pj7";
732 nvidia,function = "uartd";
733 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
734 nvidia,tristate = <TEGRA_PIN_DISABLE>;
735 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
736 };
737
738 /* Apalis USBH_EN */
739 usb_vbus_en1_pn5 {
740 nvidia,pins = "usb_vbus_en1_pn5";
741 nvidia,function = "rsvd2";
742 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
743 nvidia,tristate = <TEGRA_PIN_DISABLE>;
744 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
745 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
746 };
747
748 /* Apalis USBH_OC# */
749 pbb0 {
750 nvidia,pins = "pbb0";
751 nvidia,function = "vgp6";
752 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
753 nvidia,tristate = <TEGRA_PIN_ENABLE>;
754 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
755 };
756
757 /* Apalis USBO1_EN */
758 usb_vbus_en0_pn4 {
759 nvidia,pins = "usb_vbus_en0_pn4";
760 nvidia,function = "rsvd2";
761 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
762 nvidia,tristate = <TEGRA_PIN_DISABLE>;
763 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
764 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
765 };
766
767 /* Apalis USBO1_OC# */
768 pbb4 {
769 nvidia,pins = "pbb4";
770 nvidia,function = "vgp4";
771 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
772 nvidia,tristate = <TEGRA_PIN_ENABLE>;
773 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
774 };
775
776 /* Apalis WAKE1_MICO */
777 pex_wake_n_pdd3 {
778 nvidia,pins = "pex_wake_n_pdd3";
779 nvidia,function = "rsvd2";
780 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
781 nvidia,tristate = <TEGRA_PIN_ENABLE>;
782 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
783 };
784
785 /* CORE_PWR_REQ */
786 core_pwr_req {
787 nvidia,pins = "core_pwr_req";
788 nvidia,function = "pwron";
789 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
790 nvidia,tristate = <TEGRA_PIN_DISABLE>;
791 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
792 };
793
794 /* CPU_PWR_REQ */
795 cpu_pwr_req {
796 nvidia,pins = "cpu_pwr_req";
797 nvidia,function = "cpu";
798 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
799 nvidia,tristate = <TEGRA_PIN_DISABLE>;
800 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
801 };
802
803 /* DVFS */
804 dvfs_pwm_px0 {
805 nvidia,pins = "dvfs_pwm_px0";
806 nvidia,function = "cldvfs";
807 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
808 nvidia,tristate = <TEGRA_PIN_DISABLE>;
809 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
810 };
811 dvfs_clk_px2 {
812 nvidia,pins = "dvfs_clk_px2";
813 nvidia,function = "cldvfs";
814 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
815 nvidia,tristate = <TEGRA_PIN_DISABLE>;
816 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
817 };
818
819 /* eMMC */
820 sdmmc4_dat0_paa0 {
821 nvidia,pins = "sdmmc4_dat0_paa0";
822 nvidia,function = "sdmmc4";
823 nvidia,pull = <TEGRA_PIN_PULL_UP>;
824 nvidia,tristate = <TEGRA_PIN_DISABLE>;
825 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
826 };
827 sdmmc4_dat1_paa1 {
828 nvidia,pins = "sdmmc4_dat1_paa1";
829 nvidia,function = "sdmmc4";
830 nvidia,pull = <TEGRA_PIN_PULL_UP>;
831 nvidia,tristate = <TEGRA_PIN_DISABLE>;
832 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
833 };
834 sdmmc4_dat2_paa2 {
835 nvidia,pins = "sdmmc4_dat2_paa2";
836 nvidia,function = "sdmmc4";
837 nvidia,pull = <TEGRA_PIN_PULL_UP>;
838 nvidia,tristate = <TEGRA_PIN_DISABLE>;
839 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
840 };
841 sdmmc4_dat3_paa3 {
842 nvidia,pins = "sdmmc4_dat3_paa3";
843 nvidia,function = "sdmmc4";
844 nvidia,pull = <TEGRA_PIN_PULL_UP>;
845 nvidia,tristate = <TEGRA_PIN_DISABLE>;
846 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
847 };
848 sdmmc4_dat4_paa4 {
849 nvidia,pins = "sdmmc4_dat4_paa4";
850 nvidia,function = "sdmmc4";
851 nvidia,pull = <TEGRA_PIN_PULL_UP>;
852 nvidia,tristate = <TEGRA_PIN_DISABLE>;
853 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
854 };
855 sdmmc4_dat5_paa5 {
856 nvidia,pins = "sdmmc4_dat5_paa5";
857 nvidia,function = "sdmmc4";
858 nvidia,pull = <TEGRA_PIN_PULL_UP>;
859 nvidia,tristate = <TEGRA_PIN_DISABLE>;
860 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
861 };
862 sdmmc4_dat6_paa6 {
863 nvidia,pins = "sdmmc4_dat6_paa6";
864 nvidia,function = "sdmmc4";
865 nvidia,pull = <TEGRA_PIN_PULL_UP>;
866 nvidia,tristate = <TEGRA_PIN_DISABLE>;
867 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
868 };
869 sdmmc4_dat7_paa7 {
870 nvidia,pins = "sdmmc4_dat7_paa7";
871 nvidia,function = "sdmmc4";
872 nvidia,pull = <TEGRA_PIN_PULL_UP>;
873 nvidia,tristate = <TEGRA_PIN_DISABLE>;
874 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
875 };
876 sdmmc4_clk_pcc4 {
877 nvidia,pins = "sdmmc4_clk_pcc4";
878 nvidia,function = "sdmmc4";
879 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
880 nvidia,tristate = <TEGRA_PIN_DISABLE>;
881 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
882 };
883 sdmmc4_cmd_pt7 {
884 nvidia,pins = "sdmmc4_cmd_pt7";
885 nvidia,function = "sdmmc4";
886 nvidia,pull = <TEGRA_PIN_PULL_UP>;
887 nvidia,tristate = <TEGRA_PIN_DISABLE>;
888 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
889 };
890
891 /* JTAG_RTCK */
892 jtag_rtck {
893 nvidia,pins = "jtag_rtck";
894 nvidia,function = "rtck";
895 nvidia,pull = <TEGRA_PIN_PULL_UP>;
896 nvidia,tristate = <TEGRA_PIN_DISABLE>;
897 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
898 };
899
900 /* LAN_DEV_OFF# */
901 ulpi_data5_po6 {
902 nvidia,pins = "ulpi_data5_po6";
903 nvidia,function = "ulpi";
904 nvidia,pull = <TEGRA_PIN_PULL_UP>;
905 nvidia,tristate = <TEGRA_PIN_DISABLE>;
906 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
907 };
908
909 /* LAN_RESET# */
910 kb_row10_ps2 {
911 nvidia,pins = "kb_row10_ps2";
912 nvidia,function = "rsvd2";
913 nvidia,pull = <TEGRA_PIN_PULL_UP>;
914 nvidia,tristate = <TEGRA_PIN_DISABLE>;
915 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
916 };
917
918 /* LAN_WAKE# */
919 ulpi_data4_po5 {
920 nvidia,pins = "ulpi_data4_po5";
921 nvidia,function = "ulpi";
922 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
923 nvidia,tristate = <TEGRA_PIN_ENABLE>;
924 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
925 };
926
927 /* MCU_INT1# */
928 pk2 {
929 nvidia,pins = "pk2";
930 nvidia,function = "rsvd1";
931 nvidia,pull = <TEGRA_PIN_PULL_UP>;
932 nvidia,tristate = <TEGRA_PIN_ENABLE>;
933 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
934 };
935
936 /* MCU_INT2# */
937 pj2 {
938 nvidia,pins = "pj2";
939 nvidia,function = "rsvd1";
940 nvidia,pull = <TEGRA_PIN_PULL_UP>;
941 nvidia,tristate = <TEGRA_PIN_ENABLE>;
942 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
943 };
944
945 /* MCU_INT3# */
946 pi5 {
947 nvidia,pins = "pi5";
948 nvidia,function = "rsvd2";
949 nvidia,pull = <TEGRA_PIN_PULL_UP>;
950 nvidia,tristate = <TEGRA_PIN_ENABLE>;
951 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
952 };
953
954 /* MCU_INT4# */
955 pj0 {
956 nvidia,pins = "pj0";
957 nvidia,function = "rsvd1";
958 nvidia,pull = <TEGRA_PIN_PULL_UP>;
959 nvidia,tristate = <TEGRA_PIN_ENABLE>;
960 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
961 };
962
963 /* MCU_RESET */
964 pbb6 {
965 nvidia,pins = "pbb6";
966 nvidia,function = "rsvd2";
967 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
968 nvidia,tristate = <TEGRA_PIN_DISABLE>;
969 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
970 };
971
972 /* MCU SPI */
973 gpio_x4_aud_px4 {
974 nvidia,pins = "gpio_x4_aud_px4";
975 nvidia,function = "spi2";
976 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
977 nvidia,tristate = <TEGRA_PIN_DISABLE>;
978 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
979 };
980 gpio_x5_aud_px5 {
981 nvidia,pins = "gpio_x5_aud_px5";
982 nvidia,function = "spi2";
983 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
984 nvidia,tristate = <TEGRA_PIN_DISABLE>;
985 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
986 };
987 gpio_x6_aud_px6 { /* MCU_CS */
988 nvidia,pins = "gpio_x6_aud_px6";
989 nvidia,function = "spi2";
990 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
991 nvidia,tristate = <TEGRA_PIN_DISABLE>;
992 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
993 };
994 gpio_x7_aud_px7 {
995 nvidia,pins = "gpio_x7_aud_px7";
996 nvidia,function = "spi2";
997 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
998 nvidia,tristate = <TEGRA_PIN_ENABLE>;
999 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1000 };
1001 gpio_w2_aud_pw2 { /* MCU_CSEZP */
1002 nvidia,pins = "gpio_w2_aud_pw2";
1003 nvidia,function = "spi2";
1004 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1005 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1006 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1007 };
1008
1009 /* PMIC_CLK_32K */
1010 clk_32k_in {
1011 nvidia,pins = "clk_32k_in";
1012 nvidia,function = "clk";
1013 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1014 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1015 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1016 };
1017
1018 /* PMIC_CPU_OC_INT */
1019 clk_32k_out_pa0 {
1020 nvidia,pins = "clk_32k_out_pa0";
1021 nvidia,function = "soc";
1022 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1023 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1024 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1025 };
1026
1027 /* PWR_I2C */
1028 pwr_i2c_scl_pz6 {
1029 nvidia,pins = "pwr_i2c_scl_pz6";
1030 nvidia,function = "i2cpwr";
1031 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1032 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1033 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1034 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
1035 };
1036 pwr_i2c_sda_pz7 {
1037 nvidia,pins = "pwr_i2c_sda_pz7";
1038 nvidia,function = "i2cpwr";
1039 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1040 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1041 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1042 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
1043 };
1044
1045 /* PWR_INT_N */
1046 pwr_int_n {
1047 nvidia,pins = "pwr_int_n";
1048 nvidia,function = "pmi";
1049 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1050 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1051 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1052 };
1053
1054 /* RESET_MOCI_CTRL */
1055 pu4 {
1056 nvidia,pins = "pu4";
1057 nvidia,function = "gmi";
1058 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1059 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1060 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1061 };
1062
1063 /* RESET_OUT_N */
1064 reset_out_n {
1065 nvidia,pins = "reset_out_n";
1066 nvidia,function = "reset_out_n";
1067 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1068 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1069 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1070 };
1071
1072 /* SHIFT_CTRL_DIR_IN */
1073 kb_row0_pr0 {
1074 nvidia,pins = "kb_row0_pr0";
1075 nvidia,function = "rsvd2";
1076 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1077 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1078 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1079 };
1080 kb_row1_pr1 {
1081 nvidia,pins = "kb_row1_pr1";
1082 nvidia,function = "rsvd2";
1083 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1084 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1085 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1086 };
1087
1088 /* Configure level-shifter as output for HDA */
1089 kb_row11_ps3 {
1090 nvidia,pins = "kb_row11_ps3";
1091 nvidia,function = "rsvd2";
1092 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1093 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1094 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1095 };
1096
1097 /* SHIFT_CTRL_DIR_OUT */
1098 kb_col5_pq5 {
1099 nvidia,pins = "kb_col5_pq5";
1100 nvidia,function = "rsvd2";
1101 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1102 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1103 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1104 };
1105 kb_col6_pq6 {
1106 nvidia,pins = "kb_col6_pq6";
1107 nvidia,function = "rsvd2";
1108 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1109 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1110 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1111 };
1112 kb_col7_pq7 {
1113 nvidia,pins = "kb_col7_pq7";
1114 nvidia,function = "rsvd2";
1115 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1116 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1117 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1118 };
1119
1120 /* SHIFT_CTRL_OE */
1121 kb_col0_pq0 {
1122 nvidia,pins = "kb_col0_pq0";
1123 nvidia,function = "rsvd2";
1124 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1125 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1126 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1127 };
1128 kb_col1_pq1 {
1129 nvidia,pins = "kb_col1_pq1";
1130 nvidia,function = "rsvd2";
1131 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1132 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1133 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1134 };
1135 kb_col2_pq2 {
1136 nvidia,pins = "kb_col2_pq2";
1137 nvidia,function = "rsvd2";
1138 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1139 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1140 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1141 };
1142 kb_col4_pq4 {
1143 nvidia,pins = "kb_col4_pq4";
1144 nvidia,function = "kbc";
1145 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1146 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1147 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1148 };
1149 kb_row2_pr2 {
1150 nvidia,pins = "kb_row2_pr2";
1151 nvidia,function = "rsvd2";
1152 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1153 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1154 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1155 };
1156
1157 /* GPIO_PI6 aka TMP451 ALERT#/THERM2# */
1158 pi6 {
1159 nvidia,pins = "pi6";
1160 nvidia,function = "rsvd1";
1161 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1162 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1163 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1164 };
1165
1166 /* TOUCH_INT */
1167 gpio_w3_aud_pw3 {
1168 nvidia,pins = "gpio_w3_aud_pw3";
1169 nvidia,function = "spi6";
1170 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1171 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1172 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1173 };
1174
1175 pc7 { /* NC */
1176 nvidia,pins = "pc7";
1177 nvidia,function = "rsvd1";
1178 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1179 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1180 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1181 };
1182 pg0 { /* NC */
1183 nvidia,pins = "pg0";
1184 nvidia,function = "rsvd1";
1185 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1186 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1187 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1188 };
1189 pg1 { /* NC */
1190 nvidia,pins = "pg1";
1191 nvidia,function = "rsvd1";
1192 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1193 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1194 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1195 };
1196 pg2 { /* NC */
1197 nvidia,pins = "pg2";
1198 nvidia,function = "rsvd1";
1199 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1200 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1201 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1202 };
1203 pg3 { /* NC */
1204 nvidia,pins = "pg3";
1205 nvidia,function = "rsvd1";
1206 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1207 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1208 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1209 };
1210 pg4 { /* NC */
1211 nvidia,pins = "pg4";
1212 nvidia,function = "rsvd1";
1213 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1214 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1215 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1216 };
1217 ph4 { /* NC */
1218 nvidia,pins = "ph4";
1219 nvidia,function = "rsvd2";
1220 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1221 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1222 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1223 };
1224 ph5 { /* NC */
1225 nvidia,pins = "ph5";
1226 nvidia,function = "rsvd2";
1227 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1228 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1229 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1230 };
1231 ph6 { /* NC */
1232 nvidia,pins = "ph6";
1233 nvidia,function = "gmi";
1234 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1235 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1236 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1237 };
1238 ph7 { /* NC */
1239 nvidia,pins = "ph7";
1240 nvidia,function = "gmi";
1241 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1242 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1243 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1244 };
1245 pi0 { /* NC */
1246 nvidia,pins = "pi0";
1247 nvidia,function = "rsvd1";
1248 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1249 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1250 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1251 };
1252 pi1 { /* NC */
1253 nvidia,pins = "pi1";
1254 nvidia,function = "rsvd1";
1255 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1256 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1257 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1258 };
1259 pi2 { /* NC */
1260 nvidia,pins = "pi2";
1261 nvidia,function = "rsvd4";
1262 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1263 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1264 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1265 };
1266 pi4 { /* NC */
1267 nvidia,pins = "pi4";
1268 nvidia,function = "gmi";
1269 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1270 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1271 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1272 };
1273 pi7 { /* NC */
1274 nvidia,pins = "pi7";
1275 nvidia,function = "rsvd1";
1276 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1277 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1278 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1279 };
1280 pk0 { /* NC */
1281 nvidia,pins = "pk0";
1282 nvidia,function = "rsvd1";
1283 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1284 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1285 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1286 };
1287 pk1 { /* NC */
1288 nvidia,pins = "pk1";
1289 nvidia,function = "rsvd4";
1290 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1291 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1292 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1293 };
1294 pk3 { /* NC */
1295 nvidia,pins = "pk3";
1296 nvidia,function = "gmi";
1297 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1298 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1299 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1300 };
1301 pk4 { /* NC */
1302 nvidia,pins = "pk4";
1303 nvidia,function = "rsvd2";
1304 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1305 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1306 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1307 };
1308 dap1_fs_pn0 { /* NC */
1309 nvidia,pins = "dap1_fs_pn0";
1310 nvidia,function = "rsvd4";
1311 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1312 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1313 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1314 };
1315 dap1_din_pn1 { /* NC */
1316 nvidia,pins = "dap1_din_pn1";
1317 nvidia,function = "rsvd4";
1318 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1319 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1320 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1321 };
1322 dap1_sclk_pn3 { /* NC */
1323 nvidia,pins = "dap1_sclk_pn3";
1324 nvidia,function = "rsvd4";
1325 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1326 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1327 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1328 };
1329 ulpi_data7_po0 { /* NC */
1330 nvidia,pins = "ulpi_data7_po0";
1331 nvidia,function = "ulpi";
1332 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1333 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1334 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1335 };
1336 ulpi_data0_po1 { /* NC */
1337 nvidia,pins = "ulpi_data0_po1";
1338 nvidia,function = "ulpi";
1339 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1340 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1341 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1342 };
1343 ulpi_data1_po2 { /* NC */
1344 nvidia,pins = "ulpi_data1_po2";
1345 nvidia,function = "ulpi";
1346 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1347 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1348 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1349 };
1350 ulpi_data2_po3 { /* NC */
1351 nvidia,pins = "ulpi_data2_po3";
1352 nvidia,function = "ulpi";
1353 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1354 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1355 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1356 };
1357 ulpi_data3_po4 { /* NC */
1358 nvidia,pins = "ulpi_data3_po4";
1359 nvidia,function = "ulpi";
1360 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1361 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1362 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1363 };
1364 ulpi_data6_po7 { /* NC */
1365 nvidia,pins = "ulpi_data6_po7";
1366 nvidia,function = "ulpi";
1367 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1368 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1369 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1370 };
1371 dap4_fs_pp4 { /* NC */
1372 nvidia,pins = "dap4_fs_pp4";
1373 nvidia,function = "rsvd4";
1374 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1375 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1376 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1377 };
1378 dap4_din_pp5 { /* NC */
1379 nvidia,pins = "dap4_din_pp5";
1380 nvidia,function = "rsvd3";
1381 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1382 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1383 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1384 };
1385 dap4_dout_pp6 { /* NC */
1386 nvidia,pins = "dap4_dout_pp6";
1387 nvidia,function = "rsvd4";
1388 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1389 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1390 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1391 };
1392 dap4_sclk_pp7 { /* NC */
1393 nvidia,pins = "dap4_sclk_pp7";
1394 nvidia,function = "rsvd3";
1395 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1396 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1397 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1398 };
1399 kb_col3_pq3 { /* NC */
1400 nvidia,pins = "kb_col3_pq3";
1401 nvidia,function = "kbc";
1402 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1403 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1404 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1405 };
1406 kb_row3_pr3 { /* NC */
1407 nvidia,pins = "kb_row3_pr3";
1408 nvidia,function = "kbc";
1409 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1410 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1411 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1412 };
1413 kb_row4_pr4 { /* NC */
1414 nvidia,pins = "kb_row4_pr4";
1415 nvidia,function = "rsvd3";
1416 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1417 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1418 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1419 };
1420 kb_row5_pr5 { /* NC */
1421 nvidia,pins = "kb_row5_pr5";
1422 nvidia,function = "rsvd3";
1423 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1424 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1425 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1426 };
1427 kb_row6_pr6 { /* NC */
1428 nvidia,pins = "kb_row6_pr6";
1429 nvidia,function = "kbc";
1430 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1431 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1432 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1433 };
1434 kb_row7_pr7 { /* NC */
1435 nvidia,pins = "kb_row7_pr7";
1436 nvidia,function = "rsvd2";
1437 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1438 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1439 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1440 };
1441 kb_row8_ps0 { /* NC */
1442 nvidia,pins = "kb_row8_ps0";
1443 nvidia,function = "rsvd2";
1444 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1445 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1446 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1447 };
1448 kb_row9_ps1 { /* NC */
1449 nvidia,pins = "kb_row9_ps1";
1450 nvidia,function = "rsvd2";
1451 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1452 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1453 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1454 };
1455 kb_row12_ps4 { /* NC */
1456 nvidia,pins = "kb_row12_ps4";
1457 nvidia,function = "rsvd2";
1458 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1459 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1460 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1461 };
1462 kb_row13_ps5 { /* NC */
1463 nvidia,pins = "kb_row13_ps5";
1464 nvidia,function = "rsvd2";
1465 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1466 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1467 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1468 };
1469 kb_row14_ps6 { /* NC */
1470 nvidia,pins = "kb_row14_ps6";
1471 nvidia,function = "rsvd2";
1472 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1473 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1474 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1475 };
1476 kb_row15_ps7 { /* NC */
1477 nvidia,pins = "kb_row15_ps7";
1478 nvidia,function = "rsvd3";
1479 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1480 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1481 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1482 };
1483 kb_row16_pt0 { /* NC */
1484 nvidia,pins = "kb_row16_pt0";
1485 nvidia,function = "rsvd2";
1486 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1487 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1488 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1489 };
1490 kb_row17_pt1 { /* NC */
1491 nvidia,pins = "kb_row17_pt1";
1492 nvidia,function = "rsvd2";
1493 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1494 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1495 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1496 };
1497 pu5 { /* NC */
1498 nvidia,pins = "pu5";
1499 nvidia,function = "gmi";
1500 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1501 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1502 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1503 };
1504 pv0 { /* NC */
1505 nvidia,pins = "pv0";
1506 nvidia,function = "rsvd1";
1507 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1508 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1509 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1510 };
1511 pv1 { /* NC */
1512 nvidia,pins = "pv1";
1513 nvidia,function = "rsvd1";
1514 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1515 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1516 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1517 };
1518 gpio_x1_aud_px1 { /* NC */
1519 nvidia,pins = "gpio_x1_aud_px1";
1520 nvidia,function = "rsvd2";
1521 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1522 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1523 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1524 };
1525 gpio_x3_aud_px3 { /* NC */
1526 nvidia,pins = "gpio_x3_aud_px3";
1527 nvidia,function = "rsvd4";
1528 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1529 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1530 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1531 };
1532 pbb7 { /* NC */
1533 nvidia,pins = "pbb7";
1534 nvidia,function = "rsvd2";
1535 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1536 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1537 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1538 };
1539 pcc1 { /* NC */
1540 nvidia,pins = "pcc1";
1541 nvidia,function = "rsvd2";
1542 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1543 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1544 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1545 };
1546 pcc2 { /* NC */
1547 nvidia,pins = "pcc2";
1548 nvidia,function = "rsvd2";
1549 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1550 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1551 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1552 };
1553 clk3_req_pee1 { /* NC */
1554 nvidia,pins = "clk3_req_pee1";
1555 nvidia,function = "rsvd2";
1556 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1557 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1558 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1559 };
1560 dap_mclk1_req_pee2 { /* NC */
1561 nvidia,pins = "dap_mclk1_req_pee2";
1562 nvidia,function = "rsvd4";
1563 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1564 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1565 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1566 };
1567 /*
1568 * Leave SDMMC3_CLK_LB_OUT muxed as SDMMC3 with output
1569 * driver enabled aka not tristated and input driver
1570 * enabled as well as it features some magic properties
1571 * even though the external loopback is disabled and the
1572 * internal loopback used as per
1573 * SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1
1574 * bits being set to 0xfffd according to the TRM!
1575 */
1576 sdmmc3_clk_lb_out_pee4 { /* NC */
1577 nvidia,pins = "sdmmc3_clk_lb_out_pee4";
1578 nvidia,function = "sdmmc3";
1579 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1580 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1581 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1582 };
1583 };
1584 };
1585
1586 /* Apalis UART1 */
1587 serial@70006000 {
1588 status = "okay";
1589 };
1590
1591 /* Apalis UART2 */
1592 serial@70006040 {
1593 compatible = "nvidia,tegra124-hsuart";
1594 status = "okay";
1595 };
1596
1597 /* Apalis UART3 */
1598 serial@70006200 {
1599 compatible = "nvidia,tegra124-hsuart";
1600 status = "okay";
1601 };
1602
1603 /* Apalis UART4 */
1604 serial@70006300 {
1605 compatible = "nvidia,tegra124-hsuart";
1606 status = "okay";
1607 };
1608
1609 pwm@7000a000 {
1610 status = "okay";
1611 };
1612
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -0700[diff] [blame]1613 /*
1614 * GEN1_I2C: I2C1_SDA/SCL on MXM3 pin 209/211 (e.g. RTC on carrier
1615 * board)
1616 */
1617 i2c@7000c000 {
1618 status = "okay";
Marcel Ziswiler06a1ad72017-07-20 14:57:44 +0200[diff] [blame]1619 clock-frequency = <400000>;
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -0700[diff] [blame]1620
1621 pcie-switch@58 {
1622 compatible = "plx,pex8605";
1623 reg = <0x58>;
1624 };
1625
1626 /* M41T0M6 real time clock on carrier board */
1627 rtc@68 {
1628 compatible = "st,m41t00";
1629 reg = <0x68>;
1630 };
1631 };
1632
1633 /*
1634 * GEN2_I2C: I2C2_SDA/SCL (DDC) on MXM3 pin 205/207 (e.g. display EDID)
1635 */
1636 hdmi_ddc: i2c@7000c400 {
1637 status = "okay";
Marcel Ziswiler06a1ad72017-07-20 14:57:44 +0200[diff] [blame]1638 clock-frequency = <10000>;
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -0700[diff] [blame]1639 };
1640
1641 /*
1642 * CAM_I2C: I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor
1643 * on carrier board)
1644 */
1645 i2c@7000c500 {
1646 status = "okay";
Marcel Ziswiler06a1ad72017-07-20 14:57:44 +0200[diff] [blame]1647 clock-frequency = <400000>;
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -0700[diff] [blame]1648 };
1649
1650 /* I2C4 (DDC): unused */
1651
1652 /* PWR_I2C: power I2C to audio codec, PMIC and temperature sensor */
1653 i2c@7000d000 {
1654 status = "okay";
1655 clock-frequency = <400000>;
1656
1657 /* SGTL5000 audio codec */
1658 sgtl5000: codec@a {
1659 compatible = "fsl,sgtl5000";
1660 reg = <0x0a>;
1661 VDDA-supply = <&reg_3v3>;
1662 VDDIO-supply = <&vddio_1v8>;
1663 clocks = <&tegra_car TEGRA124_CLK_EXTERN1>;
1664 };
1665
1666 pmic: pmic@40 {
1667 compatible = "ams,as3722";
1668 reg = <0x40>;
1669 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
1670 ams,system-power-controller;
1671 #interrupt-cells = <2>;
1672 interrupt-controller;
1673 gpio-controller;
1674 #gpio-cells = <2>;
1675 pinctrl-names = "default";
1676 pinctrl-0 = <&as3722_default>;
1677
1678 as3722_default: pinmux {
1679 gpio2_7 {
1680 pins = "gpio2", /* PWR_EN_+V3.3 */
1681 "gpio7"; /* +V1.6_LPO */
1682 function = "gpio";
1683 bias-pull-up;
1684 };
1685
Marcel Ziswiler203ed322018-05-08 17:34:07 +0200[diff] [blame]1686 gpio0_1_3_4_5_6 {
1687 pins = "gpio0", "gpio1", "gpio3",
1688 "gpio4", "gpio5", "gpio6";
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -0700[diff] [blame]1689 bias-high-impedance;
1690 };
1691 };
1692
1693 regulators {
1694 vsup-sd2-supply = <&reg_3v3>;
1695 vsup-sd3-supply = <&reg_3v3>;
1696 vsup-sd4-supply = <&reg_3v3>;
1697 vsup-sd5-supply = <&reg_3v3>;
1698 vin-ldo0-supply = <&vddio_ddr_1v35>;
1699 vin-ldo1-6-supply = <&reg_3v3>;
1700 vin-ldo2-5-7-supply = <&vddio_1v8>;
1701 vin-ldo3-4-supply = <&reg_3v3>;
1702 vin-ldo9-10-supply = <&reg_3v3>;
1703 vin-ldo11-supply = <&reg_3v3>;
1704
1705 vdd_cpu: sd0 {
1706 regulator-name = "+VDD_CPU_AP";
1707 regulator-min-microvolt = <700000>;
1708 regulator-max-microvolt = <1400000>;
1709 regulator-min-microamp = <3500000>;
1710 regulator-max-microamp = <3500000>;
1711 regulator-always-on;
1712 regulator-boot-on;
1713 ams,ext-control = <2>;
1714 };
1715
1716 sd1 {
1717 regulator-name = "+VDD_CORE";
1718 regulator-min-microvolt = <700000>;
1719 regulator-max-microvolt = <1350000>;
1720 regulator-min-microamp = <2500000>;
1721 regulator-max-microamp = <4000000>;
1722 regulator-always-on;
1723 regulator-boot-on;
1724 ams,ext-control = <1>;
1725 };
1726
1727 vddio_ddr_1v35: sd2 {
1728 regulator-name =
1729 "+V1.35_VDDIO_DDR(sd2)";
1730 regulator-min-microvolt = <1350000>;
1731 regulator-max-microvolt = <1350000>;
1732 regulator-always-on;
1733 regulator-boot-on;
1734 };
1735
1736 sd3 {
1737 regulator-name =
1738 "+V1.35_VDDIO_DDR(sd3)";
1739 regulator-min-microvolt = <1350000>;
1740 regulator-max-microvolt = <1350000>;
1741 regulator-always-on;
1742 regulator-boot-on;
1743 };
1744
1745 vdd_1v05: sd4 {
1746 regulator-name = "+V1.05";
1747 regulator-min-microvolt = <1050000>;
1748 regulator-max-microvolt = <1050000>;
1749 };
1750
1751 vddio_1v8: sd5 {
1752 regulator-name = "+V1.8";
1753 regulator-min-microvolt = <1800000>;
1754 regulator-max-microvolt = <1800000>;
1755 regulator-boot-on;
1756 regulator-always-on;
1757 };
1758
1759 vdd_gpu: sd6 {
1760 regulator-name = "+VDD_GPU_AP";
1761 regulator-min-microvolt = <650000>;
1762 regulator-max-microvolt = <1200000>;
1763 regulator-min-microamp = <3500000>;
1764 regulator-max-microamp = <3500000>;
1765 regulator-boot-on;
1766 regulator-always-on;
1767 };
1768
1769 avdd_1v05: ldo0 {
1770 regulator-name = "+V1.05_AVDD";
1771 regulator-min-microvolt = <1050000>;
1772 regulator-max-microvolt = <1050000>;
1773 regulator-boot-on;
1774 regulator-always-on;
1775 ams,ext-control = <1>;
1776 };
1777
1778 vddio_sdmmc1: ldo1 {
1779 regulator-name = "VDDIO_SDMMC1";
1780 regulator-min-microvolt = <1800000>;
1781 regulator-max-microvolt = <3300000>;
1782 };
1783
1784 ldo2 {
1785 regulator-name = "+V1.2";
1786 regulator-min-microvolt = <1200000>;
1787 regulator-max-microvolt = <1200000>;
1788 regulator-boot-on;
1789 regulator-always-on;
1790 };
1791
1792 ldo3 {
1793 regulator-name = "+V1.05_RTC";
1794 regulator-min-microvolt = <1000000>;
1795 regulator-max-microvolt = <1000000>;
1796 regulator-boot-on;
1797 regulator-always-on;
1798 ams,enable-tracking;
1799 };
1800
1801 /* 1.8V for LVDS, 3.3V for eDP */
1802 ldo4 {
1803 regulator-name = "AVDD_LVDS0_PLL";
1804 regulator-min-microvolt = <1800000>;
1805 regulator-max-microvolt = <1800000>;
1806 };
1807
1808 /* LDO5 not used */
1809
1810 vddio_sdmmc3: ldo6 {
1811 regulator-name = "VDDIO_SDMMC3";
1812 regulator-min-microvolt = <1800000>;
1813 regulator-max-microvolt = <3300000>;
1814 };
1815
1816 /* LDO7 not used */
1817
1818 ldo9 {
1819 regulator-name = "+V3.3_ETH(ldo9)";
1820 regulator-min-microvolt = <3300000>;
1821 regulator-max-microvolt = <3300000>;
1822 regulator-always-on;
1823 };
1824
1825 ldo10 {
1826 regulator-name = "+V3.3_ETH(ldo10)";
1827 regulator-min-microvolt = <3300000>;
1828 regulator-max-microvolt = <3300000>;
1829 regulator-always-on;
1830 };
1831
1832 ldo11 {
1833 regulator-name = "+V1.8_VPP_FUSE";
1834 regulator-min-microvolt = <1800000>;
1835 regulator-max-microvolt = <1800000>;
1836 };
1837 };
1838 };
1839
1840 /*
1841 * TMP451 temperature sensor
1842 * Note: THERM_N directly connected to AS3722 PMIC THERM
1843 */
1844 temperature-sensor@4c {
1845 compatible = "ti,tmp451";
1846 reg = <0x4c>;
1847 interrupt-parent = <&gpio>;
1848 interrupts = <TEGRA_GPIO(I, 6) IRQ_TYPE_LEVEL_LOW>;
1849 #thermal-sensor-cells = <1>;
1850 };
1851 };
1852
1853 /* SPI1: Apalis SPI1 */
1854 spi@7000d400 {
1855 status = "okay";
1856 spi-max-frequency = <50000000>;
1857
1858 spidev0: spidev@0 {
1859 compatible = "spidev";
1860 reg = <0>;
1861 spi-max-frequency = <50000000>;
1862 };
1863 };
1864
1865 /* SPI2: MCU SPI */
1866 spi@7000d600 {
1867 status = "okay";
1868 spi-max-frequency = <25000000>;
1869 };
1870
1871 /* SPI4: Apalis SPI2 */
1872 spi@7000da00 {
1873 status = "okay";
1874 spi-max-frequency = <50000000>;
1875
1876 spidev1: spidev@0 {
1877 compatible = "spidev";
1878 reg = <0>;
1879 spi-max-frequency = <50000000>;
1880 };
1881 };
1882
1883 pmc@7000e400 {
1884 nvidia,invert-interrupt;
1885 nvidia,suspend-mode = <1>;
1886 nvidia,cpu-pwr-good-time = <500>;
1887 nvidia,cpu-pwr-off-time = <300>;
1888 nvidia,core-pwr-good-time = <641 3845>;
1889 nvidia,core-pwr-off-time = <61036>;
1890 nvidia,core-power-req-active-high;
1891 nvidia,sys-clock-req-active-high;
1892
1893 /* Set power_off bit in ResetControl register of AS3722 PMIC */
1894 i2c-thermtrip {
1895 nvidia,i2c-controller-id = <4>;
1896 nvidia,bus-addr = <0x40>;
1897 nvidia,reg-addr = <0x36>;
1898 nvidia,reg-data = <0x2>;
1899 };
1900 };
1901
1902 /* Apalis Serial ATA */
1903 sata@70020000 {
1904 avdd-supply = <&vdd_1v05>;
1905 hvdd-supply = <&reg_3v3>;
1906 vddio-supply = <&vdd_1v05>;
1907 status = "okay";
1908 };
1909
1910 hda@70030000 {
1911 status = "okay";
1912 };
1913
1914 usb@70090000 {
1915 /* USBO1, USBO1 (SS), USBH2, USBH4 and USBH4 (SS) */
1916 avddio-pex-supply = <&vdd_1v05>;
1917 avdd-pll-erefe-supply = <&avdd_1v05>;
1918 avdd-pll-utmip-supply = <&vddio_1v8>;
1919 avdd-usb-ss-pll-supply = <&vdd_1v05>;
1920 avdd-usb-supply = <&reg_3v3>;
1921 dvddio-pex-supply = <&vdd_1v05>;
1922 hvdd-usb-ss-pll-e-supply = <&reg_3v3>;
1923 hvdd-usb-ss-supply = <&reg_3v3>;
1924 status = "okay";
1925 };
1926
1927 padctl@7009f000 {
1928 pinctrl-0 = <&padctl_default>;
1929 pinctrl-names = "default";
1930
1931 padctl_default: pinmux {
1932 usb3 {
1933 nvidia,lanes = "pcie-0", "pcie-1";
1934 nvidia,function = "usb3";
1935 nvidia,iddq = <0>;
1936 };
1937
1938 pcie {
1939 nvidia,lanes = "pcie-2", "pcie-3",
1940 "pcie-4";
1941 nvidia,function = "pcie";
1942 nvidia,iddq = <0>;
1943 };
1944
1945 sata {
1946 nvidia,lanes = "sata-0";
1947 nvidia,function = "sata";
1948 nvidia,iddq = <0>;
1949 };
1950 };
1951 };
1952
1953 /* Apalis MMC1 */
1954 sdhci@700b0000 {
1955 status = "okay";
1956 /* MMC1_CD# */
1957 cd-gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>;
1958 bus-width = <4>;
1959 vqmmc-supply = <&vddio_sdmmc1>;
1960 };
1961
1962 /* Apalis SD1 */
1963 sdhci@700b0400 {
1964 status = "okay";
1965 /* SD1_CD# */
1966 cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
1967 bus-width = <4>;
1968 vqmmc-supply = <&vddio_sdmmc3>;
1969 };
1970
1971 /* eMMC */
1972 sdhci@700b0600 {
1973 status = "okay";
1974 bus-width = <8>;
1975 non-removable;
1976 };
1977
1978 /* CPU DFLL clock */
1979 clock@70110000 {
1980 status = "okay";
1981 vdd-cpu-supply = <&vdd_cpu>;
1982 nvidia,i2c-fs-rate = <400000>;
1983 };
1984
1985 ahub@70300000 {
1986 i2s@70301200 {
1987 status = "okay";
1988 };
1989 };
1990
1991 /* EHCI instance 0: USB1_DP/N -> USBO1_DP/N */
1992 usb@7d000000 {
1993 status = "okay";
1994 dr_mode = "otg";
1995 };
1996
1997 usb-phy@7d000000 {
1998 status = "okay";
1999 vbus-supply = <&reg_usbo1_vbus>;
2000 };
2001
2002 /* EHCI instance 1: USB2_DP/N -> USBH2_DP/N */
2003 usb@7d004000 {
2004 status = "okay";
2005 };
2006
2007 usb-phy@7d004000 {
2008 status = "okay";
2009 vbus-supply = <&reg_usbh_vbus>;
2010 };
2011
2012 /* EHCI instance 2: USB3_DP/N -> USBH4_DP/N */
2013 usb@7d008000 {
2014 status = "okay";
2015 };
2016
2017 usb-phy@7d008000 {
2018 status = "okay";
2019 vbus-supply = <&reg_usbh_vbus>;
2020 };
2021
2022 backlight: backlight {
2023 compatible = "pwm-backlight";
2024 /* BKL1_PWM */
2025 pwms = <&pwm 3 5000000>;
2026 brightness-levels = <255 231 223 207 191 159 127 0>;
2027 default-brightness-level = <6>;
2028 /* BKL1_ON */
2029 enable-gpios = <&gpio TEGRA_GPIO(BB, 5) GPIO_ACTIVE_HIGH>;
2030 };
2031
2032 clocks {
2033 compatible = "simple-bus";
2034 #address-cells = <1>;
2035 #size-cells = <0>;
2036
2037 clk32k_in: clock@0 {
2038 compatible = "fixed-clock";
2039 reg = <0>;
2040 #clock-cells = <0>;
2041 clock-frequency = <32768>;
2042 };
2043 };
2044
2045 cpus {
2046 cpu@0 {
2047 vdd-cpu-supply = <&vdd_cpu>;
2048 };
2049 };
2050
2051 gpio-keys {
2052 compatible = "gpio-keys";
2053
2054 wakeup {
2055 label = "WAKE1_MICO";
2056 gpios = <&gpio TEGRA_GPIO(DD, 3) GPIO_ACTIVE_LOW>;
2057 linux,code = <KEY_WAKEUP>;
2058 debounce-interval = <10>;
2059 wakeup-source;
2060 };
2061 };
2062
2063 reg_1v05_avdd_hdmi_pll: regulator-1v05-avdd-hdmi-pll {
2064 compatible = "regulator-fixed";
2065 regulator-name = "+V1.05_AVDD_HDMI_PLL";
2066 regulator-min-microvolt = <1050000>;
2067 regulator-max-microvolt = <1050000>;
2068 gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>;
2069 vin-supply = <&vdd_1v05>;
2070 };
2071
2072 reg_3v3_mxm: regulator-3v3-mxm {
2073 compatible = "regulator-fixed";
2074 regulator-name = "+V3.3_MXM";
2075 regulator-min-microvolt = <3300000>;
2076 regulator-max-microvolt = <3300000>;
2077 regulator-always-on;
2078 regulator-boot-on;
2079 };
2080
2081 reg_3v3: regulator-3v3 {
2082 compatible = "regulator-fixed";
2083 regulator-name = "+V3.3";
2084 regulator-min-microvolt = <3300000>;
2085 regulator-max-microvolt = <3300000>;
2086 regulator-always-on;
2087 regulator-boot-on;
2088 /* PWR_EN_+V3.3 */
2089 gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
2090 enable-active-high;
2091 vin-supply = <&reg_3v3_mxm>;
2092 };
2093
2094 reg_3v3_avdd_hdmi: regulator-3v3-avdd-hdmi {
2095 compatible = "regulator-fixed";
2096 regulator-name = "+V3.3_AVDD_HDMI";
2097 regulator-min-microvolt = <3300000>;
2098 regulator-max-microvolt = <3300000>;
2099 vin-supply = <&vdd_1v05>;
2100 };
2101
2102 reg_5v0: regulator-5v0 {
2103 compatible = "regulator-fixed";
2104 regulator-name = "5V_SW";
2105 regulator-min-microvolt = <5000000>;
2106 regulator-max-microvolt = <5000000>;
2107 };
2108
2109 /* USBO1_EN */
2110 reg_usbo1_vbus: regulator-usbo1-vbus {
2111 compatible = "regulator-fixed";
2112 regulator-name = "VCC_USBO1";
2113 regulator-min-microvolt = <5000000>;
2114 regulator-max-microvolt = <5000000>;
2115 gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
2116 enable-active-high;
2117 vin-supply = <&reg_5v0>;
2118 };
2119
2120 /* USBH_EN */
2121 reg_usbh_vbus: regulator-usbh-vbus {
2122 compatible = "regulator-fixed";
2123 regulator-name = "VCC_USBH(2A|2C|2D|3|4)";
2124 regulator-min-microvolt = <5000000>;
2125 regulator-max-microvolt = <5000000>;
2126 gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>;
2127 enable-active-high;
2128 vin-supply = <&reg_5v0>;
2129 };
2130
2131 sound {
2132 compatible = "toradex,tegra-audio-sgtl5000-apalis_tk1",
2133 "nvidia,tegra-audio-sgtl5000";
2134 nvidia,model = "Toradex Apalis TK1";
2135 nvidia,audio-routing =
2136 "Headphone Jack", "HP_OUT",
2137 "LINE_IN", "Line In Jack",
2138 "MIC_IN", "Mic Jack";
2139 nvidia,i2s-controller = <&tegra_i2s2>;
2140 nvidia,audio-codec = <&sgtl5000>;
2141 clocks = <&tegra_car TEGRA124_CLK_PLL_A>,
2142 <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
2143 <&tegra_car TEGRA124_CLK_EXTERN1>;
2144 clock-names = "pll_a", "pll_a_out0", "mclk";
2145 };
2146
2147 thermal-zones {
2148 cpu {
2149 trips {
2150 trip@0 {
2151 temperature = <101000>;
2152 hysteresis = <0>;
2153 type = "critical";
2154 };
2155 };
2156
2157 cooling-maps {
2158 /*
2159 * There are currently no cooling maps because
2160 * there are no cooling devices
2161 */
2162 };
2163 };
2164
2165 mem {
2166 trips {
2167 trip@0 {
2168 temperature = <101000>;
2169 hysteresis = <0>;
2170 type = "critical";
2171 };
2172 };
2173
2174 cooling-maps {
2175 /*
2176 * There are currently no cooling maps because
2177 * there are no cooling devices
2178 */
2179 };
2180 };
2181
2182 gpu {
2183 trips {
2184 trip@0 {
2185 temperature = <101000>;
2186 hysteresis = <0>;
2187 type = "critical";
2188 };
2189 };
2190
2191 cooling-maps {
2192 /*
2193 * There are currently no cooling maps because
2194 * there are no cooling devices
2195 */
2196 };
2197 };
2198 };
2199};