| wdenk | ef3386f | 2004-10-10 21:27:30 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2004, Psyent Corporation <www.psyent.com> |
| 3 | * Scott McNutt <smcnutt@psyent.com> |
| 4 | * |
| Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 5 | * SPDX-License-Identifier: GPL-2.0+ |
| wdenk | ef3386f | 2004-10-10 21:27:30 +0000 | [diff] [blame] | 6 | */ |
| 7 | |
| Thomas Chou | 0f9763f | 2014-08-25 17:09:07 +0800 | [diff] [blame] | 8 | #ifndef __ASM_NIOS2_H__ |
| 9 | #define __ASM_NIOS2_H__ |
| wdenk | ef3386f | 2004-10-10 21:27:30 +0000 | [diff] [blame] | 10 | |
| 11 | /*------------------------------------------------------------------------ |
| 12 | * Control registers -- use with wrctl() & rdctl() |
| 13 | *----------------------------------------------------------------------*/ |
| 14 | #define CTL_STATUS 0 /* Processor status reg */ |
| 15 | #define CTL_ESTATUS 1 /* Exception status reg */ |
| 16 | #define CTL_BSTATUS 2 /* Break status reg */ |
| 17 | #define CTL_IENABLE 3 /* Interrut enable reg */ |
| 18 | #define CTL_IPENDING 4 /* Interrut pending reg */ |
| 19 | |
| 20 | /*------------------------------------------------------------------------ |
| 21 | * Access to control regs |
| 22 | *----------------------------------------------------------------------*/ |
| wdenk | ef3386f | 2004-10-10 21:27:30 +0000 | [diff] [blame] | 23 | |
| Thomas Chou | fa9a2dc | 2012-11-09 14:29:15 +0800 | [diff] [blame] | 24 | #define rdctl(reg) __builtin_rdctl(reg) |
| 25 | #define wrctl(reg, val) __builtin_wrctl(reg, val) |
| wdenk | ef3386f | 2004-10-10 21:27:30 +0000 | [diff] [blame] | 26 | |
| 27 | /*------------------------------------------------------------------------ |
| 28 | * Control reg bit masks |
| 29 | *----------------------------------------------------------------------*/ |
| 30 | #define STATUS_IE (1<<0) /* Interrupt enable */ |
| 31 | #define STATUS_U (1<<1) /* User-mode */ |
| 32 | |
| 33 | /*------------------------------------------------------------------------ |
| 34 | * Bit-31 Cache bypass -- only valid for data access. When data cache |
| 35 | * is not implemented, bit 31 is ignored for compatibility. |
| 36 | *----------------------------------------------------------------------*/ |
| 37 | #define CACHE_BYPASS(a) ((a) | 0x80000000) |
| 38 | #define CACHE_NO_BYPASS(a) ((a) & ~0x80000000) |
| 39 | |
| Thomas Chou | 0f9763f | 2014-08-25 17:09:07 +0800 | [diff] [blame] | 40 | #endif /* __ASM_NIOS2_H__ */ |