Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / 34cf959862159d54a2cb7d6010a497701cf627f0 / . / board / sandburst / karef / init.S
blob: b1d47a4c75a665e55a81a4e496e6408e58f64f2f [file] [log] [blame]
Stefan Roese5ff4c3f2005-08-15 12:31:23 +0200[diff] [blame]1/*
2* Copyright (C) 2005 Sandburst Corporation
3*
4* See file CREDITS for list of people who contributed to this
5* project.
6*
7* This program is free software; you can redistribute it and/or
8* modify it under the terms of the GNU General Public License as
9* published by the Free Software Foundation; either version 2 of
10* the License, or (at your option) any later version.
11*
12* This program is distributed in the hope that it will be useful,
13* but WITHOUT ANY WARRANTY; without even the implied warranty of
14* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15* GNU General Public License for more details.
16*
17* You should have received a copy of the GNU General Public License
18* along with this program; if not, write to the Free Software
19* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20* MA 02111-1307 USA
21*/
22/*
23 * Ported from Ebony init.S by Travis B. Sawyer
24 */
25
26#include <ppc_asm.tmpl>
27#include <config.h>
28
29/* General */
30#define TLB_VALID 0x00000200
31
32/* Supported page sizes */
33
34#define SZ_1K 0x00000000
35#define SZ_4K 0x00000010
36#define SZ_16K 0x00000020
37#define SZ_64K 0x00000030
38#define SZ_256K 0x00000040
39#define SZ_1M 0x00000050
40#define SZ_16M 0x00000070
41#define SZ_256M 0x00000090
42
43/* Storage attributes */
44#define SA_W 0x00000800 /* Write-through */
45#define SA_I 0x00000400 /* Caching inhibited */
46#define SA_M 0x00000200 /* Memory coherence */
47#define SA_G 0x00000100 /* Guarded */
48#define SA_E 0x00000080 /* Endian */
49
50/* Access control */
51#define AC_X 0x00000024 /* Execute */
52#define AC_W 0x00000012 /* Write */
53#define AC_R 0x00000009 /* Read */
54
55/* Some handy macros */
56
57#define EPN(e) ((e) & 0xfffffc00)
58#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) )
59#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) )
60#define TLB2(a) ( (a)&0x00000fbf )
61
62#define tlbtab_start\
63 mflr r1 ;\
64 bl 0f ;
65
66#define tlbtab_end\
67 .long 0, 0, 0 ; \
680: mflr r0 ; \
69 mtlr r1 ; \
70 blr ;
71
72#define tlbentry(epn,sz,rpn,erpn,attr)\
73 .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
74
75
76/**************************************************************************
77 * TLB TABLE
78 *
79 * This table is used by the cpu boot code to setup the initial tlb
80 * entries. Rather than make broad assumptions in the cpu source tree,
81 * this table lets each board set things up however they like.
82 *
83 * Pointer to the table is returned in r1
84 *
85 *************************************************************************/
86
87 .section .bootpg,"ax"
88 .globl tlbtab
89
90tlbtab:
91 tlbtab_start
92 tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
93 tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I)
94 tlbentry( CFG_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
95 tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
96 tlbentry( CFG_SDRAM_BASE+0x10000000, SZ_256M, 0x10000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
97 tlbentry( CFG_SDRAM_BASE+0x20000000, SZ_256M, 0x20000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
98 tlbentry( CFG_SDRAM_BASE+0x30000000, SZ_256M, 0x30000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
99 tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I )
100 tlbentry( CFG_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I )
101 tlbtab_end