Tom Rini | 8b0c8a1 | 2018-05-06 18:27:01 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause |
Patrick Delaunay | 85b5397 | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2018, STMicroelectronics - All Rights Reserved |
Patrick Delaunay | 85b5397 | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 4 | */ |
| 5 | #include <common.h> |
| 6 | #include <clk.h> |
Simon Glass | 1d91ba7 | 2019-11-14 12:57:37 -0700 | [diff] [blame] | 7 | #include <cpu_func.h> |
Patrick Delaunay | 82168e8 | 2018-05-17 14:50:46 +0200 | [diff] [blame] | 8 | #include <debug_uart.h> |
Simon Glass | 5e6201b | 2019-08-01 09:46:51 -0600 | [diff] [blame] | 9 | #include <env.h> |
Simon Glass | 9758973 | 2020-05-10 11:40:02 -0600 | [diff] [blame] | 10 | #include <init.h> |
Simon Glass | 0f2af88 | 2020-05-10 11:40:05 -0600 | [diff] [blame] | 11 | #include <log.h> |
Patrick Delaunay | f3674a4 | 2018-05-17 15:24:07 +0200 | [diff] [blame] | 12 | #include <misc.h> |
Simon Glass | 274e0b0 | 2020-05-10 11:39:56 -0600 | [diff] [blame] | 13 | #include <net.h> |
Patrick Delaunay | 85b5397 | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 14 | #include <asm/io.h> |
Patrick Delaunay | 6332c04 | 2020-06-16 18:27:44 +0200 | [diff] [blame] | 15 | #include <asm/arch/bsec.h> |
Patrick Delaunay | 85b5397 | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 16 | #include <asm/arch/stm32.h> |
Patrick Delaunay | 01e3afe | 2018-03-19 19:09:21 +0100 | [diff] [blame] | 17 | #include <asm/arch/sys_proto.h> |
Patrick Delaunay | f3674a4 | 2018-05-17 15:24:07 +0200 | [diff] [blame] | 18 | #include <dm/device.h> |
Patrick Delaunay | c5d1565 | 2018-03-20 10:54:53 +0100 | [diff] [blame] | 19 | #include <dm/uclass.h> |
Simon Glass | 4dcacfc | 2020-05-10 11:40:13 -0600 | [diff] [blame] | 20 | #include <linux/bitops.h> |
Patrick Delaunay | 85b5397 | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 21 | |
Patrick Delaunay | 58e9553 | 2018-03-19 19:09:20 +0100 | [diff] [blame] | 22 | /* RCC register */ |
| 23 | #define RCC_TZCR (STM32_RCC_BASE + 0x00) |
| 24 | #define RCC_DBGCFGR (STM32_RCC_BASE + 0x080C) |
| 25 | #define RCC_BDCR (STM32_RCC_BASE + 0x0140) |
| 26 | #define RCC_MP_APB5ENSETR (STM32_RCC_BASE + 0x0208) |
Patrick Delaunay | d4ca35c | 2019-02-27 17:01:26 +0100 | [diff] [blame] | 27 | #define RCC_MP_AHB5ENSETR (STM32_RCC_BASE + 0x0210) |
Patrick Delaunay | 58e9553 | 2018-03-19 19:09:20 +0100 | [diff] [blame] | 28 | #define RCC_BDCR_VSWRST BIT(31) |
| 29 | #define RCC_BDCR_RTCSRC GENMASK(17, 16) |
| 30 | #define RCC_DBGCFGR_DBGCKEN BIT(8) |
Patrick Delaunay | 85b5397 | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 31 | |
Patrick Delaunay | 58e9553 | 2018-03-19 19:09:20 +0100 | [diff] [blame] | 32 | /* Security register */ |
Patrick Delaunay | 85b5397 | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 33 | #define ETZPC_TZMA1_SIZE (STM32_ETZPC_BASE + 0x04) |
| 34 | #define ETZPC_DECPROT0 (STM32_ETZPC_BASE + 0x10) |
| 35 | |
| 36 | #define TZC_GATE_KEEPER (STM32_TZC_BASE + 0x008) |
| 37 | #define TZC_REGION_ATTRIBUTE0 (STM32_TZC_BASE + 0x110) |
| 38 | #define TZC_REGION_ID_ACCESS0 (STM32_TZC_BASE + 0x114) |
| 39 | |
| 40 | #define TAMP_CR1 (STM32_TAMP_BASE + 0x00) |
| 41 | |
| 42 | #define PWR_CR1 (STM32_PWR_BASE + 0x00) |
Fabien Dessenne | 9ebbdc9 | 2019-10-30 14:38:30 +0100 | [diff] [blame] | 43 | #define PWR_MCUCR (STM32_PWR_BASE + 0x14) |
Patrick Delaunay | 85b5397 | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 44 | #define PWR_CR1_DBP BIT(8) |
Fabien Dessenne | 9ebbdc9 | 2019-10-30 14:38:30 +0100 | [diff] [blame] | 45 | #define PWR_MCUCR_SBF BIT(6) |
Patrick Delaunay | 85b5397 | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 46 | |
Patrick Delaunay | 58e9553 | 2018-03-19 19:09:20 +0100 | [diff] [blame] | 47 | /* DBGMCU register */ |
Patrick Delaunay | 01e3afe | 2018-03-19 19:09:21 +0100 | [diff] [blame] | 48 | #define DBGMCU_IDC (STM32_DBGMCU_BASE + 0x00) |
Patrick Delaunay | 58e9553 | 2018-03-19 19:09:20 +0100 | [diff] [blame] | 49 | #define DBGMCU_APB4FZ1 (STM32_DBGMCU_BASE + 0x2C) |
| 50 | #define DBGMCU_APB4FZ1_IWDG2 BIT(2) |
Patrick Delaunay | 01e3afe | 2018-03-19 19:09:21 +0100 | [diff] [blame] | 51 | #define DBGMCU_IDC_DEV_ID_MASK GENMASK(11, 0) |
| 52 | #define DBGMCU_IDC_DEV_ID_SHIFT 0 |
| 53 | #define DBGMCU_IDC_REV_ID_MASK GENMASK(31, 16) |
| 54 | #define DBGMCU_IDC_REV_ID_SHIFT 16 |
Patrick Delaunay | 85b5397 | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 55 | |
Patrick Delaunay | d4ca35c | 2019-02-27 17:01:26 +0100 | [diff] [blame] | 56 | /* GPIOZ registers */ |
| 57 | #define GPIOZ_SECCFGR 0x54004030 |
| 58 | |
Patrick Delaunay | c5d1565 | 2018-03-20 10:54:53 +0100 | [diff] [blame] | 59 | /* boot interface from Bootrom |
| 60 | * - boot instance = bit 31:16 |
| 61 | * - boot device = bit 15:0 |
| 62 | */ |
| 63 | #define BOOTROM_PARAM_ADDR 0x2FFC0078 |
| 64 | #define BOOTROM_MODE_MASK GENMASK(15, 0) |
| 65 | #define BOOTROM_MODE_SHIFT 0 |
| 66 | #define BOOTROM_INSTANCE_MASK GENMASK(31, 16) |
| 67 | #define BOOTROM_INSTANCE_SHIFT 16 |
| 68 | |
Patrick Delaunay | 45c82d2 | 2019-02-27 17:01:13 +0100 | [diff] [blame] | 69 | /* Device Part Number (RPN) = OTP_DATA1 lower 8 bits */ |
| 70 | #define RPN_SHIFT 0 |
| 71 | #define RPN_MASK GENMASK(7, 0) |
| 72 | |
| 73 | /* Package = bit 27:29 of OTP16 |
| 74 | * - 100: LBGA448 (FFI) => AA = LFBGA 18x18mm 448 balls p. 0.8mm |
| 75 | * - 011: LBGA354 (LCI) => AB = LFBGA 16x16mm 359 balls p. 0.8mm |
| 76 | * - 010: TFBGA361 (FFC) => AC = TFBGA 12x12mm 361 balls p. 0.5mm |
| 77 | * - 001: TFBGA257 (LCC) => AD = TFBGA 10x10mm 257 balls p. 0.5mm |
| 78 | * - others: Reserved |
| 79 | */ |
| 80 | #define PKG_SHIFT 27 |
| 81 | #define PKG_MASK GENMASK(2, 0) |
| 82 | |
Patrick Delaunay | 8e6985b | 2020-04-30 16:30:20 +0200 | [diff] [blame] | 83 | /* |
| 84 | * early TLB into the .data section so that it not get cleared |
| 85 | * with 16kB allignment (see TTBR0_BASE_ADDR_MASK) |
| 86 | */ |
| 87 | u8 early_tlb[PGTABLE_SIZE] __section(".data") __aligned(0x4000); |
| 88 | |
Patrick Delaunay | 58e9553 | 2018-03-19 19:09:20 +0100 | [diff] [blame] | 89 | #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) |
Patrick Delaunay | f8fe21d | 2020-04-01 09:07:33 +0200 | [diff] [blame] | 90 | #ifndef CONFIG_TFABOOT |
Patrick Delaunay | 85b5397 | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 91 | static void security_init(void) |
| 92 | { |
| 93 | /* Disable the backup domain write protection */ |
| 94 | /* the protection is enable at each reset by hardware */ |
| 95 | /* And must be disable by software */ |
| 96 | setbits_le32(PWR_CR1, PWR_CR1_DBP); |
| 97 | |
| 98 | while (!(readl(PWR_CR1) & PWR_CR1_DBP)) |
| 99 | ; |
| 100 | |
| 101 | /* If RTC clock isn't enable so this is a cold boot then we need |
| 102 | * to reset the backup domain |
| 103 | */ |
| 104 | if (!(readl(RCC_BDCR) & RCC_BDCR_RTCSRC)) { |
| 105 | setbits_le32(RCC_BDCR, RCC_BDCR_VSWRST); |
| 106 | while (!(readl(RCC_BDCR) & RCC_BDCR_VSWRST)) |
| 107 | ; |
| 108 | clrbits_le32(RCC_BDCR, RCC_BDCR_VSWRST); |
| 109 | } |
| 110 | |
| 111 | /* allow non secure access in Write/Read for all peripheral */ |
| 112 | writel(GENMASK(25, 0), ETZPC_DECPROT0); |
| 113 | |
| 114 | /* Open SYSRAM for no secure access */ |
| 115 | writel(0x0, ETZPC_TZMA1_SIZE); |
| 116 | |
| 117 | /* enable TZC1 TZC2 clock */ |
| 118 | writel(BIT(11) | BIT(12), RCC_MP_APB5ENSETR); |
| 119 | |
| 120 | /* Region 0 set to no access by default */ |
| 121 | /* bit 0 / 16 => nsaid0 read/write Enable |
| 122 | * bit 1 / 17 => nsaid1 read/write Enable |
| 123 | * ... |
| 124 | * bit 15 / 31 => nsaid15 read/write Enable |
| 125 | */ |
| 126 | writel(0xFFFFFFFF, TZC_REGION_ID_ACCESS0); |
| 127 | /* bit 30 / 31 => Secure Global Enable : write/read */ |
| 128 | /* bit 0 / 1 => Region Enable for filter 0/1 */ |
| 129 | writel(BIT(0) | BIT(1) | BIT(30) | BIT(31), TZC_REGION_ATTRIBUTE0); |
| 130 | |
| 131 | /* Enable Filter 0 and 1 */ |
| 132 | setbits_le32(TZC_GATE_KEEPER, BIT(0) | BIT(1)); |
| 133 | |
| 134 | /* RCC trust zone deactivated */ |
| 135 | writel(0x0, RCC_TZCR); |
| 136 | |
| 137 | /* TAMP: deactivate the internal tamper |
| 138 | * Bit 23 ITAMP8E: monotonic counter overflow |
| 139 | * Bit 20 ITAMP5E: RTC calendar overflow |
| 140 | * Bit 19 ITAMP4E: HSE monitoring |
| 141 | * Bit 18 ITAMP3E: LSE monitoring |
| 142 | * Bit 16 ITAMP1E: RTC power domain supply monitoring |
| 143 | */ |
| 144 | writel(0x0, TAMP_CR1); |
Patrick Delaunay | d4ca35c | 2019-02-27 17:01:26 +0100 | [diff] [blame] | 145 | |
| 146 | /* GPIOZ: deactivate the security */ |
| 147 | writel(BIT(0), RCC_MP_AHB5ENSETR); |
| 148 | writel(0x0, GPIOZ_SECCFGR); |
Patrick Delaunay | 85b5397 | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 149 | } |
Patrick Delaunay | f8fe21d | 2020-04-01 09:07:33 +0200 | [diff] [blame] | 150 | #endif /* CONFIG_TFABOOT */ |
Patrick Delaunay | 85b5397 | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 151 | |
Patrick Delaunay | 58e9553 | 2018-03-19 19:09:20 +0100 | [diff] [blame] | 152 | /* |
Patrick Delaunay | 85b5397 | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 153 | * Debug init |
Patrick Delaunay | 58e9553 | 2018-03-19 19:09:20 +0100 | [diff] [blame] | 154 | */ |
Patrick Delaunay | 85b5397 | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 155 | static void dbgmcu_init(void) |
| 156 | { |
Patrick Delaunay | 6332c04 | 2020-06-16 18:27:44 +0200 | [diff] [blame] | 157 | /* |
| 158 | * Freeze IWDG2 if Cortex-A7 is in debug mode |
| 159 | * done in TF-A for TRUSTED boot and |
| 160 | * DBGMCU access is controlled by BSEC_DENABLE.DBGSWENABLE |
| 161 | */ |
Patrick Delaunay | 4c5821d | 2020-07-24 11:13:31 +0200 | [diff] [blame] | 162 | if (!IS_ENABLED(CONFIG_TFABOOT) && bsec_dbgswenable()) { |
| 163 | setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN); |
Patrick Delaunay | 6332c04 | 2020-06-16 18:27:44 +0200 | [diff] [blame] | 164 | setbits_le32(DBGMCU_APB4FZ1, DBGMCU_APB4FZ1_IWDG2); |
Patrick Delaunay | 4c5821d | 2020-07-24 11:13:31 +0200 | [diff] [blame] | 165 | } |
| 166 | } |
| 167 | |
| 168 | void spl_board_init(void) |
| 169 | { |
| 170 | dbgmcu_init(); |
Patrick Delaunay | 85b5397 | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 171 | } |
| 172 | #endif /* !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) */ |
| 173 | |
Patrick Delaunay | f8fe21d | 2020-04-01 09:07:33 +0200 | [diff] [blame] | 174 | #if !defined(CONFIG_TFABOOT) && \ |
Patrick Delaunay | 5d06141 | 2019-02-12 11:44:39 +0100 | [diff] [blame] | 175 | (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)) |
Patrick Delaunay | 18660a6 | 2019-02-27 17:01:12 +0100 | [diff] [blame] | 176 | /* get bootmode from ROM code boot context: saved in TAMP register */ |
| 177 | static void update_bootmode(void) |
| 178 | { |
| 179 | u32 boot_mode; |
Patrick Delaunay | c5d1565 | 2018-03-20 10:54:53 +0100 | [diff] [blame] | 180 | u32 bootrom_itf = readl(BOOTROM_PARAM_ADDR); |
| 181 | u32 bootrom_device, bootrom_instance; |
| 182 | |
Patrick Delaunay | 18660a6 | 2019-02-27 17:01:12 +0100 | [diff] [blame] | 183 | /* enable TAMP clock = RTCAPBEN */ |
| 184 | writel(BIT(8), RCC_MP_APB5ENSETR); |
| 185 | |
| 186 | /* read bootrom context */ |
Patrick Delaunay | c5d1565 | 2018-03-20 10:54:53 +0100 | [diff] [blame] | 187 | bootrom_device = |
| 188 | (bootrom_itf & BOOTROM_MODE_MASK) >> BOOTROM_MODE_SHIFT; |
| 189 | bootrom_instance = |
| 190 | (bootrom_itf & BOOTROM_INSTANCE_MASK) >> BOOTROM_INSTANCE_SHIFT; |
| 191 | boot_mode = |
| 192 | ((bootrom_device << BOOT_TYPE_SHIFT) & BOOT_TYPE_MASK) | |
| 193 | ((bootrom_instance << BOOT_INSTANCE_SHIFT) & |
| 194 | BOOT_INSTANCE_MASK); |
| 195 | |
| 196 | /* save the boot mode in TAMP backup register */ |
| 197 | clrsetbits_le32(TAMP_BOOT_CONTEXT, |
| 198 | TAMP_BOOT_MODE_MASK, |
| 199 | boot_mode << TAMP_BOOT_MODE_SHIFT); |
Patrick Delaunay | 18660a6 | 2019-02-27 17:01:12 +0100 | [diff] [blame] | 200 | } |
Patrick Delaunay | c5d1565 | 2018-03-20 10:54:53 +0100 | [diff] [blame] | 201 | #endif |
Patrick Delaunay | 18660a6 | 2019-02-27 17:01:12 +0100 | [diff] [blame] | 202 | |
| 203 | u32 get_bootmode(void) |
| 204 | { |
| 205 | /* read bootmode from TAMP backup register */ |
| 206 | return (readl(TAMP_BOOT_CONTEXT) & TAMP_BOOT_MODE_MASK) >> |
| 207 | TAMP_BOOT_MODE_SHIFT; |
Patrick Delaunay | c5d1565 | 2018-03-20 10:54:53 +0100 | [diff] [blame] | 208 | } |
| 209 | |
| 210 | /* |
Patrick Delaunay | 8e6985b | 2020-04-30 16:30:20 +0200 | [diff] [blame] | 211 | * initialize the MMU and activate cache in SPL or in U-Boot pre-reloc stage |
| 212 | * MMU/TLB is updated in enable_caches() for U-Boot after relocation |
| 213 | * or is deactivated in U-Boot entry function start.S::cpu_init_cp15 |
| 214 | */ |
| 215 | static void early_enable_caches(void) |
| 216 | { |
| 217 | /* I-cache is already enabled in start.S: cpu_init_cp15 */ |
| 218 | |
| 219 | if (CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) |
| 220 | return; |
| 221 | |
| 222 | gd->arch.tlb_size = PGTABLE_SIZE; |
| 223 | gd->arch.tlb_addr = (unsigned long)&early_tlb; |
| 224 | |
| 225 | dcache_enable(); |
| 226 | |
| 227 | if (IS_ENABLED(CONFIG_SPL_BUILD)) |
Patrick Delaunay | 51ac7f1 | 2020-07-24 11:21:51 +0200 | [diff] [blame] | 228 | mmu_set_region_dcache_behaviour( |
| 229 | ALIGN(STM32_SYSRAM_BASE, MMU_SECTION_SIZE), |
| 230 | round_up(STM32_SYSRAM_SIZE, MMU_SECTION_SIZE), |
| 231 | DCACHE_DEFAULT_OPTION); |
Patrick Delaunay | 8e6985b | 2020-04-30 16:30:20 +0200 | [diff] [blame] | 232 | else |
| 233 | mmu_set_region_dcache_behaviour(STM32_DDR_BASE, STM32_DDR_SIZE, |
| 234 | DCACHE_DEFAULT_OPTION); |
| 235 | } |
| 236 | |
| 237 | /* |
Patrick Delaunay | c5d1565 | 2018-03-20 10:54:53 +0100 | [diff] [blame] | 238 | * Early system init |
| 239 | */ |
Patrick Delaunay | 85b5397 | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 240 | int arch_cpu_init(void) |
| 241 | { |
Patrick Delaunay | 82168e8 | 2018-05-17 14:50:46 +0200 | [diff] [blame] | 242 | u32 boot_mode; |
| 243 | |
Patrick Delaunay | 8e6985b | 2020-04-30 16:30:20 +0200 | [diff] [blame] | 244 | early_enable_caches(); |
| 245 | |
Patrick Delaunay | 85b5397 | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 246 | /* early armv7 timer init: needed for polling */ |
| 247 | timer_init(); |
| 248 | |
| 249 | #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) |
Patrick Delaunay | f8fe21d | 2020-04-01 09:07:33 +0200 | [diff] [blame] | 250 | #ifndef CONFIG_TFABOOT |
Patrick Delaunay | 85b5397 | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 251 | security_init(); |
Patrick Delaunay | 18660a6 | 2019-02-27 17:01:12 +0100 | [diff] [blame] | 252 | update_bootmode(); |
Patrick Delaunay | 85b5397 | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 253 | #endif |
Fabien Dessenne | 9ebbdc9 | 2019-10-30 14:38:30 +0100 | [diff] [blame] | 254 | /* Reset Coprocessor state unless it wakes up from Standby power mode */ |
| 255 | if (!(readl(PWR_MCUCR) & PWR_MCUCR_SBF)) { |
| 256 | writel(TAMP_COPRO_STATE_OFF, TAMP_COPRO_STATE); |
| 257 | writel(0, TAMP_COPRO_RSC_TBL_ADDRESS); |
| 258 | } |
Patrick Delaunay | 5d06141 | 2019-02-12 11:44:39 +0100 | [diff] [blame] | 259 | #endif |
Patrick Delaunay | 82168e8 | 2018-05-17 14:50:46 +0200 | [diff] [blame] | 260 | |
Patrick Delaunay | 82168e8 | 2018-05-17 14:50:46 +0200 | [diff] [blame] | 261 | boot_mode = get_bootmode(); |
| 262 | |
| 263 | if ((boot_mode & TAMP_BOOT_DEVICE_MASK) == BOOT_SERIAL_UART) |
| 264 | gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE; |
| 265 | #if defined(CONFIG_DEBUG_UART) && \ |
Patrick Delaunay | f8fe21d | 2020-04-01 09:07:33 +0200 | [diff] [blame] | 266 | !defined(CONFIG_TFABOOT) && \ |
Patrick Delaunay | 82168e8 | 2018-05-17 14:50:46 +0200 | [diff] [blame] | 267 | (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)) |
| 268 | else |
| 269 | debug_uart_init(); |
| 270 | #endif |
Patrick Delaunay | 85b5397 | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 271 | |
| 272 | return 0; |
| 273 | } |
| 274 | |
Patrick Delaunay | 58e9553 | 2018-03-19 19:09:20 +0100 | [diff] [blame] | 275 | void enable_caches(void) |
| 276 | { |
Patrick Delaunay | 8e6985b | 2020-04-30 16:30:20 +0200 | [diff] [blame] | 277 | /* I-cache is already enabled in start.S: icache_enable() not needed */ |
| 278 | |
| 279 | /* deactivate the data cache, early enabled in arch_cpu_init() */ |
| 280 | dcache_disable(); |
| 281 | /* |
| 282 | * update MMU after relocation and enable the data cache |
| 283 | * warning: the TLB location udpated in board_f.c::reserve_mmu |
| 284 | */ |
Patrick Delaunay | 58e9553 | 2018-03-19 19:09:20 +0100 | [diff] [blame] | 285 | dcache_enable(); |
| 286 | } |
| 287 | |
Patrick Delaunay | 01e3afe | 2018-03-19 19:09:21 +0100 | [diff] [blame] | 288 | static u32 read_idc(void) |
| 289 | { |
Patrick Delaunay | 6332c04 | 2020-06-16 18:27:44 +0200 | [diff] [blame] | 290 | /* DBGMCU access is controlled by BSEC_DENABLE.DBGSWENABLE */ |
| 291 | if (bsec_dbgswenable()) { |
| 292 | setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN); |
Patrick Delaunay | 01e3afe | 2018-03-19 19:09:21 +0100 | [diff] [blame] | 293 | |
Patrick Delaunay | 6332c04 | 2020-06-16 18:27:44 +0200 | [diff] [blame] | 294 | return readl(DBGMCU_IDC); |
| 295 | } |
| 296 | |
| 297 | if (CONFIG_IS_ENABLED(STM32MP15x)) |
| 298 | return CPU_DEV_STM32MP15; /* STM32MP15x and unknown revision */ |
| 299 | else |
| 300 | return 0x0; |
Patrick Delaunay | 01e3afe | 2018-03-19 19:09:21 +0100 | [diff] [blame] | 301 | } |
| 302 | |
Patrick Delaunay | 79bc640 | 2020-03-18 09:24:48 +0100 | [diff] [blame] | 303 | u32 get_cpu_dev(void) |
| 304 | { |
| 305 | return (read_idc() & DBGMCU_IDC_DEV_ID_MASK) >> DBGMCU_IDC_DEV_ID_SHIFT; |
| 306 | } |
| 307 | |
Patrick Delaunay | 01e3afe | 2018-03-19 19:09:21 +0100 | [diff] [blame] | 308 | u32 get_cpu_rev(void) |
| 309 | { |
| 310 | return (read_idc() & DBGMCU_IDC_REV_ID_MASK) >> DBGMCU_IDC_REV_ID_SHIFT; |
| 311 | } |
| 312 | |
Patrick Delaunay | 45c82d2 | 2019-02-27 17:01:13 +0100 | [diff] [blame] | 313 | static u32 get_otp(int index, int shift, int mask) |
| 314 | { |
| 315 | int ret; |
| 316 | struct udevice *dev; |
| 317 | u32 otp = 0; |
| 318 | |
| 319 | ret = uclass_get_device_by_driver(UCLASS_MISC, |
| 320 | DM_GET_DRIVER(stm32mp_bsec), |
| 321 | &dev); |
| 322 | |
| 323 | if (!ret) |
| 324 | ret = misc_read(dev, STM32_BSEC_SHADOW(index), |
| 325 | &otp, sizeof(otp)); |
| 326 | |
| 327 | return (otp >> shift) & mask; |
| 328 | } |
| 329 | |
| 330 | /* Get Device Part Number (RPN) from OTP */ |
| 331 | static u32 get_cpu_rpn(void) |
| 332 | { |
| 333 | return get_otp(BSEC_OTP_RPN, RPN_SHIFT, RPN_MASK); |
| 334 | } |
| 335 | |
Patrick Delaunay | 01e3afe | 2018-03-19 19:09:21 +0100 | [diff] [blame] | 336 | u32 get_cpu_type(void) |
| 337 | { |
Patrick Delaunay | 79bc640 | 2020-03-18 09:24:48 +0100 | [diff] [blame] | 338 | return (get_cpu_dev() << 16) | get_cpu_rpn(); |
Patrick Delaunay | 01e3afe | 2018-03-19 19:09:21 +0100 | [diff] [blame] | 339 | } |
| 340 | |
Patrick Delaunay | 45c82d2 | 2019-02-27 17:01:13 +0100 | [diff] [blame] | 341 | /* Get Package options from OTP */ |
Patrick Delaunay | c74d634 | 2019-07-05 17:20:13 +0200 | [diff] [blame] | 342 | u32 get_cpu_package(void) |
Patrick Delaunay | 45c82d2 | 2019-02-27 17:01:13 +0100 | [diff] [blame] | 343 | { |
| 344 | return get_otp(BSEC_OTP_PKG, PKG_SHIFT, PKG_MASK); |
| 345 | } |
| 346 | |
Patrick Delaunay | 3e738f2 | 2020-02-12 19:37:43 +0100 | [diff] [blame] | 347 | void get_soc_name(char name[SOC_NAME_SIZE]) |
Patrick Delaunay | 85b5397 | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 348 | { |
Patrick Delaunay | 45c82d2 | 2019-02-27 17:01:13 +0100 | [diff] [blame] | 349 | char *cpu_s, *cpu_r, *pkg; |
Patrick Delaunay | 01e3afe | 2018-03-19 19:09:21 +0100 | [diff] [blame] | 350 | |
Patrick Delaunay | 45c82d2 | 2019-02-27 17:01:13 +0100 | [diff] [blame] | 351 | /* MPUs Part Numbers */ |
Patrick Delaunay | 01e3afe | 2018-03-19 19:09:21 +0100 | [diff] [blame] | 352 | switch (get_cpu_type()) { |
Patrick Delaunay | db33b0e | 2020-02-26 11:26:43 +0100 | [diff] [blame] | 353 | case CPU_STM32MP157Fxx: |
| 354 | cpu_s = "157F"; |
| 355 | break; |
| 356 | case CPU_STM32MP157Dxx: |
| 357 | cpu_s = "157D"; |
| 358 | break; |
Patrick Delaunay | 45c82d2 | 2019-02-27 17:01:13 +0100 | [diff] [blame] | 359 | case CPU_STM32MP157Cxx: |
| 360 | cpu_s = "157C"; |
| 361 | break; |
| 362 | case CPU_STM32MP157Axx: |
| 363 | cpu_s = "157A"; |
| 364 | break; |
Patrick Delaunay | db33b0e | 2020-02-26 11:26:43 +0100 | [diff] [blame] | 365 | case CPU_STM32MP153Fxx: |
| 366 | cpu_s = "153F"; |
| 367 | break; |
| 368 | case CPU_STM32MP153Dxx: |
| 369 | cpu_s = "153D"; |
| 370 | break; |
Patrick Delaunay | 45c82d2 | 2019-02-27 17:01:13 +0100 | [diff] [blame] | 371 | case CPU_STM32MP153Cxx: |
| 372 | cpu_s = "153C"; |
| 373 | break; |
| 374 | case CPU_STM32MP153Axx: |
| 375 | cpu_s = "153A"; |
| 376 | break; |
Patrick Delaunay | db33b0e | 2020-02-26 11:26:43 +0100 | [diff] [blame] | 377 | case CPU_STM32MP151Fxx: |
| 378 | cpu_s = "151F"; |
| 379 | break; |
| 380 | case CPU_STM32MP151Dxx: |
| 381 | cpu_s = "151D"; |
| 382 | break; |
Patrick Delaunay | 45c82d2 | 2019-02-27 17:01:13 +0100 | [diff] [blame] | 383 | case CPU_STM32MP151Cxx: |
| 384 | cpu_s = "151C"; |
| 385 | break; |
| 386 | case CPU_STM32MP151Axx: |
| 387 | cpu_s = "151A"; |
| 388 | break; |
| 389 | default: |
| 390 | cpu_s = "????"; |
| 391 | break; |
| 392 | } |
| 393 | |
| 394 | /* Package */ |
| 395 | switch (get_cpu_package()) { |
| 396 | case PKG_AA_LBGA448: |
| 397 | pkg = "AA"; |
| 398 | break; |
| 399 | case PKG_AB_LBGA354: |
| 400 | pkg = "AB"; |
| 401 | break; |
| 402 | case PKG_AC_TFBGA361: |
| 403 | pkg = "AC"; |
| 404 | break; |
| 405 | case PKG_AD_TFBGA257: |
| 406 | pkg = "AD"; |
Patrick Delaunay | 01e3afe | 2018-03-19 19:09:21 +0100 | [diff] [blame] | 407 | break; |
| 408 | default: |
Patrick Delaunay | 45c82d2 | 2019-02-27 17:01:13 +0100 | [diff] [blame] | 409 | pkg = "??"; |
Patrick Delaunay | 01e3afe | 2018-03-19 19:09:21 +0100 | [diff] [blame] | 410 | break; |
| 411 | } |
| 412 | |
Patrick Delaunay | 45c82d2 | 2019-02-27 17:01:13 +0100 | [diff] [blame] | 413 | /* REVISION */ |
Patrick Delaunay | 01e3afe | 2018-03-19 19:09:21 +0100 | [diff] [blame] | 414 | switch (get_cpu_rev()) { |
| 415 | case CPU_REVA: |
| 416 | cpu_r = "A"; |
| 417 | break; |
| 418 | case CPU_REVB: |
| 419 | cpu_r = "B"; |
| 420 | break; |
Patrick Delaunay | c8d4afe | 2020-01-28 10:11:06 +0100 | [diff] [blame] | 421 | case CPU_REVZ: |
| 422 | cpu_r = "Z"; |
| 423 | break; |
Patrick Delaunay | 01e3afe | 2018-03-19 19:09:21 +0100 | [diff] [blame] | 424 | default: |
| 425 | cpu_r = "?"; |
| 426 | break; |
| 427 | } |
| 428 | |
Patrick Delaunay | 3e738f2 | 2020-02-12 19:37:43 +0100 | [diff] [blame] | 429 | snprintf(name, SOC_NAME_SIZE, "STM32MP%s%s Rev.%s", cpu_s, pkg, cpu_r); |
| 430 | } |
| 431 | |
| 432 | #if defined(CONFIG_DISPLAY_CPUINFO) |
| 433 | int print_cpuinfo(void) |
| 434 | { |
| 435 | char name[SOC_NAME_SIZE]; |
| 436 | |
| 437 | get_soc_name(name); |
| 438 | printf("CPU: %s\n", name); |
Patrick Delaunay | 85b5397 | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 439 | |
| 440 | return 0; |
| 441 | } |
| 442 | #endif /* CONFIG_DISPLAY_CPUINFO */ |
| 443 | |
Patrick Delaunay | c5d1565 | 2018-03-20 10:54:53 +0100 | [diff] [blame] | 444 | static void setup_boot_mode(void) |
| 445 | { |
Patrick Delaunay | 18660a6 | 2019-02-27 17:01:12 +0100 | [diff] [blame] | 446 | const u32 serial_addr[] = { |
| 447 | STM32_USART1_BASE, |
| 448 | STM32_USART2_BASE, |
| 449 | STM32_USART3_BASE, |
| 450 | STM32_UART4_BASE, |
| 451 | STM32_UART5_BASE, |
| 452 | STM32_USART6_BASE, |
| 453 | STM32_UART7_BASE, |
| 454 | STM32_UART8_BASE |
| 455 | }; |
Patrick Delaunay | c5d1565 | 2018-03-20 10:54:53 +0100 | [diff] [blame] | 456 | char cmd[60]; |
| 457 | u32 boot_ctx = readl(TAMP_BOOT_CONTEXT); |
| 458 | u32 boot_mode = |
| 459 | (boot_ctx & TAMP_BOOT_MODE_MASK) >> TAMP_BOOT_MODE_SHIFT; |
Patrick Delaunay | 1b03eb0 | 2019-06-21 15:26:39 +0200 | [diff] [blame] | 460 | unsigned int instance = (boot_mode & TAMP_BOOT_INSTANCE_MASK) - 1; |
Patrick Delaunay | 008d3c3 | 2019-02-27 17:01:20 +0100 | [diff] [blame] | 461 | u32 forced_mode = (boot_ctx & TAMP_BOOT_FORCED_MASK); |
Patrick Delaunay | 18660a6 | 2019-02-27 17:01:12 +0100 | [diff] [blame] | 462 | struct udevice *dev; |
| 463 | int alias; |
Patrick Delaunay | c5d1565 | 2018-03-20 10:54:53 +0100 | [diff] [blame] | 464 | |
Patrick Delaunay | 008d3c3 | 2019-02-27 17:01:20 +0100 | [diff] [blame] | 465 | pr_debug("%s: boot_ctx=0x%x => boot_mode=%x, instance=%d forced=%x\n", |
| 466 | __func__, boot_ctx, boot_mode, instance, forced_mode); |
Patrick Delaunay | c5d1565 | 2018-03-20 10:54:53 +0100 | [diff] [blame] | 467 | switch (boot_mode & TAMP_BOOT_DEVICE_MASK) { |
| 468 | case BOOT_SERIAL_UART: |
Patrick Delaunay | 18660a6 | 2019-02-27 17:01:12 +0100 | [diff] [blame] | 469 | if (instance > ARRAY_SIZE(serial_addr)) |
| 470 | break; |
| 471 | /* serial : search associated alias in devicetree */ |
| 472 | sprintf(cmd, "serial@%x", serial_addr[instance]); |
| 473 | if (uclass_get_device_by_name(UCLASS_SERIAL, cmd, &dev)) |
| 474 | break; |
| 475 | if (fdtdec_get_alias_seq(gd->fdt_blob, "serial", |
| 476 | dev_of_offset(dev), &alias)) |
| 477 | break; |
| 478 | sprintf(cmd, "%d", alias); |
| 479 | env_set("boot_device", "serial"); |
Patrick Delaunay | c5d1565 | 2018-03-20 10:54:53 +0100 | [diff] [blame] | 480 | env_set("boot_instance", cmd); |
Patrick Delaunay | 18660a6 | 2019-02-27 17:01:12 +0100 | [diff] [blame] | 481 | |
| 482 | /* restore console on uart when not used */ |
| 483 | if (gd->cur_serial_dev != dev) { |
| 484 | gd->flags &= ~(GD_FLG_SILENT | |
| 485 | GD_FLG_DISABLE_CONSOLE); |
| 486 | printf("serial boot with console enabled!\n"); |
| 487 | } |
Patrick Delaunay | c5d1565 | 2018-03-20 10:54:53 +0100 | [diff] [blame] | 488 | break; |
| 489 | case BOOT_SERIAL_USB: |
| 490 | env_set("boot_device", "usb"); |
| 491 | env_set("boot_instance", "0"); |
| 492 | break; |
| 493 | case BOOT_FLASH_SD: |
| 494 | case BOOT_FLASH_EMMC: |
| 495 | sprintf(cmd, "%d", instance); |
| 496 | env_set("boot_device", "mmc"); |
| 497 | env_set("boot_instance", cmd); |
| 498 | break; |
| 499 | case BOOT_FLASH_NAND: |
| 500 | env_set("boot_device", "nand"); |
| 501 | env_set("boot_instance", "0"); |
| 502 | break; |
Patrick Delaunay | b5a7ca2 | 2020-03-18 09:22:52 +0100 | [diff] [blame] | 503 | case BOOT_FLASH_SPINAND: |
| 504 | env_set("boot_device", "spi-nand"); |
| 505 | env_set("boot_instance", "0"); |
| 506 | break; |
Patrick Delaunay | c5d1565 | 2018-03-20 10:54:53 +0100 | [diff] [blame] | 507 | case BOOT_FLASH_NOR: |
| 508 | env_set("boot_device", "nor"); |
| 509 | env_set("boot_instance", "0"); |
| 510 | break; |
| 511 | default: |
| 512 | pr_debug("unexpected boot mode = %x\n", boot_mode); |
| 513 | break; |
| 514 | } |
Patrick Delaunay | 008d3c3 | 2019-02-27 17:01:20 +0100 | [diff] [blame] | 515 | |
| 516 | switch (forced_mode) { |
| 517 | case BOOT_FASTBOOT: |
| 518 | printf("Enter fastboot!\n"); |
| 519 | env_set("preboot", "env set preboot; fastboot 0"); |
| 520 | break; |
| 521 | case BOOT_STM32PROG: |
| 522 | env_set("boot_device", "usb"); |
| 523 | env_set("boot_instance", "0"); |
| 524 | break; |
| 525 | case BOOT_UMS_MMC0: |
| 526 | case BOOT_UMS_MMC1: |
| 527 | case BOOT_UMS_MMC2: |
| 528 | printf("Enter UMS!\n"); |
| 529 | instance = forced_mode - BOOT_UMS_MMC0; |
| 530 | sprintf(cmd, "env set preboot; ums 0 mmc %d", instance); |
| 531 | env_set("preboot", cmd); |
| 532 | break; |
| 533 | case BOOT_RECOVERY: |
| 534 | env_set("preboot", "env set preboot; run altbootcmd"); |
| 535 | break; |
| 536 | case BOOT_NORMAL: |
| 537 | break; |
| 538 | default: |
| 539 | pr_debug("unexpected forced boot mode = %x\n", forced_mode); |
| 540 | break; |
| 541 | } |
| 542 | |
| 543 | /* clear TAMP for next reboot */ |
| 544 | clrsetbits_le32(TAMP_BOOT_CONTEXT, TAMP_BOOT_FORCED_MASK, BOOT_NORMAL); |
Patrick Delaunay | f3674a4 | 2018-05-17 15:24:07 +0200 | [diff] [blame] | 545 | } |
| 546 | |
| 547 | /* |
| 548 | * If there is no MAC address in the environment, then it will be initialized |
| 549 | * (silently) from the value in the OTP. |
| 550 | */ |
Marek Vasut | 187cae2 | 2019-12-18 16:52:19 +0100 | [diff] [blame] | 551 | __weak int setup_mac_address(void) |
Patrick Delaunay | f3674a4 | 2018-05-17 15:24:07 +0200 | [diff] [blame] | 552 | { |
| 553 | #if defined(CONFIG_NET) |
| 554 | int ret; |
| 555 | int i; |
| 556 | u32 otp[2]; |
| 557 | uchar enetaddr[6]; |
| 558 | struct udevice *dev; |
| 559 | |
| 560 | /* MAC already in environment */ |
| 561 | if (eth_env_get_enetaddr("ethaddr", enetaddr)) |
| 562 | return 0; |
| 563 | |
| 564 | ret = uclass_get_device_by_driver(UCLASS_MISC, |
| 565 | DM_GET_DRIVER(stm32mp_bsec), |
| 566 | &dev); |
| 567 | if (ret) |
| 568 | return ret; |
| 569 | |
Patrick Delaunay | 10263a5 | 2019-02-27 17:01:29 +0100 | [diff] [blame] | 570 | ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_MAC), |
Patrick Delaunay | f3674a4 | 2018-05-17 15:24:07 +0200 | [diff] [blame] | 571 | otp, sizeof(otp)); |
Simon Glass | 587dc40 | 2018-11-06 15:21:39 -0700 | [diff] [blame] | 572 | if (ret < 0) |
Patrick Delaunay | f3674a4 | 2018-05-17 15:24:07 +0200 | [diff] [blame] | 573 | return ret; |
| 574 | |
| 575 | for (i = 0; i < 6; i++) |
| 576 | enetaddr[i] = ((uint8_t *)&otp)[i]; |
| 577 | |
| 578 | if (!is_valid_ethaddr(enetaddr)) { |
Manivannan Sadhasivam | e523772 | 2019-05-02 13:26:45 +0530 | [diff] [blame] | 579 | pr_err("invalid MAC address in OTP %pM\n", enetaddr); |
Patrick Delaunay | f3674a4 | 2018-05-17 15:24:07 +0200 | [diff] [blame] | 580 | return -EINVAL; |
| 581 | } |
| 582 | pr_debug("OTP MAC address = %pM\n", enetaddr); |
Patrick Delaunay | 3a8e406 | 2020-04-07 16:07:46 +0200 | [diff] [blame] | 583 | ret = eth_env_set_enetaddr("ethaddr", enetaddr); |
| 584 | if (ret) |
Patrick Delaunay | f3674a4 | 2018-05-17 15:24:07 +0200 | [diff] [blame] | 585 | pr_err("Failed to set mac address %pM from OTP: %d\n", |
| 586 | enetaddr, ret); |
| 587 | #endif |
| 588 | |
| 589 | return 0; |
| 590 | } |
| 591 | |
| 592 | static int setup_serial_number(void) |
| 593 | { |
| 594 | char serial_string[25]; |
| 595 | u32 otp[3] = {0, 0, 0 }; |
| 596 | struct udevice *dev; |
| 597 | int ret; |
| 598 | |
| 599 | if (env_get("serial#")) |
| 600 | return 0; |
| 601 | |
| 602 | ret = uclass_get_device_by_driver(UCLASS_MISC, |
| 603 | DM_GET_DRIVER(stm32mp_bsec), |
| 604 | &dev); |
| 605 | if (ret) |
| 606 | return ret; |
| 607 | |
Patrick Delaunay | 10263a5 | 2019-02-27 17:01:29 +0100 | [diff] [blame] | 608 | ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_SERIAL), |
Patrick Delaunay | f3674a4 | 2018-05-17 15:24:07 +0200 | [diff] [blame] | 609 | otp, sizeof(otp)); |
Simon Glass | 587dc40 | 2018-11-06 15:21:39 -0700 | [diff] [blame] | 610 | if (ret < 0) |
Patrick Delaunay | f3674a4 | 2018-05-17 15:24:07 +0200 | [diff] [blame] | 611 | return ret; |
| 612 | |
Patrick Delaunay | af5564a | 2019-02-27 17:01:25 +0100 | [diff] [blame] | 613 | sprintf(serial_string, "%08X%08X%08X", otp[0], otp[1], otp[2]); |
Patrick Delaunay | f3674a4 | 2018-05-17 15:24:07 +0200 | [diff] [blame] | 614 | env_set("serial#", serial_string); |
| 615 | |
| 616 | return 0; |
Patrick Delaunay | c5d1565 | 2018-03-20 10:54:53 +0100 | [diff] [blame] | 617 | } |
| 618 | |
| 619 | int arch_misc_init(void) |
| 620 | { |
| 621 | setup_boot_mode(); |
Patrick Delaunay | f3674a4 | 2018-05-17 15:24:07 +0200 | [diff] [blame] | 622 | setup_mac_address(); |
| 623 | setup_serial_number(); |
Patrick Delaunay | c5d1565 | 2018-03-20 10:54:53 +0100 | [diff] [blame] | 624 | |
| 625 | return 0; |
| 626 | } |