blob: adfd8fd8cb616a556687405ef824326e21e60d76 [file] [log] [blame]
Marek Vasute7628752022-04-08 02:15:01 +02001// SPDX-License-Identifier: GPL-2.0+ OR MIT
2/*
3 * Copyright 2021-2022 Marek Vasut <marex@denx.de>
4 */
5
6#include "imx8mm-verdin.dts"
7
8/ {
9 model = "MENLO MX8MM EMBEDDED DEVICE";
10 compatible = "menlo,mx8menlo",
11 "toradex,verdin-imx8mm",
12 "fsl,imx8mm";
13
14 /delete-node/ gpio-keys;
15
16 leds {
17 compatible = "gpio-leds";
18 pinctrl-names = "default";
19 pinctrl-0 = <&pinctrl_led>;
20
21 user1 {
22 label = "TestLed601";
23 gpios = <&gpio4 18 GPIO_ACTIVE_HIGH>;
24 linux,default-trigger = "mmc0";
25 };
26
27 user2 {
28 label = "TestLed602";
29 gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>;
30 linux,default-trigger = "heartbeat";
31 };
32 };
33
34 beeper {
35 compatible = "gpio-beeper";
36 pinctrl-names = "default";
37 pinctrl-0 = <&pinctrl_beeper>;
38 gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>;
39 };
40};
41
42&ecspi1 {
43 #address-cells = <1>;
44 #size-cells = <0>;
45 pinctrl-names = "default";
46 pinctrl-0 = <&pinctrl_ecspi1>;
47 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
48 status = "okay";
49
50 /* CAN controller on the baseboard */
51 canfd: can@0 {
52 compatible = "microchip,mcp2518fd";
53 clocks = <&clk20m>;
54 gpio-controller;
55 interrupt-parent = <&gpio1>;
56 interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
57 reg = <0>;
58 spi-max-frequency = <2000000>;
59 status = "okay";
60 };
61
62};
63
64&ecspi2 {
65 pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_gpio1>;
66 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>, <&gpio3 4 GPIO_ACTIVE_LOW>;
67 status = "disabled";
68};
69
70&ethphy0 {
71 max-speed = <100>;
72};
73
74&fec1 {
75 status = "okay";
76};
77
78&flexspi {
79 status = "okay";
80
81 flash@0 {
82 reg = <0>;
83 #address-cells = <1>;
84 #size-cells = <1>;
85 compatible = "jedec,spi-nor";
86 spi-max-frequency = <66000000>;
87 spi-rx-bus-width = <4>;
88 spi-tx-bus-width = <4>;
89 };
90};
91
92&gpio1 {
93 gpio-line-names =
94 "", "", "", "",
95 "", "", "", "",
96 "", "", "", "",
97 "", "", "", "",
98 "", "", "", "",
99 "", "", "", "",
100 "", "", "", "",
101 "", "", "", "";
102};
103
104&gpio2 {
105 gpio-line-names =
106 "", "", "", "",
107 "", "", "", "",
108 "", "", "", "",
109 "", "", "", "",
110 "", "", "", "",
111 "", "", "", "",
112 "", "", "", "",
113 "", "", "", "";
114};
115
116&gpio3 {
117 gpio-line-names =
118 "", "", "", "",
119 "", "", "", "",
120 "", "", "", "",
121 "", "", "", "",
122 "", "", "", "",
123 "", "", "DISP_reset", "KBD_intI",
124 "", "", "", "",
125 "", "", "", "";
126};
127
128&gpio4 {
129 /*
130 * CPLD_D[n] is ARM_CPLD[n] in schematic
131 * CPLD_int is SA_INTERRUPT in schematic
132 * CPLD_reset is RESET_SOFT in schematic
133 */
134 gpio-line-names =
135 "CPLD_D[1]", "CPLD_int", "CPLD_reset", "",
136 "", "CPLD_D[0]", "", "",
137 "", "", "", "CPLD_D[2]",
138 "CPLD_D[3]", "CPLD_D[4]", "CPLD_D[5]", "CPLD_D[6]",
139 "CPLD_D[7]", "", "", "",
140 "", "", "", "",
141 "", "", "", "KBD_intK",
142 "", "", "", "";
143};
144
145&gpio5 {
146 gpio-line-names =
147 "", "", "", "",
148 "", "", "", "",
149 "", "", "", "",
150 "", "", "", "",
151 "", "", "", "",
152 "", "", "", "",
153 "", "", "", "",
154 "", "", "", "";
155};
156
157&gpio_expander_21 {
158 status = "okay";
159};
160
161&i2c1 {
162 /* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */
163 clock-frequency = <100000>;
164};
165
166&i2c2 {
167 /* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */
168 clock-frequency = <100000>;
169};
170
171&i2c3 {
172 /* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */
173 clock-frequency = <100000>;
174 status = "okay";
175};
176
177&i2c4 {
178 /* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */
179 clock-frequency = <100000>;
180 /delete-node/ bridge@2c;
181 /delete-node/ hwmon@40;
182 /delete-node/ hdmi@48;
183 /delete-node/ touch@4a;
184 /delete-node/ hwmontemp@4f;
185 /delete-node/ eeprom@50;
186 /delete-node/ eeprom@57;
187};
188
189&iomuxc {
190 pinctrl-0 = <&pinctrl_gpio7>, <&pinctrl_gpio_hog1>,
191 <&pinctrl_gpio_hog2>, <&pinctrl_gpio_hog3>;
192
193 pinctrl_beeper: beepergrp {
194 fsl,pins = <
195 MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x1c4
196 >;
197 };
198
199 pinctrl_ecspi1: ecspi1grp {
200 fsl,pins = <
201 MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x4
202 MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x4
203 MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x1c4
204 MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x1c4
205 >;
206 };
207
208 pinctrl_led: ledgrp {
209 fsl,pins = <
210 MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x1c4
211 MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x1c4
212 >;
213 };
214
215 pinctrl_uart4_rts: uart4rtsgrp {
216 fsl,pins = <
217 /* SODIMM 222 */
218 MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x184
219 >;
220 };
221};
222
223&pinctrl_gpio1 {
224 fsl,pins = <
225 /* SODIMM 206 */
226 MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x1c4
227 >;
228};
229
230&pinctrl_gpio_hog1 {
231 fsl,pins = <
232 /* SODIMM 88 */
233 MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x1c4
234 /* CPLD_int */
235 MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x1c4
236 /* CPLD_reset */
237 MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x1c4
238 /* SODIMM 94 */
239 MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x1c4
240 /* SODIMM 96 */
241 MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x1c4
242 /* CPLD_D[7] */
243 MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x1c4
244 /* CPLD_D[6] */
245 MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x1c4
246 /* CPLD_D[5] */
247 MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x1c4
248 /* CPLD_D[4] */
249 MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x1c4
250 /* CPLD_D[3] */
251 MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x1c4
252 /* CPLD_D[2] */
253 MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x1c4
254 /* CPLD_D[1] */
255 MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x1c4
256 /* CPLD_D[0] */
257 MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x1c4
258 /* KBD_intK */
259 MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x1c4
260 /* DISP_reset */
261 MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x1c4
262 /* KBD_intI */
263 MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x1c4
264 /* SODIMM 46 */
265 MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x1c4
266 >;
267};
268
269&pinctrl_uart1 {
270 fsl,pins = <
271 /* SODIMM 149 */
272 MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x1c4
273 /* SODIMM 147 */
274 MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x1c4
275 /* SODIMM 210 */
276 MX8MM_IOMUXC_UART3_RXD_UART1_DTE_RTS_B 0x1c4
277 /* SODIMM 212 */
278 MX8MM_IOMUXC_UART3_TXD_UART1_DTE_CTS_B 0x1c4
279 >;
280};
281
282&reg_usb_otg1_vbus {
283 /delete-property/ enable-active-high;
284 gpio = <&gpio1 12 GPIO_ACTIVE_LOW>;
285};
286
287&reg_usb_otg2_vbus {
288 /delete-property/ enable-active-high;
289 gpio = <&gpio1 14 GPIO_ACTIVE_LOW>;
290};
291
292&sai2 {
293 status = "disabled";
294};
295
296&uart1 {
297 uart-has-rtscts;
298 status = "okay";
299};
300
301&uart2 {
302 uart-has-rtscts;
303 status = "okay";
304};
305
306&uart4 {
307 pinctrl-0 = <&pinctrl_uart4 &pinctrl_uart4_rts>;
308 linux,rs485-enabled-at-boot-time;
309 rts-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
310 status = "okay";
311};
312
313&usbotg1 {
314 dr_mode = "gadget";
315 status = "okay";
316};
317
318&usbotg2 {
319 dr_mode = "host";
320 status = "okay";
321};
322
323&usdhc2 {
324 status = "okay";
325};