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git01.mediatek.com / filogic / uboot / 344833a08d0212d292393087870f2e2aab7101f1 / . / arch / arm / include / asm / mach-imx / imx-nandbcb.h
blob: 907e7ed8f94284c193585ebb5c3544e5bbc7aff2 [file] [log] [blame]
Shyam Sainif63ef492019-06-14 13:05:33 +0530[diff] [blame]1/*
2 * Copyright (C) 2017 Jagan Teki <jagan@amarulasolutions.com>
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#ifndef _IMX_NAND_BCB_H_
8#define _IMX_NAND_BCB_H_
9
10#define FCB_FINGERPRINT 0x20424346 /* 'FCB' */
11#define FCB_VERSION_1 0x01000000
12
13#define DBBT_FINGERPRINT2 0x54424244 /* 'DBBT' */
14#define DBBT_VERSION_1 0x01000000
15
16struct dbbt_block {
17 u32 checksum; /* reserved on i.MX6 */
18 u32 fingerprint;
19 u32 version;
20 u32 numberbb; /* reserved on i.MX6 */
21 u32 dbbtpages;
22};
23
24struct fcb_block {
25 u32 checksum; /* First fingerprint in first byte */
26 u32 fingerprint; /* 2nd fingerprint at byte 4 */
27 u32 version; /* 3rd fingerprint at byte 8 */
28 u8 datasetup;
29 u8 datahold;
30 u8 addr_setup;
31 u8 dsample_time;
32
33 /* These are for application use only and not for ROM. */
34 u8 nandtiming;
35 u8 rea;
36 u8 rloh;
37 u8 rhoh;
38 u32 pagesize; /* 2048 for 2K pages, 4096 for 4K pages */
39 u32 oob_pagesize; /* 2112 for 2K pages, 4314 for 4K pages */
40 u32 sectors; /* Number of 2K sections per block */
41 u32 nr_nand; /* Total Number of NANDs - not used by ROM */
42 u32 nr_die; /* Number of separate chips in this NAND */
43 u32 celltype; /* MLC or SLC */
44 u32 ecc_type; /* Type of ECC, can be one of BCH-0-20 */
45 u32 ecc_nr; /* Number of bytes for Block0 - BCH */
46
47 /* Block size in bytes for all blocks other than Block0 - BCH */
48 u32 ecc_size;
49 u32 ecc_level; /* Ecc level for Block 0 - BCH */
50 u32 meta_size; /* Metadata size - BCH */
51 /* Number of blocks per page for ROM use - BCH */
52 u32 nr_blocks;
53 u32 ecc_type_sdk; /* Type of ECC, can be one of BCH-0-20 */
54 u32 ecc_nr_sdk; /* Number of bytes for Block0 - BCH */
55 /* Block size in bytes for all blocks other than Block0 - BCH */
56 u32 ecc_size_sdk;
57 u32 ecc_level_sdk; /* Ecc level for Block 0 - BCH */
58 /* Number of blocks per page for SDK use - BCH */
59 u32 nr_blocks_sdk;
60 u32 meta_size_sdk; /* Metadata size - BCH */
61 u32 erase_th; /* To set into BCH_MODE register */
62
63 /*
64 * 0: normal boot
65 * 1: to load patch starting next to FCB
66 */
67 u32 bootpatch;
68 u32 patch_size; /* Size of patch in sectors */
69 u32 fw1_start; /* Firmware image starts on this sector */
70 u32 fw2_start; /* Secondary FW Image starting Sector */
71 u32 fw1_pages; /* Number of sectors in firmware image */
72 u32 fw2_pages; /* Number of sector in secondary FW image */
73 u32 dbbt_start; /* Page address where dbbt search area begins */
74
75 /*
76 * Byte in page data that have manufacturer marked bad block marker,
77 * this will be swapped with metadata[0] to complete page data.
78 */
79 u32 bb_byte;
80
81 /*
82 * For BCH ECC sizes other than 8 and 16 the bad block marker does not
83 * start at 0th bit of bb_byte. This field is used to get to
84 * the start bit of bad block marker byte with in bb_byte
85 */
86 u32 bb_start_bit;
87
88 /*
89 * FCB value that gives byte offset for
90 * bad block marker on physical NAND page
91 */
92 u32 phy_offset;
93 u32 bchtype;
94
95 u32 readlatency;
96 u32 predelay;
97 u32 cedelay;
98 u32 postdelay;
99 u32 cmdaddpause;
100 u32 datapause;
101 u32 tmspeed;
102 u32 busytimeout;
103
104 /* the flag to enable (1)/disable(0) bi swap */
105 u32 disbbm;
106
107 /* The swap position of main area in spare area */
108 u32 spare_offset;
Igor Opaniuk344833a2019-11-03 16:49:44 +0100[diff] [blame^]109
110 /* Actual for iMX7 only */
111 u32 onfi_sync_enable;
112 u32 onfi_sync_speed;
113 u32 onfi_sync_nand_data;
114 u32 reserved2[6];
115 u32 disbbm_search;
116 u32 disbbm_search_limit;
117 u32 reserved3[15];
118 u32 read_retry_enable;
119 u32 reserved4[1];
120 u32 fill_to_1024[183];
Shyam Sainif63ef492019-06-14 13:05:33 +0530[diff] [blame]121};
122
123#endif /* _IMX_NAND_BCB_H_ */