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git01.mediatek.com / filogic / uboot / 33e34be6f961cec4c2241408caeee28f25960c3f / . / arch / arm / dts / k3-j721s2-main.dtsi
blob: 976ba1e95abadf4aa58519e08cf58b8e6bbb0e83 [file] [log] [blame]
Aswath Govindraju0e548f02022-01-25 20:56:40 +0530[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for J721S2 SoC Family Main Domain peripherals
4 *
5 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
6 */
7
8&cbass_main {
9 msmc_ram: sram@70000000 {
10 compatible = "mmio-sram";
11 reg = <0x0 0x70000000 0x0 0x400000>;
12 #address-cells = <1>;
13 #size-cells = <1>;
14 ranges = <0x0 0x0 0x70000000 0x400000>;
15
16 atf-sram@0 {
17 reg = <0x0 0x20000>;
18 };
19
20 tifs-sram@1f0000 {
21 reg = <0x1f0000 0x10000>;
22 };
23
24 l3cache-sram@200000 {
25 reg = <0x200000 0x200000>;
26 };
27 };
28
29 gic500: interrupt-controller@1800000 {
30 compatible = "arm,gic-v3";
31 #address-cells = <2>;
32 #size-cells = <2>;
33 ranges;
34 #interrupt-cells = <3>;
35 interrupt-controller;
36 reg = <0x00 0x01800000 0x00 0x200000>, /* GICD */
37 <0x00 0x01900000 0x00 0x100000>; /* GICR */
38
39 /* vcpumntirq: virtual CPU interface maintenance interrupt */
40 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
41
42 gic_its: msi-controller@1820000 {
43 compatible = "arm,gic-v3-its";
44 reg = <0x00 0x01820000 0x00 0x10000>;
45 socionext,synquacer-pre-its = <0x1000000 0x400000>;
46 msi-controller;
47 #msi-cells = <1>;
48 };
49 };
50
51 main_gpio_intr: interrupt-controller@a00000 {
52 compatible = "ti,sci-intr";
53 reg = <0x00 0x00a00000 0x00 0x800>;
54 ti,intr-trigger-type = <1>;
55 interrupt-controller;
56 interrupt-parent = <&gic500>;
57 #interrupt-cells = <1>;
58 ti,sci = <&sms>;
59 ti,sci-dev-id = <148>;
60 ti,interrupt-ranges = <8 360 56>;
61 };
62
63 main_pmx0: pinctrl@11c000 {
64 compatible = "pinctrl-single";
65 /* Proxy 0 addressing */
66 reg = <0x0 0x11c000 0x0 0x120>;
67 #pinctrl-cells = <1>;
68 pinctrl-single,register-width = <32>;
69 pinctrl-single,function-mask = <0xffffffff>;
70 };
71
72 main_uart0: serial@2800000 {
73 compatible = "ti,j721e-uart", "ti,am654-uart";
74 reg = <0x00 0x02800000 0x00 0x200>;
75 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
76 current-speed = <115200>;
77 clocks = <&k3_clks 146 3>;
78 clock-names = "fclk";
79 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
80 };
81
82 main_uart1: serial@2810000 {
83 compatible = "ti,j721e-uart", "ti,am654-uart";
84 reg = <0x00 0x02810000 0x00 0x200>;
85 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
86 current-speed = <115200>;
87 clocks = <&k3_clks 350 3>;
88 clock-names = "fclk";
89 power-domains = <&k3_pds 350 TI_SCI_PD_EXCLUSIVE>;
90 };
91
92 main_uart2: serial@2820000 {
93 compatible = "ti,j721e-uart", "ti,am654-uart";
94 reg = <0x00 0x02820000 0x00 0x200>;
95 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
96 current-speed = <115200>;
97 clocks = <&k3_clks 351 3>;
98 clock-names = "fclk";
99 power-domains = <&k3_pds 351 TI_SCI_PD_EXCLUSIVE>;
100 };
101
102 main_uart3: serial@2830000 {
103 compatible = "ti,j721e-uart", "ti,am654-uart";
104 reg = <0x00 0x02830000 0x00 0x200>;
105 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
106 current-speed = <115200>;
107 clocks = <&k3_clks 352 3>;
108 clock-names = "fclk";
109 power-domains = <&k3_pds 352 TI_SCI_PD_EXCLUSIVE>;
110 };
111
112 main_uart4: serial@2840000 {
113 compatible = "ti,j721e-uart", "ti,am654-uart";
114 reg = <0x00 0x02840000 0x00 0x200>;
115 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
116 current-speed = <115200>;
117 clocks = <&k3_clks 353 3>;
118 clock-names = "fclk";
119 power-domains = <&k3_pds 353 TI_SCI_PD_EXCLUSIVE>;
120 };
121
122 main_uart5: serial@2850000 {
123 compatible = "ti,j721e-uart", "ti,am654-uart";
124 reg = <0x00 0x02850000 0x00 0x200>;
125 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
126 current-speed = <115200>;
127 clocks = <&k3_clks 354 3>;
128 clock-names = "fclk";
129 power-domains = <&k3_pds 354 TI_SCI_PD_EXCLUSIVE>;
130 };
131
132 main_uart6: serial@2860000 {
133 compatible = "ti,j721e-uart", "ti,am654-uart";
134 reg = <0x00 0x02860000 0x00 0x200>;
135 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
136 current-speed = <115200>;
137 clocks = <&k3_clks 355 3>;
138 clock-names = "fclk";
139 power-domains = <&k3_pds 355 TI_SCI_PD_EXCLUSIVE>;
140 };
141
142 main_uart7: serial@2870000 {
143 compatible = "ti,j721e-uart", "ti,am654-uart";
144 reg = <0x00 0x02870000 0x00 0x200>;
145 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
146 current-speed = <115200>;
147 clocks = <&k3_clks 356 3>;
148 clock-names = "fclk";
149 power-domains = <&k3_pds 356 TI_SCI_PD_EXCLUSIVE>;
150 };
151
152 main_uart8: serial@2880000 {
153 compatible = "ti,j721e-uart", "ti,am654-uart";
154 reg = <0x00 0x02880000 0x00 0x200>;
155 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
156 current-speed = <115200>;
157 clocks = <&k3_clks 357 3>;
158 clock-names = "fclk";
159 power-domains = <&k3_pds 357 TI_SCI_PD_EXCLUSIVE>;
160 };
161
162 main_uart9: serial@2890000 {
163 compatible = "ti,j721e-uart", "ti,am654-uart";
164 reg = <0x00 0x02890000 0x00 0x200>;
165 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
166 current-speed = <115200>;
167 clocks = <&k3_clks 358 3>;
168 clock-names = "fclk";
169 power-domains = <&k3_pds 358 TI_SCI_PD_EXCLUSIVE>;
170 };
171
172 main_gpio0: gpio@600000 {
173 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
174 reg = <0x00 0x00600000 0x00 0x100>;
175 gpio-controller;
176 #gpio-cells = <2>;
177 interrupt-parent = <&main_gpio_intr>;
178 interrupts = <145>, <146>, <147>, <148>, <149>;
179 interrupt-controller;
180 #interrupt-cells = <2>;
181 ti,ngpio = <66>;
182 ti,davinci-gpio-unbanked = <0>;
183 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
184 clocks = <&k3_clks 111 0>;
185 clock-names = "gpio";
186 };
187
188 main_gpio2: gpio@610000 {
189 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
190 reg = <0x00 0x00610000 0x00 0x100>;
191 gpio-controller;
192 #gpio-cells = <2>;
193 interrupt-parent = <&main_gpio_intr>;
194 interrupts = <154>, <155>, <156>, <157>, <158>;
195 interrupt-controller;
196 #interrupt-cells = <2>;
197 ti,ngpio = <66>;
198 ti,davinci-gpio-unbanked = <0>;
199 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
200 clocks = <&k3_clks 112 0>;
201 clock-names = "gpio";
202 };
203
204 main_gpio4: gpio@620000 {
205 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
206 reg = <0x00 0x00620000 0x00 0x100>;
207 gpio-controller;
208 #gpio-cells = <2>;
209 interrupt-parent = <&main_gpio_intr>;
210 interrupts = <163>, <164>, <165>, <166>, <167>;
211 interrupt-controller;
212 #interrupt-cells = <2>;
213 ti,ngpio = <66>;
214 ti,davinci-gpio-unbanked = <0>;
215 power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
216 clocks = <&k3_clks 113 0>;
217 clock-names = "gpio";
218 };
219
220 main_gpio6: gpio@630000 {
221 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
222 reg = <0x00 0x00630000 0x00 0x100>;
223 gpio-controller;
224 #gpio-cells = <2>;
225 interrupt-parent = <&main_gpio_intr>;
226 interrupts = <172>, <173>, <174>, <175>, <176>;
227 interrupt-controller;
228 #interrupt-cells = <2>;
229 ti,ngpio = <66>;
230 ti,davinci-gpio-unbanked = <0>;
231 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
232 clocks = <&k3_clks 114 0>;
233 clock-names = "gpio";
234 };
235
236 main_i2c0: i2c@2000000 {
237 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
238 reg = <0x00 0x02000000 0x00 0x100>;
239 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
240 #address-cells = <1>;
241 #size-cells = <0>;
242 clocks = <&k3_clks 214 1>;
243 clock-names = "fck";
244 power-domains = <&k3_pds 214 TI_SCI_PD_EXCLUSIVE>;
245 };
246
247 main_i2c1: i2c@2010000 {
248 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
249 reg = <0x00 0x02010000 0x00 0x100>;
250 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
251 #address-cells = <1>;
252 #size-cells = <0>;
253 clocks = <&k3_clks 215 1>;
254 clock-names = "fck";
255 power-domains = <&k3_pds 215 TI_SCI_PD_EXCLUSIVE>;
256 };
257
258 main_i2c2: i2c@2020000 {
259 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
260 reg = <0x00 0x02020000 0x00 0x100>;
261 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
262 #address-cells = <1>;
263 #size-cells = <0>;
264 clocks = <&k3_clks 216 1>;
265 clock-names = "fck";
266 power-domains = <&k3_pds 216 TI_SCI_PD_EXCLUSIVE>;
267 };
268
269 main_i2c3: i2c@2030000 {
270 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
271 reg = <0x00 0x02030000 0x00 0x100>;
272 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
273 #address-cells = <1>;
274 #size-cells = <0>;
275 clocks = <&k3_clks 217 1>;
276 clock-names = "fck";
277 power-domains = <&k3_pds 217 TI_SCI_PD_EXCLUSIVE>;
278 };
279
280 main_i2c4: i2c@2040000 {
281 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
282 reg = <0x00 0x02040000 0x00 0x100>;
283 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
284 #address-cells = <1>;
285 #size-cells = <0>;
286 clocks = <&k3_clks 218 1>;
287 clock-names = "fck";
288 power-domains = <&k3_pds 218 TI_SCI_PD_EXCLUSIVE>;
289 };
290
291 main_i2c5: i2c@2050000 {
292 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
293 reg = <0x00 0x02050000 0x00 0x100>;
294 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
295 #address-cells = <1>;
296 #size-cells = <0>;
297 clocks = <&k3_clks 219 1>;
298 clock-names = "fck";
299 power-domains = <&k3_pds 219 TI_SCI_PD_EXCLUSIVE>;
300 };
301
302 main_i2c6: i2c@2060000 {
303 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
304 reg = <0x00 0x02060000 0x00 0x100>;
305 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
306 #address-cells = <1>;
307 #size-cells = <0>;
308 clocks = <&k3_clks 220 1>;
309 clock-names = "fck";
310 power-domains = <&k3_pds 220 TI_SCI_PD_EXCLUSIVE>;
311 };
312
313 main_sdhci0: mmc@4f80000 {
314 compatible = "ti,j721e-sdhci-8bit";
315 reg = <0x00 0x04f80000 0x00 0x1000>,
316 <0x00 0x04f88000 0x00 0x400>;
317 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
318 power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>;
319 clocks = <&k3_clks 98 7>, <&k3_clks 98 1>;
320 clock-names = "clk_ahb", "clk_xin";
321 assigned-clocks = <&k3_clks 98 1>;
322 assigned-clock-parents = <&k3_clks 98 2>;
323 bus-width = <8>;
324 ti,otap-del-sel-legacy = <0x0>;
325 ti,otap-del-sel-mmc-hs = <0x0>;
326 ti,otap-del-sel-ddr52 = <0x6>;
327 ti,otap-del-sel-hs200 = <0x8>;
328 ti,otap-del-sel-hs400 = <0x5>;
329 ti,itap-del-sel-legacy = <0x10>;
330 ti,itap-del-sel-mmc-hs = <0xa>;
331 ti,strobe-sel = <0x77>;
332 ti,clkbuf-sel = <0x7>;
333 ti,trm-icp = <0x8>;
334 mmc-ddr-1_8v;
335 mmc-hs200-1_8v;
336 mmc-hs400-1_8v;
337 dma-coherent;
338 };
339
340 main_sdhci1: mmc@4fb0000 {
341 compatible = "ti,j721e-sdhci-4bit";
342 reg = <0x00 0x04fb0000 0x00 0x1000>,
343 <0x00 0x04fb8000 0x00 0x400>;
344 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
345 power-domains = <&k3_pds 99 TI_SCI_PD_EXCLUSIVE>;
346 clocks = <&k3_clks 99 8>, <&k3_clks 99 1>;
347 clock-names = "clk_ahb", "clk_xin";
348 assigned-clocks = <&k3_clks 99 1>;
349 assigned-clock-parents = <&k3_clks 99 2>;
350 bus-width = <4>;
351 ti,otap-del-sel-legacy = <0x0>;
352 ti,otap-del-sel-sd-hs = <0x0>;
353 ti,otap-del-sel-sdr12 = <0xf>;
354 ti,otap-del-sel-sdr25 = <0xf>;
355 ti,otap-del-sel-sdr50 = <0xc>;
356 ti,otap-del-sel-sdr104 = <0x5>;
357 ti,otap-del-sel-ddr50 = <0xc>;
358 ti,itap-del-sel-legacy = <0x0>;
359 ti,itap-del-sel-sd-hs = <0x0>;
360 ti,itap-del-sel-sdr12 = <0x0>;
361 ti,itap-del-sel-sdr25 = <0x0>;
362 ti,clkbuf-sel = <0x7>;
363 ti,trm-icp = <0x8>;
364 dma-coherent;
365 /* Masking support for SDR104 capability */
366 // sdhci-caps-mask = <0x00000003 0x00000000>;
367 };
368
369 main_navss: bus@30000000 {
370 compatible = "simple-mfd";
371 #address-cells = <2>;
372 #size-cells = <2>;
373 ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
374 ti,sci-dev-id = <224>;
375 dma-coherent;
376 dma-ranges;
377
378 main_navss_intr: interrupt-controller@310e0000 {
379 compatible = "ti,sci-intr";
380 reg = <0x00 0x310e0000 0x00 0x4000>;
381 ti,intr-trigger-type = <4>;
382 interrupt-controller;
383 interrupt-parent = <&gic500>;
384 #interrupt-cells = <1>;
385 ti,sci = <&sms>;
386 ti,sci-dev-id = <227>;
387 ti,interrupt-ranges = <0 64 64>,
388 <64 448 64>,
389 <128 672 64>;
390 };
391
392 main_udmass_inta: msi-controller@33d00000 {
393 compatible = "ti,sci-inta";
394 reg = <0x00 0x33d00000 0x00 0x100000>;
395 interrupt-controller;
396 #interrupt-cells = <0>;
397 interrupt-parent = <&main_navss_intr>;
398 msi-controller;
399 ti,sci = <&sms>;
400 ti,sci-dev-id = <265>;
401 ti,interrupt-ranges = <0 0 256>;
402 };
403
404 secure_proxy_main: mailbox@32c00000 {
405 compatible = "ti,am654-secure-proxy";
406 #mbox-cells = <1>;
407 reg-names = "target_data", "rt", "scfg";
408 reg = <0x00 0x32c00000 0x00 0x100000>,
409 <0x00 0x32400000 0x00 0x100000>,
410 <0x00 0x32800000 0x00 0x100000>;
411 interrupt-names = "rx_011";
412 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
413 };
414
415 hwspinlock: spinlock@30e00000 {
416 compatible = "ti,am654-hwspinlock";
417 reg = <0x00 0x30e00000 0x00 0x1000>;
418 #hwlock-cells = <1>;
419 };
420
421 mailbox0_cluster0: mailbox@31f80000 {
422 compatible = "ti,am654-mailbox";
423 reg = <0x00 0x31f80000 0x00 0x200>;
424 #mbox-cells = <1>;
425 ti,mbox-num-users = <4>;
426 ti,mbox-num-fifos = <16>;
427 interrupt-parent = <&main_navss_intr>;
428 };
429
430 mailbox0_cluster1: mailbox@31f81000 {
431 compatible = "ti,am654-mailbox";
432 reg = <0x00 0x31f81000 0x00 0x200>;
433 #mbox-cells = <1>;
434 ti,mbox-num-users = <4>;
435 ti,mbox-num-fifos = <16>;
436 interrupt-parent = <&main_navss_intr>;
437 };
438
439 mailbox0_cluster2: mailbox@31f82000 {
440 compatible = "ti,am654-mailbox";
441 reg = <0x00 0x31f82000 0x00 0x200>;
442 #mbox-cells = <1>;
443 ti,mbox-num-users = <4>;
444 ti,mbox-num-fifos = <16>;
445 interrupt-parent = <&main_navss_intr>;
446 };
447
448 mailbox0_cluster3: mailbox@31f83000 {
449 compatible = "ti,am654-mailbox";
450 reg = <0x00 0x31f83000 0x00 0x200>;
451 #mbox-cells = <1>;
452 ti,mbox-num-users = <4>;
453 ti,mbox-num-fifos = <16>;
454 interrupt-parent = <&main_navss_intr>;
455 };
456
457 mailbox0_cluster4: mailbox@31f84000 {
458 compatible = "ti,am654-mailbox";
459 reg = <0x00 0x31f84000 0x00 0x200>;
460 #mbox-cells = <1>;
461 ti,mbox-num-users = <4>;
462 ti,mbox-num-fifos = <16>;
463 interrupt-parent = <&main_navss_intr>;
464 };
465
466 mailbox0_cluster5: mailbox@31f85000 {
467 compatible = "ti,am654-mailbox";
468 reg = <0x00 0x31f85000 0x00 0x200>;
469 #mbox-cells = <1>;
470 ti,mbox-num-users = <4>;
471 ti,mbox-num-fifos = <16>;
472 interrupt-parent = <&main_navss_intr>;
473 };
474
475 mailbox0_cluster6: mailbox@31f86000 {
476 compatible = "ti,am654-mailbox";
477 reg = <0x00 0x31f86000 0x00 0x200>;
478 #mbox-cells = <1>;
479 ti,mbox-num-users = <4>;
480 ti,mbox-num-fifos = <16>;
481 interrupt-parent = <&main_navss_intr>;
482 };
483
484 mailbox0_cluster7: mailbox@31f87000 {
485 compatible = "ti,am654-mailbox";
486 reg = <0x00 0x31f87000 0x00 0x200>;
487 #mbox-cells = <1>;
488 ti,mbox-num-users = <4>;
489 ti,mbox-num-fifos = <16>;
490 interrupt-parent = <&main_navss_intr>;
491 };
492
493 mailbox0_cluster8: mailbox@31f88000 {
494 compatible = "ti,am654-mailbox";
495 reg = <0x00 0x31f88000 0x00 0x200>;
496 #mbox-cells = <1>;
497 ti,mbox-num-users = <4>;
498 ti,mbox-num-fifos = <16>;
499 interrupt-parent = <&main_navss_intr>;
500 };
501
502 mailbox0_cluster9: mailbox@31f89000 {
503 compatible = "ti,am654-mailbox";
504 reg = <0x00 0x31f89000 0x00 0x200>;
505 #mbox-cells = <1>;
506 ti,mbox-num-users = <4>;
507 ti,mbox-num-fifos = <16>;
508 interrupt-parent = <&main_navss_intr>;
509 };
510
511 mailbox0_cluster10: mailbox@31f8a000 {
512 compatible = "ti,am654-mailbox";
513 reg = <0x00 0x31f8a000 0x00 0x200>;
514 #mbox-cells = <1>;
515 ti,mbox-num-users = <4>;
516 ti,mbox-num-fifos = <16>;
517 interrupt-parent = <&main_navss_intr>;
518 };
519
520 mailbox0_cluster11: mailbox@31f8b000 {
521 compatible = "ti,am654-mailbox";
522 reg = <0x00 0x31f8b000 0x00 0x200>;
523 #mbox-cells = <1>;
524 ti,mbox-num-users = <4>;
525 ti,mbox-num-fifos = <16>;
526 interrupt-parent = <&main_navss_intr>;
527 };
528
529 mailbox1_cluster0: mailbox@31f90000 {
530 compatible = "ti,am654-mailbox";
531 reg = <0x00 0x31f90000 0x00 0x200>;
532 #mbox-cells = <1>;
533 ti,mbox-num-users = <4>;
534 ti,mbox-num-fifos = <16>;
535 interrupt-parent = <&main_navss_intr>;
536 };
537
538 mailbox1_cluster1: mailbox@31f91000 {
539 compatible = "ti,am654-mailbox";
540 reg = <0x00 0x31f91000 0x00 0x200>;
541 #mbox-cells = <1>;
542 ti,mbox-num-users = <4>;
543 ti,mbox-num-fifos = <16>;
544 interrupt-parent = <&main_navss_intr>;
545 };
546
547 mailbox1_cluster2: mailbox@31f92000 {
548 compatible = "ti,am654-mailbox";
549 reg = <0x00 0x31f92000 0x00 0x200>;
550 #mbox-cells = <1>;
551 ti,mbox-num-users = <4>;
552 ti,mbox-num-fifos = <16>;
553 interrupt-parent = <&main_navss_intr>;
554 };
555
556 mailbox1_cluster3: mailbox@31f93000 {
557 compatible = "ti,am654-mailbox";
558 reg = <0x00 0x31f93000 0x00 0x200>;
559 #mbox-cells = <1>;
560 ti,mbox-num-users = <4>;
561 ti,mbox-num-fifos = <16>;
562 interrupt-parent = <&main_navss_intr>;
563 };
564
565 mailbox1_cluster4: mailbox@31f94000 {
566 compatible = "ti,am654-mailbox";
567 reg = <0x00 0x31f94000 0x00 0x200>;
568 #mbox-cells = <1>;
569 ti,mbox-num-users = <4>;
570 ti,mbox-num-fifos = <16>;
571 interrupt-parent = <&main_navss_intr>;
572 };
573
574 mailbox1_cluster5: mailbox@31f95000 {
575 compatible = "ti,am654-mailbox";
576 reg = <0x00 0x31f95000 0x00 0x200>;
577 #mbox-cells = <1>;
578 ti,mbox-num-users = <4>;
579 ti,mbox-num-fifos = <16>;
580 interrupt-parent = <&main_navss_intr>;
581 };
582
583 mailbox1_cluster6: mailbox@31f96000 {
584 compatible = "ti,am654-mailbox";
585 reg = <0x00 0x31f96000 0x00 0x200>;
586 #mbox-cells = <1>;
587 ti,mbox-num-users = <4>;
588 ti,mbox-num-fifos = <16>;
589 interrupt-parent = <&main_navss_intr>;
590 };
591
592 mailbox1_cluster7: mailbox@31f97000 {
593 compatible = "ti,am654-mailbox";
594 reg = <0x00 0x31f97000 0x00 0x200>;
595 #mbox-cells = <1>;
596 ti,mbox-num-users = <4>;
597 ti,mbox-num-fifos = <16>;
598 interrupt-parent = <&main_navss_intr>;
599 };
600
601 mailbox1_cluster8: mailbox@31f98000 {
602 compatible = "ti,am654-mailbox";
603 reg = <0x00 0x31f98000 0x00 0x200>;
604 #mbox-cells = <1>;
605 ti,mbox-num-users = <4>;
606 ti,mbox-num-fifos = <16>;
607 interrupt-parent = <&main_navss_intr>;
608 };
609
610 mailbox1_cluster9: mailbox@31f99000 {
611 compatible = "ti,am654-mailbox";
612 reg = <0x00 0x31f99000 0x00 0x200>;
613 #mbox-cells = <1>;
614 ti,mbox-num-users = <4>;
615 ti,mbox-num-fifos = <16>;
616 interrupt-parent = <&main_navss_intr>;
617 };
618
619 mailbox1_cluster10: mailbox@31f9a000 {
620 compatible = "ti,am654-mailbox";
621 reg = <0x00 0x31f9a000 0x00 0x200>;
622 #mbox-cells = <1>;
623 ti,mbox-num-users = <4>;
624 ti,mbox-num-fifos = <16>;
625 interrupt-parent = <&main_navss_intr>;
626 };
627
628 mailbox1_cluster11: mailbox@31f9b000 {
629 compatible = "ti,am654-mailbox";
630 reg = <0x00 0x31f9b000 0x00 0x200>;
631 #mbox-cells = <1>;
632 ti,mbox-num-users = <4>;
633 ti,mbox-num-fifos = <16>;
634 interrupt-parent = <&main_navss_intr>;
635 };
636
637 main_ringacc: ringacc@3c000000 {
638 compatible = "ti,am654-navss-ringacc";
639 reg = <0x0 0x3c000000 0x0 0x400000>,
640 <0x0 0x38000000 0x0 0x400000>,
641 <0x0 0x31120000 0x0 0x100>,
642 <0x0 0x33000000 0x0 0x40000>;
643 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
644 ti,num-rings = <1024>;
645 ti,sci-rm-range-gp-rings = <0x1>;
646 ti,sci = <&sms>;
647 ti,sci-dev-id = <259>;
648 msi-parent = <&main_udmass_inta>;
649 };
650
651 main_udmap: dma-controller@31150000 {
652 compatible = "ti,j721e-navss-main-udmap";
653 reg = <0x0 0x31150000 0x0 0x100>,
654 <0x0 0x34000000 0x0 0x80000>,
655 <0x0 0x35000000 0x0 0x200000>;
656 reg-names = "gcfg", "rchanrt", "tchanrt";
657 msi-parent = <&main_udmass_inta>;
658 #dma-cells = <1>;
659
660 ti,sci = <&sms>;
661 ti,sci-dev-id = <263>;
662 ti,ringacc = <&main_ringacc>;
663
664 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
665 <0x0f>, /* TX_HCHAN */
666 <0x10>; /* TX_UHCHAN */
667 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
668 <0x0b>, /* RX_HCHAN */
669 <0x0c>; /* RX_UHCHAN */
670 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
671 };
672
673 cpts@310d0000 {
674 compatible = "ti,j721e-cpts";
675 reg = <0x0 0x310d0000 0x0 0x400>;
676 reg-names = "cpts";
677 clocks = <&k3_clks 226 5>;
678 clock-names = "cpts";
679 interrupts-extended = <&main_navss_intr 391>;
680 interrupt-names = "cpts";
681 ti,cpts-periodic-outputs = <6>;
682 ti,cpts-ext-ts-inputs = <8>;
683 };
684 };
685
686 main_mcan0: can@2701000 {
687 compatible = "bosch,m_can";
688 reg = <0x00 0x02701000 0x00 0x200>,
689 <0x00 0x02708000 0x00 0x8000>;
690 reg-names = "m_can", "message_ram";
691 power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
692 clocks = <&k3_clks 182 0>, <&k3_clks 182 1>;
693 clock-names = "hclk", "cclk";
694 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
695 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
696 interrupt-names = "int0", "int1";
697 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
698 };
699
700 main_mcan1: can@2711000 {
701 compatible = "bosch,m_can";
702 reg = <0x00 0x02711000 0x00 0x200>,
703 <0x00 0x02718000 0x00 0x8000>;
704 reg-names = "m_can", "message_ram";
705 power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>;
706 clocks = <&k3_clks 183 0>, <&k3_clks 183 1>;
707 clock-names = "hclk", "cclk";
708 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
709 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
710 interrupt-names = "int0", "int1";
711 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
712 };
713
714 main_mcan2: can@2721000 {
715 compatible = "bosch,m_can";
716 reg = <0x00 0x02721000 0x00 0x200>,
717 <0x00 0x02728000 0x00 0x8000>;
718 reg-names = "m_can", "message_ram";
719 power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>;
720 clocks = <&k3_clks 184 0>, <&k3_clks 184 1>;
721 clock-names = "hclk", "cclk";
722 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
723 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
724 interrupt-names = "int0", "int1";
725 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
726 };
727
728 main_mcan3: can@2731000 {
729 compatible = "bosch,m_can";
730 reg = <0x00 0x02731000 0x00 0x200>,
731 <0x00 0x02738000 0x00 0x8000>;
732 reg-names = "m_can", "message_ram";
733 power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>;
734 clocks = <&k3_clks 185 0>, <&k3_clks 185 1>;
735 clock-names = "hclk", "cclk";
736 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
737 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
738 interrupt-names = "int0", "int1";
739 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
740 };
741
742 main_mcan4: can@2741000 {
743 compatible = "bosch,m_can";
744 reg = <0x00 0x02741000 0x00 0x200>,
745 <0x00 0x02748000 0x00 0x8000>;
746 reg-names = "m_can", "message_ram";
747 power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>;
748 clocks = <&k3_clks 186 0>, <&k3_clks 186 1>;
749 clock-names = "hclk", "cclk";
750 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
751 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
752 interrupt-names = "int0", "int1";
753 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
754 };
755
756 main_mcan5: can@2751000 {
757 compatible = "bosch,m_can";
758 reg = <0x00 0x02751000 0x00 0x200>,
759 <0x00 0x02758000 0x00 0x8000>;
760 reg-names = "m_can", "message_ram";
761 power-domains = <&k3_pds 187 TI_SCI_PD_EXCLUSIVE>;
762 clocks = <&k3_clks 187 0>, <&k3_clks 187 1>;
763 clock-names = "hclk", "cclk";
764 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
765 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
766 interrupt-names = "int0", "int1";
767 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
768 };
769
770 main_mcan6: can@2761000 {
771 compatible = "bosch,m_can";
772 reg = <0x00 0x02761000 0x00 0x200>,
773 <0x00 0x02768000 0x00 0x8000>;
774 reg-names = "m_can", "message_ram";
775 power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
776 clocks = <&k3_clks 188 0>, <&k3_clks 188 1>;
777 clock-names = "hclk", "cclk";
778 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
779 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
780 interrupt-names = "int0", "int1";
781 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
782 };
783
784 main_mcan7: can@2771000 {
785 compatible = "bosch,m_can";
786 reg = <0x00 0x02771000 0x00 0x200>,
787 <0x00 0x02778000 0x00 0x8000>;
788 reg-names = "m_can", "message_ram";
789 power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
790 clocks = <&k3_clks 189 0>, <&k3_clks 189 1>;
791 clock-names = "hclk", "cclk";
792 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
793 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
794 interrupt-names = "int0", "int1";
795 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
796 };
797
798 main_mcan8: can@2781000 {
799 compatible = "bosch,m_can";
800 reg = <0x00 0x02781000 0x00 0x200>,
801 <0x00 0x02788000 0x00 0x8000>;
802 reg-names = "m_can", "message_ram";
803 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
804 clocks = <&k3_clks 190 0>, <&k3_clks 190 1>;
805 clock-names = "hclk", "cclk";
806 interrupts = <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>,
807 <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>;
808 interrupt-names = "int0", "int1";
809 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
810 };
811
812 main_mcan9: can@2791000 {
813 compatible = "bosch,m_can";
814 reg = <0x00 0x02791000 0x00 0x200>,
815 <0x00 0x02798000 0x00 0x8000>;
816 reg-names = "m_can", "message_ram";
817 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
818 clocks = <&k3_clks 191 0>, <&k3_clks 191 1>;
819 clock-names = "hclk", "cclk";
820 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>,
821 <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>;
822 interrupt-names = "int0", "int1";
823 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
824 };
825
826 main_mcan10: can@27a1000 {
827 compatible = "bosch,m_can";
828 reg = <0x00 0x027a1000 0x00 0x200>,
829 <0x00 0x027a8000 0x00 0x8000>;
830 reg-names = "m_can", "message_ram";
831 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
832 clocks = <&k3_clks 192 0>, <&k3_clks 192 1>;
833 clock-names = "hclk", "cclk";
834 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>,
835 <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
836 interrupt-names = "int0", "int1";
837 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
838 };
839
840 main_mcan11: can@27b1000 {
841 compatible = "bosch,m_can";
842 reg = <0x00 0x027b1000 0x00 0x200>,
843 <0x00 0x027b8000 0x00 0x8000>;
844 reg-names = "m_can", "message_ram";
845 power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
846 clocks = <&k3_clks 193 0>, <&k3_clks 193 1>;
847 clock-names = "hclk", "cclk";
848 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>,
849 <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
850 interrupt-names = "int0", "int1";
851 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
852 };
853
854 main_mcan12: can@27c1000 {
855 compatible = "bosch,m_can";
856 reg = <0x00 0x027c1000 0x00 0x200>,
857 <0x00 0x027c8000 0x00 0x8000>;
858 reg-names = "m_can", "message_ram";
859 power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>;
860 clocks = <&k3_clks 194 0>, <&k3_clks 194 1>;
861 clock-names = "hclk", "cclk";
862 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
863 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>;
864 interrupt-names = "int0", "int1";
865 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
866 };
867
868 main_mcan13: can@27d1000 {
869 compatible = "bosch,m_can";
870 reg = <0x00 0x027d1000 0x00 0x200>,
871 <0x00 0x027d8000 0x00 0x8000>;
872 reg-names = "m_can", "message_ram";
873 power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>;
874 clocks = <&k3_clks 195 0>, <&k3_clks 195 1>;
875 clock-names = "hclk", "cclk";
876 interrupts = <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
877 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>;
878 interrupt-names = "int0", "int1";
879 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
880 };
881
882 main_mcan14: can@2681000 {
883 compatible = "bosch,m_can";
884 reg = <0x00 0x02681000 0x00 0x200>,
885 <0x00 0x02688000 0x00 0x8000>;
886 reg-names = "m_can", "message_ram";
887 power-domains = <&k3_pds 197 TI_SCI_PD_EXCLUSIVE>;
888 clocks = <&k3_clks 197 0>, <&k3_clks 197 1>;
889 clock-names = "hclk", "cclk";
890 interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
891 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>;
892 interrupt-names = "int0", "int1";
893 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
894 };
895
896 main_mcan15: can@2691000 {
897 compatible = "bosch,m_can";
898 reg = <0x00 0x02691000 0x00 0x200>,
899 <0x00 0x02698000 0x00 0x8000>;
900 reg-names = "m_can", "message_ram";
901 power-domains = <&k3_pds 199 TI_SCI_PD_EXCLUSIVE>;
902 clocks = <&k3_clks 199 0>, <&k3_clks 199 1>;
903 clock-names = "hclk", "cclk";
904 interrupts = <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
905 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>;
906 interrupt-names = "int0", "int1";
907 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
908 };
909
910 main_mcan16: can@26a1000 {
911 compatible = "bosch,m_can";
912 reg = <0x00 0x026a1000 0x00 0x200>,
913 <0x00 0x026a8000 0x00 0x8000>;
914 reg-names = "m_can", "message_ram";
915 power-domains = <&k3_pds 201 TI_SCI_PD_EXCLUSIVE>;
916 clocks = <&k3_clks 201 0>, <&k3_clks 201 1>;
917 clock-names = "hclk", "cclk";
918 interrupts = <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>,
919 <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>;
920 interrupt-names = "int0", "int1";
921 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
922 };
923
924 main_mcan17: can@26b1000 {
925 compatible = "bosch,m_can";
926 reg = <0x00 0x026b1000 0x00 0x200>,
927 <0x00 0x026b8000 0x00 0x8000>;
928 reg-names = "m_can", "message_ram";
929 power-domains = <&k3_pds 206 TI_SCI_PD_EXCLUSIVE>;
930 clocks = <&k3_clks 206 0>, <&k3_clks 206 1>;
931 clock-names = "hclk", "cclk";
932 interrupts = <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>,
933 <GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>;
934 interrupt-names = "int0", "int1";
935 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
936 };
937};