arch/arm/dts/imx6qdl-mba6.dtsi

// SPDX-License-Identifier: GPL-2.0+
//
// Copyright (C) 2020 TQ-Systems GmbH

/ {
	aliases {
		mmc1 = &usdhc2;
	};

	chosen {
		linux,stdout-path = &uart2;
		stdout-path = &uart2;
	};

	regulators {
		reg_mba6_3p3v: regulator@1 {
			compatible = "regulator-fixed";
			regulator-name = "supply-mba6-3p3v";
			reg = <1>;
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
			regulator-always-on;
		};

		reg_otgvbus: regulator@2 {
			compatible = "regulator-fixed";
			reg = <2>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_reg_otgpwr>;
			regulator-name = "otg-vbus-supply";
			regulator-min-microvolt = <5000000>;
			regulator-max-microvolt = <5000000>;
			gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
			enable-active-high;
			vin_supply = <&reg_3p3v>;
		};
	};
};

&fec {
	phy-mode = "rgmii-id";
	phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
	phy-reset-duration = <1>;
	phy-reset-post-delay = <100>;
	phy-handle = <&ethphy>;
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy: ethernet-phy@3 {
			compatible = "ethernet-phy-id0022.1622",
				     "ethernet-phy-ieee802.3-c22";
			reg = <3>;
			force-master;
			max-speed = <1000>;
			interrupt-parent = <&gpio1>;
			interrupts = <28 IRQ_TYPE_LEVEL_LOW>;
		};
	};
};

&iomuxc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_hog>;

	mba6 {
		pinctrl_enet: enetgrp {
			fsl,pins = <
				/* FEC phy IRQ */
				MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28     0x00011008
				/* FEC phy reset */
				MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25   0x1b099
				/* DSE = 100, 100k up, SPEED = MED */
				MX6QDL_PAD_ENET_MDIO__ENET_MDIO       0xb0a0
				MX6QDL_PAD_ENET_MDC__ENET_MDC         0xb0a0
				/* DSE = 111, pull 100k up */
				MX6QDL_PAD_RGMII_TXC__RGMII_TXC       0xb038
				MX6QDL_PAD_RGMII_TD0__RGMII_TD0       0xb038
				MX6QDL_PAD_RGMII_TD1__RGMII_TD1       0xb038
				MX6QDL_PAD_RGMII_TD2__RGMII_TD2       0xb038
				MX6QDL_PAD_RGMII_TD3__RGMII_TD3       0xb038
				MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0xb038
				/* DSE = 111, pull external */
				MX6QDL_PAD_RGMII_RXC__RGMII_RXC       0x0038
				MX6QDL_PAD_RGMII_RD0__RGMII_RD0       0x0038
				MX6QDL_PAD_RGMII_RD1__RGMII_RD1       0x0038
				MX6QDL_PAD_RGMII_RD2__RGMII_RD2       0x0038
				MX6QDL_PAD_RGMII_RD3__RGMII_RD3       0x0038
				MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x0038
				/* HYS = 1, DSE = 111, 100k up, SPEED = HIGH */
				MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK  0x1b0f0
			>;
		};

		pinctrl_hog: hoggrp {
			fsl,pins = <
				MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x0001b099 /* LCD.PWR_EN */
				MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x0001b099 /* LCD.RESET */
				/* LCD.CONTRAST -> Rev 0100 only, not used on Rev.0200*/
				MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x0001b099

				MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x0001b099
				MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x0001b099
				MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x0001b099

				MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x0001b099
				MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x0001b099
				MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x0001b099
				MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x0001b099
				MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x0001b099
				MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x0001b099
				MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x0001b099

				MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x0001b099
				MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x0001b099
				MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x0001b099
				MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x0001b099
				MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x0001b099

				MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x0001b099
				MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x0001b099
				MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x0001b099
				MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x0001b099

				MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x0001b099
				MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x0001b099
				MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x0001b099

				MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x0001b099
				MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x0001b099
			>;
		};

		pinctrl_reg_otgpwr: regotgpwrgrp {
			fsl,pins = <
				/* OTG_PWR */
				MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x0001b099
			>;
		};

		pinctrl_uart2: uart2grp {
			fsl,pins = <
				MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b099
				MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b099
			>;
		};

		pinctrl_usdhc2: usdhc2grp {
			fsl,pins = <
				/* CLK: 47k Pup SPD_LOW DSE 40Ohm SRE_FAST HYS */
				MX6QDL_PAD_SD2_CLK__SD2_CLK    0x00017071
				/* SD2: 47k Pup SPD_LOW DSE 80Ohm SRE_FAST HYS */
				MX6QDL_PAD_SD2_CMD__SD2_CMD    0x00017059
				MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x00017059
				MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x00017059
				MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x00017059
				MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x00017059

				MX6QDL_PAD_GPIO_4__GPIO1_IO04  0x0001b099 /* usdhc2 CD */
				MX6QDL_PAD_GPIO_2__GPIO1_IO02  0x0001b099 /* usdhc2 WP */
			>;
		};

		pinctrl_usbotg: usbotggrp {
			fsl,pins = <
				MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x0001b0b0
				MX6QDL_PAD_GPIO_1__USB_OTG_ID  0x00017059
			>;
		};
	};
};

&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	status = "okay";
};

&usbh1 {
	disable-over-current;
	status = "okay";
};

&usbotg {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usbotg>;
	dr_mode = "otg";
	vbus-supply = <&reg_otgvbus>;
	status = "okay";
};

&usdhc2 { /* Baseboard Slot */
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc2>;
	vmmc-supply = <&reg_mba6_3p3v>;
	bus-width = <4>;
	no-1-8-v;
	cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
	wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
	status = "okay";
};

&wdog1 {
	status = "okay";
};