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git01.mediatek.com / filogic / uboot / 33e34be6f961cec4c2241408caeee28f25960c3f / . / arch / arm / dts / am335x-icev2.dts
blob: 2a1b3a53e9baeffb933d3aa708aebb573dbd5ac8 [file] [log] [blame]
Lokesh Vutla7ecf1962016-05-16 11:47:28 +0530[diff] [blame]1/*
2 * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/*
10 * AM335x ICE V2 board
11 * http://www.ti.com/tool/tmdsice3359
12 */
13
14/dts-v1/;
15
16#include "am33xx.dtsi"
17
18/ {
19 model = "TI AM3359 ICE-V2";
20 compatible = "ti,am3359-icev2", "ti,am33xx";
21
22 chosen {
23 stdout-path = &uart3;
24 tick-timer = &timer2;
25 };
26
27 memory {
28 device_type = "memory";
29 reg = <0x80000000 0x10000000>; /* 256 MB */
30 };
31
32 vbat: fixedregulator@0 {
33 compatible = "regulator-fixed";
34 regulator-name = "vbat";
35 regulator-min-microvolt = <5000000>;
36 regulator-max-microvolt = <5000000>;
37 regulator-boot-on;
38 };
39
40 vtt_fixed: fixedregulator@1 {
41 compatible = "regulator-fixed";
42 regulator-name = "vtt";
43 regulator-min-microvolt = <1500000>;
44 regulator-max-microvolt = <1500000>;
45 gpio = <&gpio0 18 GPIO_ACTIVE_HIGH>;
46 regulator-always-on;
47 regulator-boot-on;
48 enable-active-high;
49 };
50
51 leds@0 {
52 compatible = "gpio-leds";
53
54 led@0 {
55 label = "out0";
56 gpios = <&tpic2810 0 GPIO_ACTIVE_HIGH>;
57 default-state = "off";
58 };
59
60 led@1 {
61 label = "out1";
62 gpios = <&tpic2810 1 GPIO_ACTIVE_HIGH>;
63 default-state = "off";
64 };
65
66 led@2 {
67 label = "out2";
68 gpios = <&tpic2810 2 GPIO_ACTIVE_HIGH>;
69 default-state = "off";
70 };
71
72 led@3 {
73 label = "out3";
74 gpios = <&tpic2810 3 GPIO_ACTIVE_HIGH>;
75 default-state = "off";
76 };
77
78 led@4 {
79 label = "out4";
80 gpios = <&tpic2810 4 GPIO_ACTIVE_HIGH>;
81 default-state = "off";
82 };
83
84 led@5 {
85 label = "out5";
86 gpios = <&tpic2810 5 GPIO_ACTIVE_HIGH>;
87 default-state = "off";
88 };
89
90 led@6 {
91 label = "out6";
92 gpios = <&tpic2810 6 GPIO_ACTIVE_HIGH>;
93 default-state = "off";
94 };
95
96 led@7 {
97 label = "out7";
98 gpios = <&tpic2810 7 GPIO_ACTIVE_HIGH>;
99 default-state = "off";
100 };
101 };
102
103 /* Tricolor status LEDs */
104 leds@1 {
105 compatible = "gpio-leds";
106 pinctrl-names = "default";
107 pinctrl-0 = <&user_leds>;
108
109 led@0 {
110 label = "status0:red:cpu0";
111 gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>;
112 default-state = "off";
113 linux,default-trigger = "cpu0";
114 };
115
116 led@1 {
117 label = "status0:green:usr";
118 gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>;
119 default-state = "off";
120 };
121
122 led@2 {
123 label = "status0:yellow:usr";
124 gpios = <&gpio3 9 GPIO_ACTIVE_HIGH>;
125 default-state = "off";
126 };
127
128 led@3 {
129 label = "status1:red:mmc0";
130 gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;
131 default-state = "off";
132 linux,default-trigger = "mmc0";
133 };
134
135 led@4 {
136 label = "status1:green:usr";
137 gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>;
138 default-state = "off";
139 };
140
141 led@5 {
142 label = "status1:yellow:usr";
143 gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>;
144 default-state = "off";
145 };
146 };
147};
148
149&am33xx_pinmux {
150 user_leds: user_leds {
151 pinctrl-single,pins = <
152 AM33XX_IOPAD(0x91c, PIN_OUTPUT | MUX_MODE7) /* (J18) gmii1_txd3.gpio0[16] */
153 AM33XX_IOPAD(0x920, PIN_OUTPUT | MUX_MODE7) /* (K15) gmii1_txd2.gpio0[17] */
154 AM33XX_IOPAD(0x9b0, PIN_OUTPUT | MUX_MODE7) /* (A15) xdma_event_intr0.gpio0[19] */
155 AM33XX_IOPAD(0x9b4, PIN_OUTPUT | MUX_MODE7) /* (D14) xdma_event_intr1.gpio0[20] */
156 AM33XX_IOPAD(0x880, PIN_OUTPUT | MUX_MODE7) /* (U9) gpmc_csn1.gpio1[30] */
157 AM33XX_IOPAD(0x92c, PIN_OUTPUT | MUX_MODE7) /* (K18) gmii1_txclk.gpio3[9] */
158 >;
159 };
160
161 mmc0_pins_default: mmc0_pins_default {
162 pinctrl-single,pins = <
163 AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) /* (F17) mmc0_dat3.mmc0_dat3 */
164 AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) /* (F18) mmc0_dat2.mmc0_dat2 */
165 AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) /* (G15) mmc0_dat1.mmc0_dat1 */
166 AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) /* (G16) mmc0_dat0.mmc0_dat0 */
167 AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) /* (G17) mmc0_clk.mmc0_clk */
168 AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) /* (G18) mmc0_cmd.mmc0_cmd */
169 AM33XX_IOPAD(0x960, PIN_INPUT_PULLUP | MUX_MODE5) /* (C15) spi0_cs1.mmc0_sdcd */
170 >;
171 };
172
173 i2c0_pins_default: i2c0_pins_default {
174 pinctrl-single,pins = <
175 AM33XX_IOPAD(0x988, PIN_INPUT | MUX_MODE0) /* (C17) I2C0_SDA.I2C0_SDA */
176 AM33XX_IOPAD(0x98c, PIN_INPUT | MUX_MODE0) /* (C16) I2C0_SCL.I2C0_SCL */
177 >;
178 };
179
180 spi0_pins_default: spi0_pins_default {
181 pinctrl-single,pins = <
182 AM33XX_IOPAD(0x950, PIN_INPUT_PULLUP | MUX_MODE0) /* (A17) spi0_sclk.spi0_sclk */
183 AM33XX_IOPAD(0x954, PIN_INPUT_PULLUP | MUX_MODE0) /* (B17) spi0_d0.spi0_d0 */
184 AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0) /* (B16) spi0_d1.spi0_d1 */
185 AM33XX_IOPAD(0x95c, PIN_INPUT_PULLUP | MUX_MODE0) /* (A16) spi0_cs0.spi0_cs0 */
186 >;
187 };
188
189 uart3_pins_default: uart3_pins_default {
190 pinctrl-single,pins = <
191 AM33XX_IOPAD(0x934, PIN_INPUT_PULLUP | MUX_MODE1) /* (L17) gmii1_rxd3.uart3_rxd */
192 AM33XX_IOPAD(0x938, PIN_OUTPUT_PULLUP | MUX_MODE1) /* (L16) gmii1_rxd2.uart3_txd */
193 >;
194 };
195
196 cpsw_default: cpsw_default {
197 pinctrl-single,pins = <
198 /* Slave 1, RMII mode */
199 AM33XX_IOPAD(0x90c, (PIN_INPUT_PULLUP | MUX_MODE1)) /* mii1_crs.rmii1_crs_dv */
200 AM33XX_IOPAD(0x944, (PIN_INPUT_PULLUP | MUX_MODE0)) /* rmii1_refclk.rmii1_refclk */
201 AM33XX_IOPAD(0x940, (PIN_INPUT_PULLUP | MUX_MODE1)) /* mii1_rxd0.rmii1_rxd0 */
202 AM33XX_IOPAD(0x93c, (PIN_INPUT_PULLUP | MUX_MODE1)) /* mii1_rxd1.rmii1_rxd1 */
203 AM33XX_IOPAD(0x910, (PIN_INPUT_PULLUP | MUX_MODE1)) /* mii1_rxerr.rmii1_rxerr */
204 AM33XX_IOPAD(0x928, (PIN_OUTPUT_PULLDOWN | MUX_MODE1)) /* mii1_txd0.rmii1_txd0 */
205 AM33XX_IOPAD(0x924, (PIN_OUTPUT_PULLDOWN | MUX_MODE1)) /* mii1_txd1.rmii1_txd1 */
206 AM33XX_IOPAD(0x914, (PIN_OUTPUT_PULLDOWN | MUX_MODE1)) /* mii1_txen.rmii1_txen */
207 /* Slave 2, RMII mode */
208 AM33XX_IOPAD(0x870, (PIN_INPUT_PULLUP | MUX_MODE3)) /* gpmc_wait0.rmii2_crs_dv */
209 AM33XX_IOPAD(0x908, (PIN_INPUT_PULLUP | MUX_MODE1)) /* mii1_col.rmii2_refclk */
210 AM33XX_IOPAD(0x86c, (PIN_INPUT_PULLUP | MUX_MODE3)) /* gpmc_a11.rmii2_rxd0 */
211 AM33XX_IOPAD(0x868, (PIN_INPUT_PULLUP | MUX_MODE3)) /* gpmc_a10.rmii2_rxd1 */
212 AM33XX_IOPAD(0x874, (PIN_INPUT_PULLUP | MUX_MODE3)) /* gpmc_wpn.rmii2_rxerr */
213 AM33XX_IOPAD(0x854, (PIN_OUTPUT_PULLDOWN | MUX_MODE3)) /* gpmc_a5.rmii2_txd0 */
214 AM33XX_IOPAD(0x850, (PIN_OUTPUT_PULLDOWN | MUX_MODE3)) /* gpmc_a4.rmii2_txd1 */
215 AM33XX_IOPAD(0x840, (PIN_OUTPUT_PULLDOWN | MUX_MODE3)) /* gpmc_a0.rmii2_txen */
216 >;
217 };
218
219 cpsw_sleep: cpsw_sleep {
220 pinctrl-single,pins = <
221 /* Slave 1 reset value */
222 AM33XX_IOPAD(0x90c, (PIN_INPUT_PULLDOWN | MUX_MODE7))
223 AM33XX_IOPAD(0x944, (PIN_INPUT_PULLDOWN | MUX_MODE7))
224 AM33XX_IOPAD(0x940, (PIN_INPUT_PULLDOWN | MUX_MODE7))
225 AM33XX_IOPAD(0x93c, (PIN_INPUT_PULLDOWN | MUX_MODE7))
226 AM33XX_IOPAD(0x910, (PIN_INPUT_PULLDOWN | MUX_MODE7))
227 AM33XX_IOPAD(0x928, (PIN_INPUT_PULLDOWN | MUX_MODE7))
228 AM33XX_IOPAD(0x924, (PIN_INPUT_PULLDOWN | MUX_MODE7))
229 AM33XX_IOPAD(0x914, (PIN_INPUT_PULLDOWN | MUX_MODE7))
230
231 /* Slave 2 reset value */
232 AM33XX_IOPAD(0x870, (PIN_INPUT_PULLDOWN | MUX_MODE7))
233 AM33XX_IOPAD(0x908, (PIN_INPUT_PULLDOWN | MUX_MODE7))
234 AM33XX_IOPAD(0x86c, (PIN_INPUT_PULLDOWN | MUX_MODE7))
235 AM33XX_IOPAD(0x868, (PIN_INPUT_PULLDOWN | MUX_MODE7))
236 AM33XX_IOPAD(0x874, (PIN_INPUT_PULLDOWN | MUX_MODE7))
237 AM33XX_IOPAD(0x854, (PIN_INPUT_PULLDOWN | MUX_MODE7))
238 AM33XX_IOPAD(0x850, (PIN_INPUT_PULLDOWN | MUX_MODE7))
239 AM33XX_IOPAD(0x840, (PIN_INPUT_PULLDOWN | MUX_MODE7))
240 >;
241 };
242
243 davinci_mdio_default: davinci_mdio_default {
244 pinctrl-single,pins = <
245 /* MDIO */
246 AM33XX_IOPAD(0x948, (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)) /* mdio_data.mdio_data */
247 AM33XX_IOPAD(0x94c, (PIN_OUTPUT_PULLUP | MUX_MODE0)) /* mdio_clk.mdio_clk */
248 >;
249 };
250
251 davinci_mdio_sleep: davinci_mdio_sleep {
252 pinctrl-single,pins = <
253 /* MDIO reset value */
254 AM33XX_IOPAD(0x948, (PIN_INPUT_PULLDOWN | MUX_MODE7))
255 AM33XX_IOPAD(0x94c, (PIN_INPUT_PULLDOWN | MUX_MODE7))
256 >;
257 };
258};
259
260&i2c0 {
261 pinctrl-names = "default";
262 pinctrl-0 = <&i2c0_pins_default>;
263
264 status = "okay";
265 clock-frequency = <400000>;
266
267 tps: power-controller@2d {
268 reg = <0x2d>;
269 };
270
271 tpic2810: gpio@60 {
272 compatible = "ti,tpic2810";
273 reg = <0x60>;
274 gpio-controller;
275 #gpio-cells = <2>;
276 };
277};
278
279#include "tps65910.dtsi"
280
281&tps {
282 vcc1-supply = <&vbat>;
283 vcc2-supply = <&vbat>;
284 vcc3-supply = <&vbat>;
285 vcc4-supply = <&vbat>;
286 vcc5-supply = <&vbat>;
287 vcc6-supply = <&vbat>;
288 vcc7-supply = <&vbat>;
289 vccio-supply = <&vbat>;
290
291 regulators {
292 vrtc_reg: regulator@0 {
293 regulator-always-on;
294 };
295
296 vio_reg: regulator@1 {
297 regulator-always-on;
298 };
299
300 vdd1_reg: regulator@2 {
301 regulator-name = "vdd_mpu";
302 regulator-min-microvolt = <912500>;
303 regulator-max-microvolt = <1326000>;
304 regulator-boot-on;
305 regulator-always-on;
306 };
307
308 vdd2_reg: regulator@3 {
309 regulator-name = "vdd_core";
310 regulator-min-microvolt = <912500>;
311 regulator-max-microvolt = <1144000>;
312 regulator-boot-on;
313 regulator-always-on;
314 };
315
316 vdd3_reg: regulator@4 {
317 regulator-always-on;
318 };
319
320 vdig1_reg: regulator@5 {
321 regulator-always-on;
322 };
323
324 vdig2_reg: regulator@6 {
325 regulator-always-on;
326 };
327
328 vpll_reg: regulator@7 {
329 regulator-always-on;
330 };
331
332 vdac_reg: regulator@8 {
333 regulator-always-on;
334 };
335
336 vaux1_reg: regulator@9 {
337 regulator-always-on;
338 };
339
340 vaux2_reg: regulator@10 {
341 regulator-always-on;
342 };
343
344 vaux33_reg: regulator@11 {
345 regulator-always-on;
346 };
347
348 vmmc_reg: regulator@12 {
349 regulator-min-microvolt = <1800000>;
350 regulator-max-microvolt = <3300000>;
351 regulator-always-on;
352 };
353 };
354};
355
356&mmc1 {
357 status = "okay";
358 vmmc-supply = <&vmmc_reg>;
359 bus-width = <4>;
360 pinctrl-names = "default";
361 pinctrl-0 = <&mmc0_pins_default>;
362};
363
364&gpio0 {
365 /* Do not idle the GPIO used for holding the VTT regulator */
366 ti,no-reset-on-init;
367 ti,no-idle-on-init;
368
369 p7 {
370 gpio-hog;
371 gpios = <7 GPIO_ACTIVE_HIGH>;
372 output-high;
373 line-name = "FET_SWITCH_CTRL";
374 };
375};
376
377&uart3 {
378 pinctrl-names = "default";
379 pinctrl-0 = <&uart3_pins_default>;
380 status = "okay";
381};
382
383&gpio3 {
384 p4 {
385 gpio-hog;
386 gpios = <4 GPIO_ACTIVE_HIGH>;
387 output-high;
388 line-name = "PR1_MII_CTRL";
389 };
390
391 p10 {
392 gpio-hog;
393 gpios = <10 GPIO_ACTIVE_HIGH>;
394 output-high;
395 line-name = "MUX_MII_CTRL";
396 };
397};
398
399&cpsw_emac0 {
Grygorii Strashkoa6f37dc2019-08-31 10:30:34 +0300[diff] [blame]400 phy-handle = <&ethphy0>;
Lokesh Vutla7ecf1962016-05-16 11:47:28 +0530[diff] [blame]401 phy-mode = "rmii";
402 dual_emac_res_vlan = <1>;
403};
404
405&cpsw_emac1 {
Grygorii Strashkoa6f37dc2019-08-31 10:30:34 +0300[diff] [blame]406 phy-handle = <&ethphy1>;
Lokesh Vutla7ecf1962016-05-16 11:47:28 +0530[diff] [blame]407 phy-mode = "rmii";
408 dual_emac_res_vlan = <2>;
409};
410
411&mac {
412 pinctrl-names = "default", "sleep";
413 pinctrl-0 = <&cpsw_default>;
414 pinctrl-1 = <&cpsw_sleep>;
415 status = "okay";
416 dual_emac;
417};
418
419&phy_sel {
420 rmii-clock-ext;
421};
422
423&davinci_mdio {
424 pinctrl-names = "default", "sleep";
425 pinctrl-0 = <&davinci_mdio_default>;
426 pinctrl-1 = <&davinci_mdio_sleep>;
427 status = "okay";
428 reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>;
429 reset-delay-us = <2>; /* PHY datasheet states 1uS min */
Grygorii Strashkoa6f37dc2019-08-31 10:30:34 +0300[diff] [blame]430
431 ethphy0: ethernet-phy@1 {
432 reg = <1>;
433 };
434
435 ethphy1: ethernet-phy@3 {
436 reg = <3>;
437 };
Lokesh Vutla7ecf1962016-05-16 11:47:28 +0530[diff] [blame]438};
Faiz Abbas027e6582020-09-14 12:11:13 +0530[diff] [blame]439
440&spi0 {
441 status = "okay";
442 pinctrl-names = "default";
443 pinctrl-0 = <&spi0_pins_default>;
444
445 sn65hvs882@1 {
446 compatible = "pisosr-gpio";
447 gpio-controller;
448 #gpio-cells = <2>;
449
450 load-gpios = <&gpio3 18 GPIO_ACTIVE_LOW>;
451
452 reg = <1>;
453 spi-max-frequency = <1000000>;
454 spi-cpol;
455 };
456
457 spi_nor: flash@0 {
458 #address-cells = <1>;
459 #size-cells = <1>;
460 compatible = "winbond,w25q64", "jedec,spi-nor";
461 spi-max-frequency = <80000000>;
462 m25p,fast-read;
463 reg = <0>;
464
465 partition@0 {
466 label = "u-boot-spl";
467 reg = <0x0 0x80000>;
468 read-only;
469 };
470
471 partition@1 {
472 label = "u-boot";
473 reg = <0x80000 0x100000>;
474 read-only;
475 };
476
477 partition@2 {
478 label = "u-boot-env";
479 reg = <0x180000 0x20000>;
480 read-only;
481 };
482
483 partition@3 {
484 label = "misc";
485 reg = <0x1A0000 0x660000>;
486 };
487 };
488};