blob: c3ca171b83ba1ca263b653aa53af77ed7a7271dd [file] [log] [blame]
Simon Glass582ba6e2019-12-06 21:42:58 -07001/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright 2019 Google LLC
4 */
5
6#ifndef _ASM_ARCH_UART_H
7#define _ASM_ARCH_UART_H
8
Simon Glass9cfd95b2021-03-15 18:00:31 +13009#include <dt-structs.h>
Simon Glass298530a2020-12-19 10:40:05 -070010#include <ns16550.h>
11
12/**
13 * struct apl_ns16550_plat - platform data for the APL UART
14 *
15 * Note that when of-platdata is in use, apl_ns16550_of_to_plat() actually
16 * copies the ns16550_plat contents to the start of this struct, meaning that
17 * dtplat is no-longer valid. This is done so that the ns16550 driver can use
18 * dev_get_plat() without any offsets or adjustments.
19 */
20struct apl_ns16550_plat {
21#if CONFIG_IS_ENABLED(OF_PLATDATA)
22 struct dtd_intel_apl_ns16550 dtplat;
23#endif
24 struct ns16550_plat ns16550;
25};
26
Simon Glass582ba6e2019-12-06 21:42:58 -070027/**
28 * apl_uart_init() - Set up the APL UART device and clock
29 *
30 * This enables the PCI device, sets up the MMIO region and turns on the clock
31 * using LPSS.
32 *
33 * The UART won't actually work unless the GPIO settings are correct and the
34 * signals actually exit the SoC. See board_debug_uart_init() for that.
35 */
Simon Glass298530a2020-12-19 10:40:05 -070036void apl_uart_init(pci_dev_t bdf, ulong base);
Simon Glass582ba6e2019-12-06 21:42:58 -070037
38#endif