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git01.mediatek.com / filogic / uboot / 33d25b34b5a8a98a490426bba0c3345df8a688e3 / . / include / linux / mtd / fsl_upm.h
blob: 0a949bca0de37c539e7a181d0c2f3d6850ffb135 [file] [log] [blame]
Anton Vorontsov6ab97e92008-01-14 23:09:32 +0300[diff] [blame]1/*
2 * FSL UPM NAND driver
3 *
4 * Copyright (C) 2007 MontaVista Software, Inc.
5 * Anton Vorontsov <avorontsov@ru.mvista.com>
6 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]7 * SPDX-License-Identifier: GPL-2.0+
Anton Vorontsov6ab97e92008-01-14 23:09:32 +0300[diff] [blame]8 */
9
10#ifndef __LINUX_MTD_NAND_FSL_UPM
11#define __LINUX_MTD_NAND_FSL_UPM
12
13#include <linux/mtd/nand.h>
14
Wolfgang Grandegger64de8db2009-02-11 18:38:23 +0100[diff] [blame]15#define FSL_UPM_WAIT_RUN_PATTERN 0x1
16#define FSL_UPM_WAIT_WRITE_BYTE 0x2
17#define FSL_UPM_WAIT_WRITE_BUFFER 0x4
18
Anton Vorontsov6ab97e92008-01-14 23:09:32 +0300[diff] [blame]19struct fsl_upm {
Anton Vorontsov6ab97e92008-01-14 23:09:32 +0300[diff] [blame]20 void __iomem *mdr;
21 void __iomem *mxmr;
22 void __iomem *mar;
23 void __iomem *io_addr;
24};
25
26struct fsl_upm_nand {
27 struct fsl_upm upm;
28
29 int width;
30 int upm_cmd_offset;
31 int upm_addr_offset;
Wolfgang Grandeggerac205332009-02-11 18:38:22 +0100[diff] [blame]32 int upm_mar_chip_offset;
Wolfgang Grandegger64de8db2009-02-11 18:38:23 +0100[diff] [blame]33 int wait_flags;
Wolfgang Grandeggerf1540442009-02-11 18:38:21 +0100[diff] [blame]34 int (*dev_ready)(int chip_nr);
Anton Vorontsov6ab97e92008-01-14 23:09:32 +0300[diff] [blame]35 int chip_delay;
Wolfgang Grandeggerf1540442009-02-11 18:38:21 +0100[diff] [blame]36 int chip_offset;
37 int chip_nr;
Anton Vorontsov67166032008-06-12 11:10:21 -0500[diff] [blame]38
39 /* no need to fill */
40 int last_ctrl;
Anton Vorontsov6ab97e92008-01-14 23:09:32 +0300[diff] [blame]41};
42
43extern int fsl_upm_nand_init(struct nand_chip *chip, struct fsl_upm_nand *fun);
44
45#endif