Haavard Skinnemoen | d347f44 | 2007-10-29 13:02:54 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2007 Atmel Corporation |
| 3 | * |
| 4 | * Configuration settings for the ATSTK1003 CPU daughterboard |
| 5 | * |
Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 6 | * SPDX-License-Identifier: GPL-2.0+ |
Haavard Skinnemoen | d347f44 | 2007-10-29 13:02:54 +0100 | [diff] [blame] | 7 | */ |
| 8 | #ifndef __CONFIG_H |
| 9 | #define __CONFIG_H |
| 10 | |
Andreas Bießmann | 94156fa | 2010-11-04 23:15:30 +0000 | [diff] [blame] | 11 | #include <asm/arch/hardware.h> |
Haavard Skinnemoen | 23f62f1 | 2008-05-19 11:36:28 +0200 | [diff] [blame] | 12 | |
Andreas Bießmann | 43a25da | 2011-04-18 04:12:37 +0000 | [diff] [blame] | 13 | #define CONFIG_AVR32 |
| 14 | #define CONFIG_AT32AP |
| 15 | #define CONFIG_AT32AP7001 |
| 16 | #define CONFIG_ATSTK1003 |
| 17 | #define CONFIG_ATSTK1000 |
Haavard Skinnemoen | d347f44 | 2007-10-29 13:02:54 +0100 | [diff] [blame] | 18 | |
Haavard Skinnemoen | d347f44 | 2007-10-29 13:02:54 +0100 | [diff] [blame] | 19 | /* |
| 20 | * Timer clock frequency. We're using the CPU-internal COUNT register |
| 21 | * for this, so this is equivalent to the CPU core clock frequency |
| 22 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 23 | #define CONFIG_SYS_HZ 1000 |
Haavard Skinnemoen | d347f44 | 2007-10-29 13:02:54 +0100 | [diff] [blame] | 24 | |
| 25 | /* |
| 26 | * Set up the PLL to run at 140 MHz, the CPU to run at the PLL |
| 27 | * frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the |
| 28 | * PLL frequency. |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 29 | * (CONFIG_SYS_OSC0_HZ * CONFIG_SYS_PLL0_MUL) / CONFIG_SYS_PLL0_DIV = PLL MHz |
Haavard Skinnemoen | d347f44 | 2007-10-29 13:02:54 +0100 | [diff] [blame] | 30 | */ |
Andreas Bießmann | 43a25da | 2011-04-18 04:12:37 +0000 | [diff] [blame] | 31 | #define CONFIG_PLL |
| 32 | #define CONFIG_SYS_POWER_MANAGER |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 33 | #define CONFIG_SYS_OSC0_HZ 20000000 |
| 34 | #define CONFIG_SYS_PLL0_DIV 1 |
| 35 | #define CONFIG_SYS_PLL0_MUL 7 |
| 36 | #define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16 |
Haavard Skinnemoen | d347f44 | 2007-10-29 13:02:54 +0100 | [diff] [blame] | 37 | /* |
| 38 | * Set the CPU running at: |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 39 | * PLL / (2^CONFIG_SYS_CLKDIV_CPU) = CPU MHz |
Haavard Skinnemoen | d347f44 | 2007-10-29 13:02:54 +0100 | [diff] [blame] | 40 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 41 | #define CONFIG_SYS_CLKDIV_CPU 0 |
Haavard Skinnemoen | d347f44 | 2007-10-29 13:02:54 +0100 | [diff] [blame] | 42 | /* |
| 43 | * Set the HSB running at: |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 44 | * PLL / (2^CONFIG_SYS_CLKDIV_HSB) = HSB MHz |
Haavard Skinnemoen | d347f44 | 2007-10-29 13:02:54 +0100 | [diff] [blame] | 45 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 46 | #define CONFIG_SYS_CLKDIV_HSB 1 |
Haavard Skinnemoen | d347f44 | 2007-10-29 13:02:54 +0100 | [diff] [blame] | 47 | /* |
| 48 | * Set the PBA running at: |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 49 | * PLL / (2^CONFIG_SYS_CLKDIV_PBA) = PBA MHz |
Haavard Skinnemoen | d347f44 | 2007-10-29 13:02:54 +0100 | [diff] [blame] | 50 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 51 | #define CONFIG_SYS_CLKDIV_PBA 2 |
Haavard Skinnemoen | d347f44 | 2007-10-29 13:02:54 +0100 | [diff] [blame] | 52 | /* |
| 53 | * Set the PBB running at: |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 54 | * PLL / (2^CONFIG_SYS_CLKDIV_PBB) = PBB MHz |
Haavard Skinnemoen | d347f44 | 2007-10-29 13:02:54 +0100 | [diff] [blame] | 55 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 56 | #define CONFIG_SYS_CLKDIV_PBB 1 |
Haavard Skinnemoen | d347f44 | 2007-10-29 13:02:54 +0100 | [diff] [blame] | 57 | |
Haavard Skinnemoen | c6f292f | 2010-08-12 13:52:54 +0700 | [diff] [blame] | 58 | /* Reserve VM regions for SDRAM and NOR flash */ |
| 59 | #define CONFIG_SYS_NR_VM_REGIONS 2 |
| 60 | |
Haavard Skinnemoen | d347f44 | 2007-10-29 13:02:54 +0100 | [diff] [blame] | 61 | /* |
| 62 | * The PLLOPT register controls the PLL like this: |
| 63 | * icp = PLLOPT<2> |
| 64 | * ivco = PLLOPT<1:0> |
| 65 | * |
| 66 | * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz). |
| 67 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 68 | #define CONFIG_SYS_PLL0_OPT 0x04 |
Haavard Skinnemoen | d347f44 | 2007-10-29 13:02:54 +0100 | [diff] [blame] | 69 | |
Andreas Bießmann | 5807e79 | 2010-11-04 23:15:31 +0000 | [diff] [blame] | 70 | #define CONFIG_USART_BASE ATMEL_BASE_USART1 |
| 71 | #define CONFIG_USART_ID 1 |
Haavard Skinnemoen | d347f44 | 2007-10-29 13:02:54 +0100 | [diff] [blame] | 72 | |
| 73 | /* User serviceable stuff */ |
Andreas Bießmann | 43a25da | 2011-04-18 04:12:37 +0000 | [diff] [blame] | 74 | #define CONFIG_DOS_PARTITION |
Haavard Skinnemoen | d347f44 | 2007-10-29 13:02:54 +0100 | [diff] [blame] | 75 | |
Andreas Bießmann | 43a25da | 2011-04-18 04:12:37 +0000 | [diff] [blame] | 76 | #define CONFIG_CMDLINE_TAG |
| 77 | #define CONFIG_SETUP_MEMORY_TAGS |
| 78 | #define CONFIG_INITRD_TAG |
Haavard Skinnemoen | d347f44 | 2007-10-29 13:02:54 +0100 | [diff] [blame] | 79 | |
| 80 | #define CONFIG_STACKSIZE (2048) |
| 81 | |
| 82 | #define CONFIG_BAUDRATE 115200 |
| 83 | #define CONFIG_BOOTARGS \ |
| 84 | "console=ttyS0 root=/dev/mmcblk0p1 rootwait" |
| 85 | |
| 86 | #define CONFIG_BOOTCOMMAND \ |
Sven Schnelle | 8aa9682 | 2011-10-21 14:49:25 +0200 | [diff] [blame] | 87 | "mmc rescan; ext2load mmc 0:1 0x10400000 /boot/uImage; bootm" |
Haavard Skinnemoen | d347f44 | 2007-10-29 13:02:54 +0100 | [diff] [blame] | 88 | |
| 89 | /* |
| 90 | * Only interrupt autoboot if <space> is pressed. Otherwise, garbage |
| 91 | * data on the serial line may interrupt the boot sequence. |
| 92 | */ |
| 93 | #define CONFIG_BOOTDELAY 1 |
Andreas Bießmann | 43a25da | 2011-04-18 04:12:37 +0000 | [diff] [blame] | 94 | #define CONFIG_AUTOBOOT |
| 95 | #define CONFIG_AUTOBOOT_KEYED |
Wolfgang Denk | dd5463b | 2008-07-16 16:38:59 +0200 | [diff] [blame] | 96 | #define CONFIG_AUTOBOOT_PROMPT \ |
| 97 | "Press SPACE to abort autoboot in %d seconds\n", bootdelay |
Haavard Skinnemoen | d347f44 | 2007-10-29 13:02:54 +0100 | [diff] [blame] | 98 | #define CONFIG_AUTOBOOT_DELAY_STR "d" |
| 99 | #define CONFIG_AUTOBOOT_STOP_STR " " |
| 100 | |
| 101 | /* |
| 102 | * Command line configuration. |
| 103 | */ |
| 104 | #include <config_cmd_default.h> |
| 105 | |
| 106 | #define CONFIG_CMD_ASKENV |
| 107 | #define CONFIG_CMD_EXT2 |
| 108 | #define CONFIG_CMD_FAT |
| 109 | #define CONFIG_CMD_JFFS2 |
| 110 | #define CONFIG_CMD_MMC |
| 111 | |
| 112 | #undef CONFIG_CMD_FPGA |
| 113 | #undef CONFIG_CMD_NET |
| 114 | #undef CONFIG_CMD_NFS |
| 115 | #undef CONFIG_CMD_SETGETDCR |
| 116 | #undef CONFIG_CMD_XIMG |
| 117 | |
Andreas Bießmann | 43a25da | 2011-04-18 04:12:37 +0000 | [diff] [blame] | 118 | #define CONFIG_ATMEL_USART |
| 119 | #define CONFIG_PORTMUX_PIO |
| 120 | #define CONFIG_SYS_HSDRAMC |
| 121 | #define CONFIG_MMC |
Sven Schnelle | 8aa9682 | 2011-10-21 14:49:25 +0200 | [diff] [blame] | 122 | #define CONFIG_GENERIC_ATMEL_MCI |
| 123 | #define CONFIG_GENERIC_MMC |
Haavard Skinnemoen | d347f44 | 2007-10-29 13:02:54 +0100 | [diff] [blame] | 124 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 125 | #define CONFIG_SYS_DCACHE_LINESZ 32 |
| 126 | #define CONFIG_SYS_ICACHE_LINESZ 32 |
Haavard Skinnemoen | d347f44 | 2007-10-29 13:02:54 +0100 | [diff] [blame] | 127 | |
| 128 | #define CONFIG_NR_DRAM_BANKS 1 |
| 129 | |
Andreas Bießmann | ab7344a | 2011-06-28 04:15:58 +0000 | [diff] [blame] | 130 | #define CONFIG_SYS_FLASH_CFI |
| 131 | #define CONFIG_FLASH_CFI_DRIVER |
Haavard Skinnemoen | d347f44 | 2007-10-29 13:02:54 +0100 | [diff] [blame] | 132 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 133 | #define CONFIG_SYS_FLASH_BASE 0x00000000 |
| 134 | #define CONFIG_SYS_FLASH_SIZE 0x800000 |
| 135 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 |
| 136 | #define CONFIG_SYS_MAX_FLASH_SECT 135 |
Haavard Skinnemoen | d347f44 | 2007-10-29 13:02:54 +0100 | [diff] [blame] | 137 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 138 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE |
Andreas Bießmann | 71c2bf5 | 2011-04-18 04:12:44 +0000 | [diff] [blame] | 139 | #define CONFIG_SYS_TEXT_BASE 0x00000000 |
Haavard Skinnemoen | d347f44 | 2007-10-29 13:02:54 +0100 | [diff] [blame] | 140 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 141 | #define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE |
| 142 | #define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE |
| 143 | #define CONFIG_SYS_SDRAM_BASE EBI_SDRAM_BASE |
Haavard Skinnemoen | d347f44 | 2007-10-29 13:02:54 +0100 | [diff] [blame] | 144 | |
Andreas Bießmann | 43a25da | 2011-04-18 04:12:37 +0000 | [diff] [blame] | 145 | #define CONFIG_ENV_IS_IN_FLASH |
Jean-Christophe PLAGNIOL-VILLARD | 7e1cda6 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 146 | #define CONFIG_ENV_SIZE 65536 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 147 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE) |
Haavard Skinnemoen | d347f44 | 2007-10-29 13:02:54 +0100 | [diff] [blame] | 148 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 149 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE) |
Haavard Skinnemoen | d347f44 | 2007-10-29 13:02:54 +0100 | [diff] [blame] | 150 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 151 | #define CONFIG_SYS_MALLOC_LEN (256*1024) |
Haavard Skinnemoen | d347f44 | 2007-10-29 13:02:54 +0100 | [diff] [blame] | 152 | |
| 153 | /* Allow 4MB for the kernel run-time image */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 154 | #define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000) |
| 155 | #define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024) |
Haavard Skinnemoen | d347f44 | 2007-10-29 13:02:54 +0100 | [diff] [blame] | 156 | |
| 157 | /* Other configuration settings that shouldn't have to change all that often */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 158 | #define CONFIG_SYS_PROMPT "U-Boot> " |
| 159 | #define CONFIG_SYS_CBSIZE 256 |
| 160 | #define CONFIG_SYS_MAXARGS 16 |
| 161 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) |
Andreas Bießmann | 43a25da | 2011-04-18 04:12:37 +0000 | [diff] [blame] | 162 | #define CONFIG_SYS_LONGHELP |
Haavard Skinnemoen | d347f44 | 2007-10-29 13:02:54 +0100 | [diff] [blame] | 163 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 164 | #define CONFIG_SYS_MEMTEST_START EBI_SDRAM_BASE |
| 165 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x700000) |
| 166 | #define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 } |
Haavard Skinnemoen | d347f44 | 2007-10-29 13:02:54 +0100 | [diff] [blame] | 167 | |
| 168 | #endif /* __CONFIG_H */ |