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goda.yusukefd768072008-01-25 20:46:36 +09001/*
2 * Configuation settings for the Renesas Solutions Migo-R board
3 *
4 * Copyright (C) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
5 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
goda.yusukefd768072008-01-25 20:46:36 +09007 */
8
9#ifndef __MIGO_R_H
10#define __MIGO_R_H
11
12#undef DEBUG
13#define CONFIG_SH 1
14#define CONFIG_SH4 1
15#define CONFIG_CPU_SH7722 1
16#define CONFIG_MIGO_R 1
17
18#define CONFIG_CMD_LOADB
19#define CONFIG_CMD_LOADS
20#define CONFIG_CMD_FLASH
21#define CONFIG_CMD_MEMORY
22#define CONFIG_CMD_NET
23#define CONFIG_CMD_PING
24#define CONFIG_CMD_NFS
goda.yusukefd768072008-01-25 20:46:36 +090025#define CONFIG_CMD_SDRAM
Mike Frysinger78dcaf42009-01-28 19:08:14 -050026#define CONFIG_CMD_SAVEENV
goda.yusukefd768072008-01-25 20:46:36 +090027
28#define CONFIG_BAUDRATE 115200
29#define CONFIG_BOOTDELAY 3
30#define CONFIG_BOOTARGS "console=ttySC0,115200 root=1f01"
goda.yusukefd768072008-01-25 20:46:36 +090031
32#define CONFIG_VERSION_VARIABLE
33#undef CONFIG_SHOW_BOOT_PROGRESS
34
35/* SMC9111 */
Ben Warren0fd6aae2009-10-04 22:37:03 -070036#define CONFIG_SMC91111
goda.yusukefd768072008-01-25 20:46:36 +090037#define CONFIG_SMC91111_BASE (0xB0000000)
38
39/* MEMORY */
40#define MIGO_R_SDRAM_BASE (0x8C000000)
41#define MIGO_R_FLASH_BASE_1 (0xA0000000)
42#define MIGO_R_FLASH_BANK_SIZE (64 * 1024 * 1024)
43
Nobuhiro Iwamatsu66a5a382011-01-17 20:43:40 +090044#define CONFIG_SYS_TEXT_BASE 0x8FFC0000
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020045#define CONFIG_SYS_LONGHELP /* undef to save memory */
46#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
47#define CONFIG_SYS_CBSIZE 256 /* Buffer size for input from the Console */
48#define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */
49#define CONFIG_SYS_MAXARGS 16 /* max args accepted for monitor commands */
50#define CONFIG_SYS_BARGSIZE 512 /* Buffer size for Boot Arguments passed to kernel */
51#define CONFIG_SYS_BAUDRATE_TABLE { 115200 } /* List of legal baudrate settings for this board */
goda.yusukefd768072008-01-25 20:46:36 +090052
53/* SCIF */
Jean-Christophe PLAGNIOL-VILLARD6ce9ea62008-08-13 01:40:38 +020054#define CONFIG_SCIF_CONSOLE 1
goda.yusukefd768072008-01-25 20:46:36 +090055#define CONFIG_CONS_SCIF0 1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020056#undef CONFIG_SYS_CONSOLE_INFO_QUIET /* Suppress display of console
goda.yusukefd768072008-01-25 20:46:36 +090057 information at boot */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020058#undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
59#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
goda.yusukefd768072008-01-25 20:46:36 +090060
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020061#define CONFIG_SYS_MEMTEST_START (MIGO_R_SDRAM_BASE)
62#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
goda.yusukefd768072008-01-25 20:46:36 +090063
64/* Enable alternate, more extensive, memory test */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020065#undef CONFIG_SYS_ALT_MEMTEST
goda.yusukefd768072008-01-25 20:46:36 +090066/* Scratch address used by the alternate memory test */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020067#undef CONFIG_SYS_MEMTEST_SCRATCH
goda.yusukefd768072008-01-25 20:46:36 +090068
69/* Enable temporary baudrate change while serial download */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020070#undef CONFIG_SYS_LOADS_BAUD_CHANGE
goda.yusukefd768072008-01-25 20:46:36 +090071
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020072#define CONFIG_SYS_SDRAM_BASE (MIGO_R_SDRAM_BASE)
goda.yusukefd768072008-01-25 20:46:36 +090073/* maybe more, but if so u-boot doesn't know about it... */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020074#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024)
goda.yusukefd768072008-01-25 20:46:36 +090075/* default load address for scripts ?!? */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020076#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024)
goda.yusukefd768072008-01-25 20:46:36 +090077
78/* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020079#define CONFIG_SYS_MONITOR_BASE (MIGO_R_FLASH_BASE_1)
goda.yusukefd768072008-01-25 20:46:36 +090080/* Monitor size */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020081#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
goda.yusukefd768072008-01-25 20:46:36 +090082/* Size of DRAM reserved for malloc() use */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020083#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020084#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
goda.yusukefd768072008-01-25 20:46:36 +090085
86/* FLASH */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020087#define CONFIG_SYS_FLASH_CFI
Jean-Christophe PLAGNIOL-VILLARD8d94c232008-08-13 01:40:42 +020088#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020089#undef CONFIG_SYS_FLASH_QUIET_TEST
goda.yusukefd768072008-01-25 20:46:36 +090090/* print 'E' for empty sector on flinfo */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020091#define CONFIG_SYS_FLASH_EMPTY_INFO
goda.yusukefd768072008-01-25 20:46:36 +090092/* Physical start address of Flash memory */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020093#define CONFIG_SYS_FLASH_BASE (MIGO_R_FLASH_BASE_1)
goda.yusukefd768072008-01-25 20:46:36 +090094/* Max number of sectors on each Flash chip */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020095#define CONFIG_SYS_MAX_FLASH_SECT 512
goda.yusukefd768072008-01-25 20:46:36 +090096
97/* if you use all NOR Flash , you change dip-switch. Please see MIGO_R01 Manual. */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020098#define CONFIG_SYS_MAX_FLASH_BANKS 1
99#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE + (0 * MIGO_R_FLASH_BANK_SIZE) }
goda.yusukefd768072008-01-25 20:46:36 +0900100
101/* Timeout for Flash erase operations (in ms) */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200102#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000)
goda.yusukefd768072008-01-25 20:46:36 +0900103/* Timeout for Flash write operations (in ms) */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200104#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000)
goda.yusukefd768072008-01-25 20:46:36 +0900105/* Timeout for Flash set sector lock bit operations (in ms) */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200106#define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000)
goda.yusukefd768072008-01-25 20:46:36 +0900107/* Timeout for Flash clear lock bit operations (in ms) */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200108#define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000)
goda.yusukefd768072008-01-25 20:46:36 +0900109
110/* Use hardware flash sectors protection instead of U-Boot software protection */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200111#undef CONFIG_SYS_FLASH_PROTECTION
112#undef CONFIG_SYS_DIRECT_FLASH_TFTP
goda.yusukefd768072008-01-25 20:46:36 +0900113
114/* ENV setting */
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +0200115#define CONFIG_ENV_IS_IN_FLASH
goda.yusukefd768072008-01-25 20:46:36 +0900116#define CONFIG_ENV_OVERWRITE 1
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200117#define CONFIG_ENV_SECT_SIZE (128 * 1024)
118#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200119#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
120/* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
121#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200122#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
goda.yusukefd768072008-01-25 20:46:36 +0900123
124/* Board Clock */
125#define CONFIG_SYS_CLK_FREQ 33333333
Jean-Christophe PLAGNIOL-VILLARD32e6acc2009-06-04 12:06:48 +0200126#define CONFIG_SYS_TMU_CLK_DIV (4) /* 4 (default), 16, 64, 256 or 1024 */
Jean-Christophe PLAGNIOL-VILLARD51704102009-06-04 12:06:47 +0200127#define CONFIG_SYS_HZ 1000
goda.yusukefd768072008-01-25 20:46:36 +0900128
129#endif /* __MIGO_R_H */