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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
wdenk9c53f402003-10-15 23:53:47 +00002/*
Dipen Dudhat5d51bf92011-01-19 12:46:27 +05303 * Copyright 2004, 2007-2011 Freescale Semiconductor, Inc.
Kumar Galadccd9e32009-03-19 02:46:19 -05004 *
wdenk9c53f402003-10-15 23:53:47 +00005 * (C) Copyright 2003 Motorola Inc.
6 * Xianghua Xiao, (X.Xiao@motorola.com)
7 *
8 * (C) Copyright 2000
9 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
wdenk9c53f402003-10-15 23:53:47 +000010 */
11
12#include <common.h>
13#include <ppc_asm.tmpl>
Haiying Wang8cb2af72011-02-11 01:25:30 -060014#include <linux/compiler.h>
wdenk9c53f402003-10-15 23:53:47 +000015#include <asm/processor.h>
Trent Piepho0b691fc2008-12-03 15:16:37 -080016#include <asm/io.h>
wdenk9c53f402003-10-15 23:53:47 +000017
Wolfgang Denk6405a152006-03-31 18:32:53 +020018DECLARE_GLOBAL_DATA_PTR;
19
Prabhakar Kushwaha7e8382f2013-09-03 11:20:15 +053020
21#ifndef CONFIG_SYS_FSL_NUM_CC_PLLS
22#define CONFIG_SYS_FSL_NUM_CC_PLLS 6
23#endif
wdenk9c53f402003-10-15 23:53:47 +000024/* --------------------------------------------------------------- */
25
Prabhakar Kushwahad1698082013-08-16 14:52:26 +053026void get_sys_info(sys_info_t *sys_info)
wdenk9c53f402003-10-15 23:53:47 +000027{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020028 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
Kumar Galadccd9e32009-03-19 02:46:19 -050029#ifdef CONFIG_FSL_CORENET
30 volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR);
Timur Tabi47289422011-08-05 16:15:24 -050031 unsigned int cpu;
Shaveta Leekhadbf0bc82015-01-19 12:46:54 +053032#ifdef CONFIG_HETROGENOUS_CLUSTERS
33 unsigned int dsp_cpu;
34 uint rcw_tmp1, rcw_tmp2;
35#endif
Prabhakar Kushwaha7e8382f2013-09-03 11:20:15 +053036#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
37 int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS;
38#endif
York Sun7c355f52014-10-27 11:31:33 -070039 __maybe_unused u32 svr;
Kumar Galadccd9e32009-03-19 02:46:19 -050040
41 const u8 core_cplx_PLL[16] = {
42 [ 0] = 0, /* CC1 PPL / 1 */
43 [ 1] = 0, /* CC1 PPL / 2 */
44 [ 2] = 0, /* CC1 PPL / 4 */
45 [ 4] = 1, /* CC2 PPL / 1 */
46 [ 5] = 1, /* CC2 PPL / 2 */
47 [ 6] = 1, /* CC2 PPL / 4 */
48 [ 8] = 2, /* CC3 PPL / 1 */
49 [ 9] = 2, /* CC3 PPL / 2 */
50 [10] = 2, /* CC3 PPL / 4 */
51 [12] = 3, /* CC4 PPL / 1 */
52 [13] = 3, /* CC4 PPL / 2 */
53 [14] = 3, /* CC4 PPL / 4 */
54 };
55
Prabhakar Kushwahad1698082013-08-16 14:52:26 +053056 const u8 core_cplx_pll_div[16] = {
Kumar Galadccd9e32009-03-19 02:46:19 -050057 [ 0] = 1, /* CC1 PPL / 1 */
58 [ 1] = 2, /* CC1 PPL / 2 */
59 [ 2] = 4, /* CC1 PPL / 4 */
60 [ 4] = 1, /* CC2 PPL / 1 */
61 [ 5] = 2, /* CC2 PPL / 2 */
62 [ 6] = 4, /* CC2 PPL / 4 */
63 [ 8] = 1, /* CC3 PPL / 1 */
64 [ 9] = 2, /* CC3 PPL / 2 */
65 [10] = 4, /* CC3 PPL / 4 */
66 [12] = 1, /* CC4 PPL / 1 */
67 [13] = 2, /* CC4 PPL / 2 */
68 [14] = 4, /* CC4 PPL / 4 */
69 };
Prabhakar Kushwaha7e8382f2013-09-03 11:20:15 +053070 uint i, freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
Yangbo Lu163beec2015-04-22 13:57:40 +080071#if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV) || \
72 defined(CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK)
Prabhakar Kushwaha7e8382f2013-09-03 11:20:15 +053073 uint rcw_tmp;
74#endif
75 uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
Kumar Galadccd9e32009-03-19 02:46:19 -050076 unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
Srikanth Srinivasanf58c2a42010-02-10 17:32:43 +080077 uint mem_pll_rat;
Kumar Galadccd9e32009-03-19 02:46:19 -050078
Prabhakar Kushwahad1698082013-08-16 14:52:26 +053079 sys_info->freq_systembus = sysclk;
Priyanka Jaine9dcaa82013-12-17 14:25:52 +053080#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
vijay raid84fd502014-04-15 11:34:12 +053081 uint ddr_refclk_sel;
82 unsigned int porsr1_sys_clk;
83 porsr1_sys_clk = in_be32(&gur->porsr1) >> FSL_DCFG_PORSR1_SYSCLK_SHIFT
84 & FSL_DCFG_PORSR1_SYSCLK_MASK;
85 if (porsr1_sys_clk == FSL_DCFG_PORSR1_SYSCLK_DIFF)
86 sys_info->diff_sysclk = 1;
87 else
88 sys_info->diff_sysclk = 0;
89
Priyanka Jaine9dcaa82013-12-17 14:25:52 +053090 /*
91 * DDR_REFCLK_SEL rcw bit is used to determine if DDR PLLS
92 * are driven by separate DDR Refclock or single source
93 * differential clock.
94 */
vijay raid84fd502014-04-15 11:34:12 +053095 ddr_refclk_sel = (in_be32(&gur->rcwsr[5]) >>
Priyanka Jaine9dcaa82013-12-17 14:25:52 +053096 FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_SHIFT) &
97 FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_MASK;
98 /*
vijay raid84fd502014-04-15 11:34:12 +053099 * For single source clocking, both ddrclock and sysclock
Priyanka Jaine9dcaa82013-12-17 14:25:52 +0530100 * are driven by differential sysclock.
101 */
vijay raid84fd502014-04-15 11:34:12 +0530102 if (ddr_refclk_sel == FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK)
Priyanka Jaine9dcaa82013-12-17 14:25:52 +0530103 sys_info->freq_ddrbus = CONFIG_SYS_CLK_FREQ;
vijay raid84fd502014-04-15 11:34:12 +0530104 else
Priyanka Jaine9dcaa82013-12-17 14:25:52 +0530105#endif
York Sun3b5179f2012-10-08 07:44:31 +0000106#ifdef CONFIG_DDR_CLK_FREQ
Priyanka Jaine9dcaa82013-12-17 14:25:52 +0530107 sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
York Sun3b5179f2012-10-08 07:44:31 +0000108#else
Priyanka Jaine9dcaa82013-12-17 14:25:52 +0530109 sys_info->freq_ddrbus = sysclk;
York Sun3b5179f2012-10-08 07:44:31 +0000110#endif
Kumar Galadccd9e32009-03-19 02:46:19 -0500111
Prabhakar Kushwahad1698082013-08-16 14:52:26 +0530112 sys_info->freq_systembus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
York Sunb8a076b2012-10-08 07:44:09 +0000113 mem_pll_rat = (in_be32(&gur->rcwsr[0]) >>
114 FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT)
115 & FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
York Sun7b083df2014-03-28 15:07:27 -0700116#ifdef CONFIG_SYS_FSL_ERRATUM_A007212
117 if (mem_pll_rat == 0) {
118 mem_pll_rat = (in_be32(&gur->rcwsr[0]) >>
119 FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT) &
120 FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
121 }
122#endif
Zang Roy-R619111b1e5cf2013-11-28 13:23:37 +0800123 /* T4240/T4160 Rev2.0 MEM_PLL_RAT uses a value which is half of
124 * T4240/T4160 Rev1.0. eg. It's 12 in Rev1.0, however, for Rev2.0
125 * it uses 6.
York Sun7c355f52014-10-27 11:31:33 -0700126 * T2080 rev 1.1 and later also use half mem_pll comparing with rev 1.0
Zang Roy-R619111b1e5cf2013-11-28 13:23:37 +0800127 */
York Sun0fad3262016-11-21 13:35:41 -0800128#if defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160) || \
York Sunc1845032016-11-21 13:41:30 -0800129 defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081)
York Sun7c355f52014-10-27 11:31:33 -0700130 svr = get_svr();
131 switch (SVR_SOC_VER(svr)) {
132 case SVR_T4240:
133 case SVR_T4160:
134 case SVR_T4120:
135 case SVR_T4080:
136 if (SVR_MAJ(svr) >= 2)
137 mem_pll_rat *= 2;
138 break;
139 case SVR_T2080:
140 case SVR_T2081:
141 if ((SVR_MAJ(svr) > 1) || (SVR_MIN(svr) >= 1))
142 mem_pll_rat *= 2;
143 break;
144 default:
145 break;
146 }
Zang Roy-R619111b1e5cf2013-11-28 13:23:37 +0800147#endif
Srikanth Srinivasanf58c2a42010-02-10 17:32:43 +0800148 if (mem_pll_rat > 2)
Prabhakar Kushwahad1698082013-08-16 14:52:26 +0530149 sys_info->freq_ddrbus *= mem_pll_rat;
Srikanth Srinivasanf58c2a42010-02-10 17:32:43 +0800150 else
Prabhakar Kushwahad1698082013-08-16 14:52:26 +0530151 sys_info->freq_ddrbus = sys_info->freq_systembus * mem_pll_rat;
Kumar Galadccd9e32009-03-19 02:46:19 -0500152
Prabhakar Kushwaha7e8382f2013-09-03 11:20:15 +0530153 for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
154 ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0x3f;
Srikanth Srinivasanf58c2a42010-02-10 17:32:43 +0800155 if (ratio[i] > 4)
Prabhakar Kushwaha7e8382f2013-09-03 11:20:15 +0530156 freq_c_pll[i] = sysclk * ratio[i];
Srikanth Srinivasanf58c2a42010-02-10 17:32:43 +0800157 else
Prabhakar Kushwaha7e8382f2013-09-03 11:20:15 +0530158 freq_c_pll[i] = sys_info->freq_systembus * ratio[i];
Srikanth Srinivasanf58c2a42010-02-10 17:32:43 +0800159 }
Shaveta Leekhadbf0bc82015-01-19 12:46:54 +0530160
York Sund7778f72012-10-08 07:44:11 +0000161#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
162 /*
Prabhakar Kushwaha7e8382f2013-09-03 11:20:15 +0530163 * As per CHASSIS2 architeture total 12 clusters are posible and
York Sund7778f72012-10-08 07:44:11 +0000164 * Each cluster has up to 4 cores, sharing the same PLL selection.
Prabhakar Kushwaha7e8382f2013-09-03 11:20:15 +0530165 * The cluster clock assignment is SoC defined.
166 *
167 * Total 4 clock groups are possible with 3 PLLs each.
168 * as per array indices, clock group A has 0, 1, 2 numbered PLLs &
169 * clock group B has 3, 4, 6 and so on.
170 *
171 * Clock group A having PLL1, PLL2, PLL3, feeding cores of any cluster
172 * depends upon the SoC architeture. Same applies to other
173 * clock groups and clusters.
174 *
York Sund7778f72012-10-08 07:44:11 +0000175 */
Timur Tabi47289422011-08-05 16:15:24 -0500176 for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
York Sunaa150bb2013-03-25 07:40:07 +0000177 int cluster = fsl_qoriq_core_to_cluster(cpu);
178 u32 c_pll_sel = (in_be32(&clk->clkcsr[cluster].clkcncsr) >> 27)
York Sund7778f72012-10-08 07:44:11 +0000179 & 0xf;
Kumar Galadccd9e32009-03-19 02:46:19 -0500180 u32 cplx_pll = core_cplx_PLL[c_pll_sel];
Prabhakar Kushwaha7e8382f2013-09-03 11:20:15 +0530181 cplx_pll += cc_group[cluster] - 1;
Prabhakar Kushwahad1698082013-08-16 14:52:26 +0530182 sys_info->freq_processor[cpu] =
Prabhakar Kushwaha7e8382f2013-09-03 11:20:15 +0530183 freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
Kumar Galadccd9e32009-03-19 02:46:19 -0500184 }
Shaveta Leekhadbf0bc82015-01-19 12:46:54 +0530185
186#ifdef CONFIG_HETROGENOUS_CLUSTERS
187 for_each_cpu(i, dsp_cpu, cpu_num_dspcores(), cpu_dsp_mask()) {
188 int dsp_cluster = fsl_qoriq_dsp_core_to_cluster(dsp_cpu);
189 u32 c_pll_sel = (in_be32
190 (&clk->clkcsr[dsp_cluster].clkcncsr) >> 27)
191 & 0xf;
192 u32 cplx_pll = core_cplx_PLL[c_pll_sel];
193 cplx_pll += cc_group[dsp_cluster] - 1;
194 sys_info->freq_processor_dsp[dsp_cpu] =
195 freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
196 }
197#endif
198
York Sunfda566d2016-11-18 11:56:57 -0800199#if defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420) || \
York Sune20c6852016-11-21 12:54:19 -0800200 defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081)
Sandeep Singhf7dfe252013-03-25 07:33:09 +0000201#define FM1_CLK_SEL 0xe0000000
202#define FM1_CLK_SHIFT 29
York Sun7d29dd62016-11-18 13:01:34 -0800203#elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023)
Shengzhou Liue6fb7702014-11-24 17:11:54 +0800204#define FM1_CLK_SEL 0x00000007
205#define FM1_CLK_SHIFT 0
Sandeep Singhf7dfe252013-03-25 07:33:09 +0000206#else
York Sund7778f72012-10-08 07:44:11 +0000207#define PME_CLK_SEL 0xe0000000
208#define PME_CLK_SHIFT 29
209#define FM1_CLK_SEL 0x1c000000
210#define FM1_CLK_SHIFT 26
Sandeep Singhf7dfe252013-03-25 07:33:09 +0000211#endif
Prabhakar Kushwaha7e8382f2013-09-03 11:20:15 +0530212#if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV)
York Sun7d29dd62016-11-18 13:01:34 -0800213#if defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023)
Shengzhou Liue6fb7702014-11-24 17:11:54 +0800214 rcw_tmp = in_be32(&gur->rcwsr[15]) - 4;
215#else
York Sund7778f72012-10-08 07:44:11 +0000216 rcw_tmp = in_be32(&gur->rcwsr[7]);
Prabhakar Kushwaha7e8382f2013-09-03 11:20:15 +0530217#endif
Shengzhou Liue6fb7702014-11-24 17:11:54 +0800218#endif
York Sund7778f72012-10-08 07:44:11 +0000219
220#ifdef CONFIG_SYS_DPAA_PME
Prabhakar Kushwaha7e8382f2013-09-03 11:20:15 +0530221#ifndef CONFIG_PME_PLAT_CLK_DIV
York Sund7778f72012-10-08 07:44:11 +0000222 switch ((rcw_tmp & PME_CLK_SEL) >> PME_CLK_SHIFT) {
223 case 1:
Prabhakar Kushwaha7e8382f2013-09-03 11:20:15 +0530224 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK];
York Sund7778f72012-10-08 07:44:11 +0000225 break;
226 case 2:
Prabhakar Kushwaha7e8382f2013-09-03 11:20:15 +0530227 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 2;
York Sund7778f72012-10-08 07:44:11 +0000228 break;
229 case 3:
Prabhakar Kushwaha7e8382f2013-09-03 11:20:15 +0530230 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 3;
York Sund7778f72012-10-08 07:44:11 +0000231 break;
232 case 4:
Prabhakar Kushwaha7e8382f2013-09-03 11:20:15 +0530233 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 4;
York Sund7778f72012-10-08 07:44:11 +0000234 break;
235 case 6:
Prabhakar Kushwaha7e8382f2013-09-03 11:20:15 +0530236 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 2;
York Sund7778f72012-10-08 07:44:11 +0000237 break;
238 case 7:
Prabhakar Kushwaha7e8382f2013-09-03 11:20:15 +0530239 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 3;
York Sund7778f72012-10-08 07:44:11 +0000240 break;
241 default:
242 printf("Error: Unknown PME clock select!\n");
243 case 0:
Prabhakar Kushwahad1698082013-08-16 14:52:26 +0530244 sys_info->freq_pme = sys_info->freq_systembus / 2;
York Sund7778f72012-10-08 07:44:11 +0000245 break;
246
247 }
Prabhakar Kushwaha7e8382f2013-09-03 11:20:15 +0530248#else
249 sys_info->freq_pme = sys_info->freq_systembus / CONFIG_SYS_PME_CLK;
250
251#endif
York Sund7778f72012-10-08 07:44:11 +0000252#endif
253
Haiying Wang09d0aa92012-10-11 07:13:39 +0000254#ifdef CONFIG_SYS_DPAA_QBMAN
Shengzhou Liue6fb7702014-11-24 17:11:54 +0800255#ifndef CONFIG_QBMAN_CLK_DIV
256#define CONFIG_QBMAN_CLK_DIV 2
257#endif
258 sys_info->freq_qman = sys_info->freq_systembus / CONFIG_QBMAN_CLK_DIV;
Haiying Wang09d0aa92012-10-11 07:13:39 +0000259#endif
260
Shaveta Leekhadbf0bc82015-01-19 12:46:54 +0530261#if defined(CONFIG_SYS_MAPLE)
262#define CPRI_CLK_SEL 0x1C000000
263#define CPRI_CLK_SHIFT 26
264#define CPRI_ALT_CLK_SEL 0x00007000
265#define CPRI_ALT_CLK_SHIFT 12
266
267 rcw_tmp1 = in_be32(&gur->rcwsr[7]); /* Reading RCW bits: 224-255*/
268 rcw_tmp2 = in_be32(&gur->rcwsr[15]); /* Reading RCW bits: 480-511*/
269 /* For MAPLE and CPRI frequency */
270 switch ((rcw_tmp1 & CPRI_CLK_SEL) >> CPRI_CLK_SHIFT) {
271 case 1:
272 sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK];
273 sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK];
274 break;
275 case 2:
276 sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 2;
277 sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 2;
278 break;
279 case 3:
280 sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 3;
281 sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 3;
282 break;
283 case 4:
284 sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 4;
285 sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 4;
286 break;
287 case 5:
288 if (((rcw_tmp2 & CPRI_ALT_CLK_SEL)
289 >> CPRI_ALT_CLK_SHIFT) == 6) {
290 sys_info->freq_maple =
291 freq_c_pll[CONFIG_SYS_CPRI_CLK - 2] / 2;
292 sys_info->freq_cpri =
293 freq_c_pll[CONFIG_SYS_CPRI_CLK - 2] / 2;
294 }
295 if (((rcw_tmp2 & CPRI_ALT_CLK_SEL)
296 >> CPRI_ALT_CLK_SHIFT) == 7) {
297 sys_info->freq_maple =
298 freq_c_pll[CONFIG_SYS_CPRI_CLK - 2] / 3;
299 sys_info->freq_cpri =
300 freq_c_pll[CONFIG_SYS_CPRI_CLK - 2] / 3;
301 }
302 break;
303 case 6:
304 sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK + 1] / 2;
305 sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK + 1] / 2;
306 break;
307 case 7:
308 sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK + 1] / 3;
309 sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK + 1] / 3;
310 break;
311 default:
312 printf("Error: Unknown MAPLE/CPRI clock select!\n");
313 }
314
315 /* For MAPLE ULB and eTVPE frequencies */
316#define ULB_CLK_SEL 0x00000038
317#define ULB_CLK_SHIFT 3
318#define ETVPE_CLK_SEL 0x00000007
319#define ETVPE_CLK_SHIFT 0
320
321 switch ((rcw_tmp2 & ULB_CLK_SEL) >> ULB_CLK_SHIFT) {
322 case 1:
323 sys_info->freq_maple_ulb = freq_c_pll[CONFIG_SYS_ULB_CLK];
324 break;
325 case 2:
326 sys_info->freq_maple_ulb = freq_c_pll[CONFIG_SYS_ULB_CLK] / 2;
327 break;
328 case 3:
329 sys_info->freq_maple_ulb = freq_c_pll[CONFIG_SYS_ULB_CLK] / 3;
330 break;
331 case 4:
332 sys_info->freq_maple_ulb = freq_c_pll[CONFIG_SYS_ULB_CLK] / 4;
333 break;
334 case 5:
335 sys_info->freq_maple_ulb = sys_info->freq_systembus;
336 break;
337 case 6:
338 sys_info->freq_maple_ulb =
339 freq_c_pll[CONFIG_SYS_ULB_CLK - 1] / 2;
340 break;
341 case 7:
342 sys_info->freq_maple_ulb =
343 freq_c_pll[CONFIG_SYS_ULB_CLK - 1] / 3;
344 break;
345 default:
346 printf("Error: Unknown MAPLE ULB clock select!\n");
347 }
348
349 switch ((rcw_tmp2 & ETVPE_CLK_SEL) >> ETVPE_CLK_SHIFT) {
350 case 1:
351 sys_info->freq_maple_etvpe = freq_c_pll[CONFIG_SYS_ETVPE_CLK];
352 break;
353 case 2:
354 sys_info->freq_maple_etvpe =
355 freq_c_pll[CONFIG_SYS_ETVPE_CLK] / 2;
356 break;
357 case 3:
358 sys_info->freq_maple_etvpe =
359 freq_c_pll[CONFIG_SYS_ETVPE_CLK] / 3;
360 break;
361 case 4:
362 sys_info->freq_maple_etvpe =
363 freq_c_pll[CONFIG_SYS_ETVPE_CLK] / 4;
364 break;
365 case 5:
366 sys_info->freq_maple_etvpe = sys_info->freq_systembus;
367 break;
368 case 6:
369 sys_info->freq_maple_etvpe =
370 freq_c_pll[CONFIG_SYS_ETVPE_CLK - 1] / 2;
371 break;
372 case 7:
373 sys_info->freq_maple_etvpe =
374 freq_c_pll[CONFIG_SYS_ETVPE_CLK - 1] / 3;
375 break;
376 default:
377 printf("Error: Unknown MAPLE eTVPE clock select!\n");
378 }
379
380#endif
381
York Sund7778f72012-10-08 07:44:11 +0000382#ifdef CONFIG_SYS_DPAA_FMAN
Prabhakar Kushwaha7e8382f2013-09-03 11:20:15 +0530383#ifndef CONFIG_FM_PLAT_CLK_DIV
York Sund7778f72012-10-08 07:44:11 +0000384 switch ((rcw_tmp & FM1_CLK_SEL) >> FM1_CLK_SHIFT) {
385 case 1:
Prabhakar Kushwaha7e8382f2013-09-03 11:20:15 +0530386 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK];
York Sund7778f72012-10-08 07:44:11 +0000387 break;
388 case 2:
Prabhakar Kushwaha7e8382f2013-09-03 11:20:15 +0530389 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 2;
York Sund7778f72012-10-08 07:44:11 +0000390 break;
391 case 3:
Prabhakar Kushwaha7e8382f2013-09-03 11:20:15 +0530392 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 3;
York Sund7778f72012-10-08 07:44:11 +0000393 break;
394 case 4:
Prabhakar Kushwaha7e8382f2013-09-03 11:20:15 +0530395 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 4;
York Sund7778f72012-10-08 07:44:11 +0000396 break;
Sandeep Singhf7dfe252013-03-25 07:33:09 +0000397 case 5:
Prabhakar Kushwahad1698082013-08-16 14:52:26 +0530398 sys_info->freq_fman[0] = sys_info->freq_systembus;
Sandeep Singhf7dfe252013-03-25 07:33:09 +0000399 break;
York Sund7778f72012-10-08 07:44:11 +0000400 case 6:
Prabhakar Kushwaha7e8382f2013-09-03 11:20:15 +0530401 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 2;
York Sund7778f72012-10-08 07:44:11 +0000402 break;
403 case 7:
Prabhakar Kushwaha7e8382f2013-09-03 11:20:15 +0530404 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 3;
York Sund7778f72012-10-08 07:44:11 +0000405 break;
406 default:
407 printf("Error: Unknown FMan1 clock select!\n");
408 case 0:
Prabhakar Kushwahad1698082013-08-16 14:52:26 +0530409 sys_info->freq_fman[0] = sys_info->freq_systembus / 2;
York Sund7778f72012-10-08 07:44:11 +0000410 break;
411 }
412#if (CONFIG_SYS_NUM_FMAN) == 2
Prabhakar Kushwaha7e8382f2013-09-03 11:20:15 +0530413#ifdef CONFIG_SYS_FM2_CLK
York Sund7778f72012-10-08 07:44:11 +0000414#define FM2_CLK_SEL 0x00000038
415#define FM2_CLK_SHIFT 3
416 rcw_tmp = in_be32(&gur->rcwsr[15]);
417 switch ((rcw_tmp & FM2_CLK_SEL) >> FM2_CLK_SHIFT) {
418 case 1:
Prabhakar Kushwaha7e8382f2013-09-03 11:20:15 +0530419 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1];
York Sund7778f72012-10-08 07:44:11 +0000420 break;
421 case 2:
Prabhakar Kushwaha7e8382f2013-09-03 11:20:15 +0530422 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 2;
York Sund7778f72012-10-08 07:44:11 +0000423 break;
424 case 3:
Prabhakar Kushwaha7e8382f2013-09-03 11:20:15 +0530425 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 3;
York Sund7778f72012-10-08 07:44:11 +0000426 break;
427 case 4:
Prabhakar Kushwaha7e8382f2013-09-03 11:20:15 +0530428 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 4;
York Sund7778f72012-10-08 07:44:11 +0000429 break;
Shaohui Xie45359a32013-11-28 13:52:51 +0800430 case 5:
431 sys_info->freq_fman[1] = sys_info->freq_systembus;
432 break;
York Sund7778f72012-10-08 07:44:11 +0000433 case 6:
Prabhakar Kushwaha7e8382f2013-09-03 11:20:15 +0530434 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 2;
York Sund7778f72012-10-08 07:44:11 +0000435 break;
436 case 7:
Prabhakar Kushwaha7e8382f2013-09-03 11:20:15 +0530437 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 3;
York Sund7778f72012-10-08 07:44:11 +0000438 break;
439 default:
440 printf("Error: Unknown FMan2 clock select!\n");
441 case 0:
Prabhakar Kushwahad1698082013-08-16 14:52:26 +0530442 sys_info->freq_fman[1] = sys_info->freq_systembus / 2;
York Sund7778f72012-10-08 07:44:11 +0000443 break;
444 }
Prabhakar Kushwaha7e8382f2013-09-03 11:20:15 +0530445#endif
York Sund7778f72012-10-08 07:44:11 +0000446#endif /* CONFIG_SYS_NUM_FMAN == 2 */
Prabhakar Kushwaha7e8382f2013-09-03 11:20:15 +0530447#else
448 sys_info->freq_fman[0] = sys_info->freq_systembus / CONFIG_SYS_FM1_CLK;
449#endif
450#endif
Kumar Galadccd9e32009-03-19 02:46:19 -0500451
Yangbo Lu163beec2015-04-22 13:57:40 +0800452#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
York Sune20c6852016-11-21 12:54:19 -0800453#if defined(CONFIG_ARCH_T2080)
Yangbo Lu163beec2015-04-22 13:57:40 +0800454#define ESDHC_CLK_SEL 0x00000007
455#define ESDHC_CLK_SHIFT 0
456#define ESDHC_CLK_RCWSR 15
457#else /* Support T1040 T1024 by now */
458#define ESDHC_CLK_SEL 0xe0000000
459#define ESDHC_CLK_SHIFT 29
460#define ESDHC_CLK_RCWSR 7
461#endif
462 rcw_tmp = in_be32(&gur->rcwsr[ESDHC_CLK_RCWSR]);
463 switch ((rcw_tmp & ESDHC_CLK_SEL) >> ESDHC_CLK_SHIFT) {
464 case 1:
465 sys_info->freq_sdhc = freq_c_pll[CONFIG_SYS_SDHC_CLK];
466 break;
467 case 2:
468 sys_info->freq_sdhc = freq_c_pll[CONFIG_SYS_SDHC_CLK] / 2;
469 break;
470 case 3:
471 sys_info->freq_sdhc = freq_c_pll[CONFIG_SYS_SDHC_CLK] / 3;
472 break;
473#if defined(CONFIG_SYS_SDHC_CLK_2_PLL)
474 case 4:
475 sys_info->freq_sdhc = freq_c_pll[CONFIG_SYS_SDHC_CLK] / 4;
476 break;
York Sune20c6852016-11-21 12:54:19 -0800477#if defined(CONFIG_ARCH_T2080)
Yangbo Lu163beec2015-04-22 13:57:40 +0800478 case 5:
479 sys_info->freq_sdhc = freq_c_pll[1 - CONFIG_SYS_SDHC_CLK];
480 break;
481#endif
482 case 6:
483 sys_info->freq_sdhc = freq_c_pll[1 - CONFIG_SYS_SDHC_CLK] / 2;
484 break;
485 case 7:
486 sys_info->freq_sdhc = freq_c_pll[1 - CONFIG_SYS_SDHC_CLK] / 3;
487 break;
488#endif
489 default:
490 sys_info->freq_sdhc = 0;
491 printf("Error: Unknown SDHC peripheral clock select!\n");
492 }
493#endif
York Sund7778f72012-10-08 07:44:11 +0000494#else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
495
496 for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
York Sunaa150bb2013-03-25 07:40:07 +0000497 u32 c_pll_sel = (in_be32(&clk->clkcsr[cpu].clkcncsr) >> 27)
498 & 0xf;
York Sund7778f72012-10-08 07:44:11 +0000499 u32 cplx_pll = core_cplx_PLL[c_pll_sel];
500
Prabhakar Kushwahad1698082013-08-16 14:52:26 +0530501 sys_info->freq_processor[cpu] =
Prabhakar Kushwaha7e8382f2013-09-03 11:20:15 +0530502 freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
York Sund7778f72012-10-08 07:44:11 +0000503 }
Kumar Galadccd9e32009-03-19 02:46:19 -0500504#define PME_CLK_SEL 0x80000000
505#define FM1_CLK_SEL 0x40000000
506#define FM2_CLK_SEL 0x20000000
Kumar Gala3842bb52011-02-16 02:03:29 -0600507#define HWA_ASYNC_DIV 0x04000000
508#if (CONFIG_SYS_FSL_NUM_CC_PLLS == 2)
509#define HWA_CC_PLL 1
Timur Tabid5e13882012-10-05 11:09:19 +0000510#elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 3)
511#define HWA_CC_PLL 2
Kumar Gala3842bb52011-02-16 02:03:29 -0600512#elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 4)
Wolfgang Denk80f70212011-05-19 22:21:41 +0200513#define HWA_CC_PLL 2
Kumar Gala3842bb52011-02-16 02:03:29 -0600514#else
515#error CONFIG_SYS_FSL_NUM_CC_PLLS not set or unknown case
516#endif
Kumar Galadccd9e32009-03-19 02:46:19 -0500517 rcw_tmp = in_be32(&gur->rcwsr[7]);
518
519#ifdef CONFIG_SYS_DPAA_PME
Kumar Gala3842bb52011-02-16 02:03:29 -0600520 if (rcw_tmp & PME_CLK_SEL) {
521 if (rcw_tmp & HWA_ASYNC_DIV)
Prabhakar Kushwaha7e8382f2013-09-03 11:20:15 +0530522 sys_info->freq_pme = freq_c_pll[HWA_CC_PLL] / 4;
Kumar Gala3842bb52011-02-16 02:03:29 -0600523 else
Prabhakar Kushwaha7e8382f2013-09-03 11:20:15 +0530524 sys_info->freq_pme = freq_c_pll[HWA_CC_PLL] / 2;
Kumar Gala3842bb52011-02-16 02:03:29 -0600525 } else {
Prabhakar Kushwahad1698082013-08-16 14:52:26 +0530526 sys_info->freq_pme = sys_info->freq_systembus / 2;
Kumar Gala3842bb52011-02-16 02:03:29 -0600527 }
Kumar Galadccd9e32009-03-19 02:46:19 -0500528#endif
529
530#ifdef CONFIG_SYS_DPAA_FMAN
Kumar Gala3842bb52011-02-16 02:03:29 -0600531 if (rcw_tmp & FM1_CLK_SEL) {
532 if (rcw_tmp & HWA_ASYNC_DIV)
Prabhakar Kushwaha7e8382f2013-09-03 11:20:15 +0530533 sys_info->freq_fman[0] = freq_c_pll[HWA_CC_PLL] / 4;
Kumar Gala3842bb52011-02-16 02:03:29 -0600534 else
Prabhakar Kushwaha7e8382f2013-09-03 11:20:15 +0530535 sys_info->freq_fman[0] = freq_c_pll[HWA_CC_PLL] / 2;
Kumar Gala3842bb52011-02-16 02:03:29 -0600536 } else {
Prabhakar Kushwahad1698082013-08-16 14:52:26 +0530537 sys_info->freq_fman[0] = sys_info->freq_systembus / 2;
Kumar Gala3842bb52011-02-16 02:03:29 -0600538 }
Kumar Galadccd9e32009-03-19 02:46:19 -0500539#if (CONFIG_SYS_NUM_FMAN) == 2
Kumar Gala3842bb52011-02-16 02:03:29 -0600540 if (rcw_tmp & FM2_CLK_SEL) {
541 if (rcw_tmp & HWA_ASYNC_DIV)
Prabhakar Kushwaha7e8382f2013-09-03 11:20:15 +0530542 sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 4;
Kumar Gala3842bb52011-02-16 02:03:29 -0600543 else
Prabhakar Kushwaha7e8382f2013-09-03 11:20:15 +0530544 sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 2;
Kumar Gala3842bb52011-02-16 02:03:29 -0600545 } else {
Prabhakar Kushwahad1698082013-08-16 14:52:26 +0530546 sys_info->freq_fman[1] = sys_info->freq_systembus / 2;
Kumar Gala3842bb52011-02-16 02:03:29 -0600547 }
Kumar Galadccd9e32009-03-19 02:46:19 -0500548#endif
549#endif
550
Shaohui Xie835c9ad2013-03-25 07:33:25 +0000551#ifdef CONFIG_SYS_DPAA_QBMAN
Prabhakar Kushwahad1698082013-08-16 14:52:26 +0530552 sys_info->freq_qman = sys_info->freq_systembus / 2;
Shaohui Xie835c9ad2013-03-25 07:33:25 +0000553#endif
554
York Sund7778f72012-10-08 07:44:11 +0000555#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
556
Zhao Qiangb818ba22014-03-21 16:21:45 +0800557#ifdef CONFIG_U_QE
558 sys_info->freq_qe = sys_info->freq_systembus / 2;
559#endif
560
York Sund7778f72012-10-08 07:44:11 +0000561#else /* CONFIG_FSL_CORENET */
Prabhakar Kushwahad1698082013-08-16 14:52:26 +0530562 uint plat_ratio, e500_ratio, half_freq_systembus;
Haiying Wangbb8aea72009-01-15 11:58:35 -0500563 int i;
Haiying Wang61414682009-05-20 12:30:29 -0400564#ifdef CONFIG_QE
Haiying Wang8cb2af72011-02-11 01:25:30 -0600565 __maybe_unused u32 qe_ratio;
Haiying Wang61414682009-05-20 12:30:29 -0400566#endif
wdenk9c53f402003-10-15 23:53:47 +0000567
568 plat_ratio = (gur->porpllsr) & 0x0000003e;
569 plat_ratio >>= 1;
Prabhakar Kushwahad1698082013-08-16 14:52:26 +0530570 sys_info->freq_systembus = plat_ratio * CONFIG_SYS_CLK_FREQ;
Andy Fleming6d972762007-04-23 02:37:47 -0500571
572 /* Divide before multiply to avoid integer
573 * overflow for processor speeds above 2GHz */
Prabhakar Kushwahad1698082013-08-16 14:52:26 +0530574 half_freq_systembus = sys_info->freq_systembus/2;
Poonam Aggrwal4baef822009-07-31 12:08:14 +0530575 for (i = 0; i < cpu_numcores(); i++) {
Haiying Wangbb8aea72009-01-15 11:58:35 -0500576 e500_ratio = ((gur->porpllsr) >> (i * 8 + 16)) & 0x3f;
Prabhakar Kushwahad1698082013-08-16 14:52:26 +0530577 sys_info->freq_processor[i] = e500_ratio * half_freq_systembus;
Haiying Wangbb8aea72009-01-15 11:58:35 -0500578 }
James Yangd1d51ad2008-02-08 18:05:08 -0600579
Prabhakar Kushwahad1698082013-08-16 14:52:26 +0530580 /* Note: freq_ddrbus is the MCLK frequency, not the data rate. */
581 sys_info->freq_ddrbus = sys_info->freq_systembus;
Kumar Gala07db1702007-12-07 04:59:26 -0600582
583#ifdef CONFIG_DDR_CLK_FREQ
584 {
Jason Jinbfcd6c32008-09-27 14:40:57 +0800585 u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
586 >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
Kumar Gala07db1702007-12-07 04:59:26 -0600587 if (ddr_ratio != 0x7)
Prabhakar Kushwahad1698082013-08-16 14:52:26 +0530588 sys_info->freq_ddrbus = ddr_ratio * CONFIG_DDR_CLK_FREQ;
Kumar Gala07db1702007-12-07 04:59:26 -0600589 }
590#endif
Trent Piepho0b691fc2008-12-03 15:16:37 -0800591
Haiying Wang61414682009-05-20 12:30:29 -0400592#ifdef CONFIG_QE
York Sun0f577972016-11-18 11:05:38 -0800593#if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025)
Prabhakar Kushwahad1698082013-08-16 14:52:26 +0530594 sys_info->freq_qe = sys_info->freq_systembus;
Haiying Wang8cb2af72011-02-11 01:25:30 -0600595#else
Haiying Wang61414682009-05-20 12:30:29 -0400596 qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO)
597 >> MPC85xx_PORPLLSR_QE_RATIO_SHIFT;
Prabhakar Kushwahad1698082013-08-16 14:52:26 +0530598 sys_info->freq_qe = qe_ratio * CONFIG_SYS_CLK_FREQ;
Haiying Wang61414682009-05-20 12:30:29 -0400599#endif
Haiying Wang8cb2af72011-02-11 01:25:30 -0600600#endif
Haiying Wang325a12f2011-01-20 22:26:31 +0000601
602#ifdef CONFIG_SYS_DPAA_FMAN
Prabhakar Kushwahad1698082013-08-16 14:52:26 +0530603 sys_info->freq_fman[0] = sys_info->freq_systembus;
Haiying Wang325a12f2011-01-20 22:26:31 +0000604#endif
605
606#endif /* CONFIG_FSL_CORENET */
Haiying Wang61414682009-05-20 12:30:29 -0400607
Dipen Dudhat5d51bf92011-01-19 12:46:27 +0530608#if defined(CONFIG_FSL_LBC)
Prabhakar Kushwahabedc5622017-02-02 15:02:00 +0530609 sys_info->freq_localbus = sys_info->freq_systembus /
610 CONFIG_SYS_FSL_LBC_CLK_DIV;
Dipen Dudhat5d51bf92011-01-19 12:46:27 +0530611#endif
Kumar Gala17ec6fa2012-10-08 07:44:06 +0000612
613#if defined(CONFIG_FSL_IFC)
Prabhakar Kushwaha3c48f582017-02-02 15:01:26 +0530614 sys_info->freq_localbus = sys_info->freq_systembus /
615 CONFIG_SYS_FSL_IFC_CLK_DIV;
Kumar Gala17ec6fa2012-10-08 07:44:06 +0000616#endif
wdenk9c53f402003-10-15 23:53:47 +0000617}
618
Andy Fleming6d972762007-04-23 02:37:47 -0500619
wdenk9c53f402003-10-15 23:53:47 +0000620int get_clocks (void)
621{
wdenk9c53f402003-10-15 23:53:47 +0000622 sys_info_t sys_info;
York Sun5ac012a2016-11-15 13:57:15 -0800623#ifdef CONFIG_ARCH_MPC8544
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200624 volatile ccsr_gur_t *gur = (void *) CONFIG_SYS_MPC85xx_GUTS_ADDR;
Timur Tabi44befe02008-04-04 11:15:58 -0500625#endif
Jon Loeligerf5ad3782005-07-23 10:37:35 -0500626#if defined(CONFIG_CPM2)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200627 volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
wdenk9c53f402003-10-15 23:53:47 +0000628 uint sccr, dfbrg;
629
630 /* set VCO = 4 * BRG */
Kumar Galacd113a02007-11-28 00:36:33 -0600631 cpm->im_cpm_intctl.sccr &= 0xfffffffc;
632 sccr = cpm->im_cpm_intctl.sccr;
wdenk9c53f402003-10-15 23:53:47 +0000633 dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT;
634#endif
635 get_sys_info (&sys_info);
Prabhakar Kushwahad1698082013-08-16 14:52:26 +0530636 gd->cpu_clk = sys_info.freq_processor[0];
637 gd->bus_clk = sys_info.freq_systembus;
638 gd->mem_clk = sys_info.freq_ddrbus;
639 gd->arch.lbc_clk = sys_info.freq_localbus;
Timur Tabi44befe02008-04-04 11:15:58 -0500640
Haiying Wang61414682009-05-20 12:30:29 -0400641#ifdef CONFIG_QE
Prabhakar Kushwahad1698082013-08-16 14:52:26 +0530642 gd->arch.qe_clk = sys_info.freq_qe;
Simon Glass8518b172012-12-13 20:48:50 +0000643 gd->arch.brg_clk = gd->arch.qe_clk / 2;
Haiying Wang61414682009-05-20 12:30:29 -0400644#endif
Timur Tabi44befe02008-04-04 11:15:58 -0500645 /*
646 * The base clock for I2C depends on the actual SOC. Unfortunately,
647 * there is no pattern that can be used to determine the frequency, so
648 * the only choice is to look up the actual SOC number and use the value
649 * for that SOC. This information is taken from application note
650 * AN2919.
651 */
York Sunbf820c02016-11-16 11:18:31 -0800652#if defined(CONFIG_ARCH_MPC8540) || defined(CONFIG_ARCH_MPC8541) || \
York Sunb4046f42016-11-16 11:26:45 -0800653 defined(CONFIG_ARCH_MPC8560) || defined(CONFIG_ARCH_MPC8555) || \
York Sun08672a52016-11-16 15:23:52 -0800654 defined(CONFIG_ARCH_P1022)
Prabhakar Kushwahad1698082013-08-16 14:52:26 +0530655 gd->arch.i2c1_clk = sys_info.freq_systembus;
York Sun5ac012a2016-11-15 13:57:15 -0800656#elif defined(CONFIG_ARCH_MPC8544)
Timur Tabi44befe02008-04-04 11:15:58 -0500657 /*
658 * On the 8544, the I2C clock is the same as the SEC clock. This can be
659 * either CCB/2 or CCB/3, depending on the value of cfg_sec_freq. See
660 * 4.4.3.3 of the 8544 RM. Note that this might actually work for all
661 * 85xx, but only the 8544 has cfg_sec_freq, so it's unknown if the
662 * PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544.
663 */
664 if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG)
Prabhakar Kushwahad1698082013-08-16 14:52:26 +0530665 gd->arch.i2c1_clk = sys_info.freq_systembus / 3;
Kumar Gala9632f662008-10-16 21:58:49 -0500666 else
Prabhakar Kushwahad1698082013-08-16 14:52:26 +0530667 gd->arch.i2c1_clk = sys_info.freq_systembus / 2;
Timur Tabi44befe02008-04-04 11:15:58 -0500668#else
669 /* Most 85xx SOCs use CCB/2, so this is the default behavior. */
Prabhakar Kushwahad1698082013-08-16 14:52:26 +0530670 gd->arch.i2c1_clk = sys_info.freq_systembus / 2;
Timur Tabi44befe02008-04-04 11:15:58 -0500671#endif
Simon Glassc2baaec2012-12-13 20:48:49 +0000672 gd->arch.i2c2_clk = gd->arch.i2c1_clk;
Timur Tabic1499f482008-01-09 14:35:26 -0600673
Dipen Dudhat9af188d2009-09-01 17:27:00 +0530674#if defined(CONFIG_FSL_ESDHC)
Yangbo Lu163beec2015-04-22 13:57:40 +0800675#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
676 gd->arch.sdhc_clk = sys_info.freq_sdhc / 2;
677#else
York Sun5f163882016-11-16 16:02:09 -0800678#if defined(CONFIG_ARCH_MPC8569) || defined(CONFIG_ARCH_P1010)
Simon Glass9e247d12012-12-13 20:49:05 +0000679 gd->arch.sdhc_clk = gd->bus_clk;
Anton Vorontsovda225942009-10-15 17:47:06 +0400680#else
Simon Glass9e247d12012-12-13 20:49:05 +0000681 gd->arch.sdhc_clk = gd->bus_clk / 2;
Kumar Galacd777282008-08-12 11:14:19 -0500682#endif
Yangbo Lu163beec2015-04-22 13:57:40 +0800683#endif
Anton Vorontsovda225942009-10-15 17:47:06 +0400684#endif /* defined(CONFIG_FSL_ESDHC) */
Kumar Galacd777282008-08-12 11:14:19 -0500685
Jon Loeligerf5ad3782005-07-23 10:37:35 -0500686#if defined(CONFIG_CPM2)
Prabhakar Kushwahad1698082013-08-16 14:52:26 +0530687 gd->arch.vco_out = 2*sys_info.freq_systembus;
Simon Glass44ea8512012-12-13 20:48:46 +0000688 gd->arch.cpm_clk = gd->arch.vco_out / 2;
689 gd->arch.scc_clk = gd->arch.vco_out / 4;
690 gd->arch.brg_clk = gd->arch.vco_out / (1 << (2 * (dfbrg + 1)));
wdenk9c53f402003-10-15 23:53:47 +0000691#endif
692
693 if(gd->cpu_clk != 0) return (0);
694 else return (1);
695}
696
697
698/********************************************
699 * get_bus_freq
700 * return system bus freq in Hz
701 *********************************************/
702ulong get_bus_freq (ulong dummy)
703{
James Yangd1d51ad2008-02-08 18:05:08 -0600704 return gd->bus_clk;
wdenk9c53f402003-10-15 23:53:47 +0000705}
Kumar Gala07db1702007-12-07 04:59:26 -0600706
707/********************************************
708 * get_ddr_freq
709 * return ddr bus freq in Hz
710 *********************************************/
711ulong get_ddr_freq (ulong dummy)
712{
James Yangd1d51ad2008-02-08 18:05:08 -0600713 return gd->mem_clk;
Kumar Gala07db1702007-12-07 04:59:26 -0600714}