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git01.mediatek.com / filogic / uboot / 338baa3e94f1f668793b61765f950ddf14f66d93 / . / arch / arm / include / asm / arch-mx25 / iomux-mx25.h
blob: 1ce7a8586f83fe2c46401a52567f6104f4371db3 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]2/*
3 * (C) Copyright 2013 ADVANSEE
4 * Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
5 *
6 * Based on mainline Linux i.MX iomux-mx25.h file:
7 * Copyright (C) 2009 by Lothar Wassmann <LW@KARO-electronics.de>
8 *
9 * Based on Linux arch/arm/mach-mx25/mx25_pins.h:
10 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
11 * and Linux arch/arm/plat-mxc/include/mach/iomux-mx35.h:
12 * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH <armlinux@phytec.de>
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]13 */
14
15#ifndef __IOMUX_MX25_H__
16#define __IOMUX_MX25_H__
17
Stefano Babic33731bc2017-06-29 10:16:06 +0200[diff] [blame]18#include <asm/mach-imx/iomux-v3.h>
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]19
20/* Pad control groupings */
21#define MX25_KPP_ROW_PAD_CTRL PAD_CTL_PUS_100K_UP
22#define MX25_KPP_COL_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
23
24/*
25 * The naming convention for the pad modes is MX25_PAD_<padname>__<padmode>
26 * If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num>
27 * See also iomux-v3.h
28 */
29
30/* PAD MUX ALT INPSE PATH PADCTRL */
31enum {
32 MX25_PAD_A10__A10 = IOMUX_PAD(0x000, 0x008, 0x00, 0, 0, NO_PAD_CTRL),
33 MX25_PAD_A10__GPIO_4_0 = IOMUX_PAD(0x000, 0x008, 0x05, 0, 0, NO_PAD_CTRL),
34
35 MX25_PAD_A13__A13 = IOMUX_PAD(0x22C, 0x00c, 0x00, 0, 0, NO_PAD_CTRL),
36 MX25_PAD_A13__GPIO_4_1 = IOMUX_PAD(0x22C, 0x00c, 0x05, 0, 0, NO_PAD_CTRL),
37
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]38 MX25_PAD_A14__A14 = IOMUX_PAD(0x230, 0x010, 0x00, 0, 0, NO_PAD_CTRL),
39 MX25_PAD_A14__GPIO_2_0 = IOMUX_PAD(0x230, 0x010, 0x05, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]40
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]41 MX25_PAD_A15__A15 = IOMUX_PAD(0x234, 0x014, 0x00, 0, 0, NO_PAD_CTRL),
42 MX25_PAD_A15__GPIO_2_1 = IOMUX_PAD(0x234, 0x014, 0x05, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]43
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]44 MX25_PAD_A16__A16 = IOMUX_PAD(0x000, 0x018, 0x00, 0, 0, NO_PAD_CTRL),
45 MX25_PAD_A16__GPIO_2_2 = IOMUX_PAD(0x000, 0x018, 0x05, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]46
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]47 MX25_PAD_A17__A17 = IOMUX_PAD(0x238, 0x01c, 0x00, 0, 0, NO_PAD_CTRL),
48 MX25_PAD_A17__GPIO_2_3 = IOMUX_PAD(0x238, 0x01c, 0x05, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]49
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]50 MX25_PAD_A18__A18 = IOMUX_PAD(0x23c, 0x020, 0x00, 0, 0, NO_PAD_CTRL),
51 MX25_PAD_A18__GPIO_2_4 = IOMUX_PAD(0x23c, 0x020, 0x05, 0, 0, NO_PAD_CTRL),
52 MX25_PAD_A18__FEC_COL = IOMUX_PAD(0x23c, 0x020, 0x07, 0x504, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]53
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]54 MX25_PAD_A19__A19 = IOMUX_PAD(0x240, 0x024, 0x00, 0, 0, NO_PAD_CTRL),
55 MX25_PAD_A19__FEC_RX_ER = IOMUX_PAD(0x240, 0x024, 0x07, 0x518, 0, NO_PAD_CTRL),
56 MX25_PAD_A19__GPIO_2_5 = IOMUX_PAD(0x240, 0x024, 0x05, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]57
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]58 MX25_PAD_A20__A20 = IOMUX_PAD(0x244, 0x028, 0x00, 0, 0, NO_PAD_CTRL),
59 MX25_PAD_A20__GPIO_2_6 = IOMUX_PAD(0x244, 0x028, 0x05, 0, 0, NO_PAD_CTRL),
60 MX25_PAD_A20__FEC_RDATA2 = IOMUX_PAD(0x244, 0x028, 0x07, 0x50c, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]61
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]62 MX25_PAD_A21__A21 = IOMUX_PAD(0x248, 0x02c, 0x00, 0, 0, NO_PAD_CTRL),
63 MX25_PAD_A21__GPIO_2_7 = IOMUX_PAD(0x248, 0x02c, 0x05, 0, 0, NO_PAD_CTRL),
64 MX25_PAD_A21__FEC_RDATA3 = IOMUX_PAD(0x248, 0x02c, 0x07, 0x510, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]65
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]66 MX25_PAD_A22__A22 = IOMUX_PAD(0x000, 0x030, 0x00, 0, 0, NO_PAD_CTRL),
67 MX25_PAD_A22__GPIO_2_8 = IOMUX_PAD(0x000, 0x030, 0x05, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]68
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]69 MX25_PAD_A23__A23 = IOMUX_PAD(0x24c, 0x034, 0x00, 0, 0, NO_PAD_CTRL),
70 MX25_PAD_A23__GPIO_2_9 = IOMUX_PAD(0x24c, 0x034, 0x05, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]71
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]72 MX25_PAD_A24__A24 = IOMUX_PAD(0x250, 0x038, 0x00, 0, 0, NO_PAD_CTRL),
73 MX25_PAD_A24__GPIO_2_10 = IOMUX_PAD(0x250, 0x038, 0x05, 0, 0, NO_PAD_CTRL),
74 MX25_PAD_A24__FEC_RX_CLK = IOMUX_PAD(0x250, 0x038, 0x07, 0x514, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]75
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]76 MX25_PAD_A25__A25 = IOMUX_PAD(0x254, 0x03c, 0x00, 0, 0, NO_PAD_CTRL),
77 MX25_PAD_A25__GPIO_2_11 = IOMUX_PAD(0x254, 0x03c, 0x05, 0, 0, NO_PAD_CTRL),
78 MX25_PAD_A25__FEC_CRS = IOMUX_PAD(0x254, 0x03c, 0x07, 0x508, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]79
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]80 MX25_PAD_EB0__EB0 = IOMUX_PAD(0x258, 0x040, 0x00, 0, 0, NO_PAD_CTRL),
81 MX25_PAD_EB0__AUD4_TXD = IOMUX_PAD(0x258, 0x040, 0x04, 0x464, 0, NO_PAD_CTRL),
82 MX25_PAD_EB0__GPIO_2_12 = IOMUX_PAD(0x258, 0x040, 0x05, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]83
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]84 MX25_PAD_EB1__EB1 = IOMUX_PAD(0x25c, 0x044, 0x00, 0, 0, NO_PAD_CTRL),
85 MX25_PAD_EB1__AUD4_RXD = IOMUX_PAD(0x25c, 0x044, 0x04, 0x460, 0, NO_PAD_CTRL),
86 MX25_PAD_EB1__GPIO_2_13 = IOMUX_PAD(0x25c, 0x044, 0x05, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]87
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]88 MX25_PAD_OE__OE = IOMUX_PAD(0x260, 0x048, 0x00, 0, 0, NO_PAD_CTRL),
89 MX25_PAD_OE__AUD4_TXC = IOMUX_PAD(0x260, 0x048, 0x04, 0, 0, NO_PAD_CTRL),
90 MX25_PAD_OE__GPIO_2_14 = IOMUX_PAD(0x260, 0x048, 0x05, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]91
92 MX25_PAD_CS0__CS0 = IOMUX_PAD(0x000, 0x04c, 0x00, 0, 0, NO_PAD_CTRL),
93 MX25_PAD_CS0__GPIO_4_2 = IOMUX_PAD(0x000, 0x04c, 0x05, 0, 0, NO_PAD_CTRL),
94
95 MX25_PAD_CS1__CS1 = IOMUX_PAD(0x000, 0x050, 0x00, 0, 0, NO_PAD_CTRL),
96 MX25_PAD_CS1__NF_CE3 = IOMUX_PAD(0x000, 0x050, 0x01, 0, 0, NO_PAD_CTRL),
97 MX25_PAD_CS1__GPIO_4_3 = IOMUX_PAD(0x000, 0x050, 0x05, 0, 0, NO_PAD_CTRL),
98
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]99 MX25_PAD_CS4__CS4 = IOMUX_PAD(0x264, 0x054, 0x00, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]100 MX25_PAD_CS4__NF_CE1 = IOMUX_PAD(0x264, 0x054, 0x01, 0, 0, NO_PAD_CTRL),
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]101 MX25_PAD_CS4__UART5_CTS = IOMUX_PAD(0x264, 0x054, 0x03, 0, 0, NO_PAD_CTRL),
102 MX25_PAD_CS4__GPIO_3_20 = IOMUX_PAD(0x264, 0x054, 0x05, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]103
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]104 MX25_PAD_CS5__CS5 = IOMUX_PAD(0x268, 0x058, 0x00, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]105 MX25_PAD_CS5__NF_CE2 = IOMUX_PAD(0x268, 0x058, 0x01, 0, 0, NO_PAD_CTRL),
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]106 MX25_PAD_CS5__UART5_RTS = IOMUX_PAD(0x268, 0x058, 0x03, 0x574, 0, NO_PAD_CTRL),
107 MX25_PAD_CS5__GPIO_3_21 = IOMUX_PAD(0x268, 0x058, 0x05, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]108
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]109 MX25_PAD_NF_CE0__NF_CE0 = IOMUX_PAD(0x26c, 0x05c, 0x00, 0, 0, NO_PAD_CTRL),
110 MX25_PAD_NF_CE0__GPIO_3_22 = IOMUX_PAD(0x26c, 0x05c, 0x05, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]111
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]112 MX25_PAD_ECB__ECB = IOMUX_PAD(0x270, 0x060, 0x00, 0, 0, NO_PAD_CTRL),
113 MX25_PAD_ECB__UART5_TXD_MUX = IOMUX_PAD(0x270, 0x060, 0x03, 0, 0, NO_PAD_CTRL),
114 MX25_PAD_ECB__GPIO_3_23 = IOMUX_PAD(0x270, 0x060, 0x05, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]115
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]116 MX25_PAD_LBA__LBA = IOMUX_PAD(0x274, 0x064, 0x00, 0, 0, NO_PAD_CTRL),
117 MX25_PAD_LBA__UART5_RXD_MUX = IOMUX_PAD(0x274, 0x064, 0x03, 0x578, 0, NO_PAD_CTRL),
118 MX25_PAD_LBA__GPIO_3_24 = IOMUX_PAD(0x274, 0x064, 0x05, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]119
120 MX25_PAD_BCLK__BCLK = IOMUX_PAD(0x000, 0x068, 0x00, 0, 0, NO_PAD_CTRL),
121 MX25_PAD_BCLK__GPIO_4_4 = IOMUX_PAD(0x000, 0x068, 0x05, 0, 0, NO_PAD_CTRL),
122
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]123 MX25_PAD_RW__RW = IOMUX_PAD(0x278, 0x06c, 0x00, 0, 0, NO_PAD_CTRL),
124 MX25_PAD_RW__AUD4_TXFS = IOMUX_PAD(0x278, 0x06c, 0x04, 0x474, 0, NO_PAD_CTRL),
125 MX25_PAD_RW__GPIO_3_25 = IOMUX_PAD(0x278, 0x06c, 0x05, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]126
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]127 MX25_PAD_NFWE_B__NFWE_B = IOMUX_PAD(0x000, 0x070, 0x00, 0, 0, NO_PAD_CTRL),
128 MX25_PAD_NFWE_B__GPIO_3_26 = IOMUX_PAD(0x000, 0x070, 0x05, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]129
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]130 MX25_PAD_NFRE_B__NFRE_B = IOMUX_PAD(0x000, 0x074, 0x00, 0, 0, NO_PAD_CTRL),
131 MX25_PAD_NFRE_B__GPIO_3_27 = IOMUX_PAD(0x000, 0x074, 0x05, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]132
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]133 MX25_PAD_NFALE__NFALE = IOMUX_PAD(0x000, 0x078, 0x00, 0, 0, NO_PAD_CTRL),
134 MX25_PAD_NFALE__GPIO_3_28 = IOMUX_PAD(0x000, 0x078, 0x05, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]135
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]136 MX25_PAD_NFCLE__NFCLE = IOMUX_PAD(0x000, 0x07c, 0x00, 0, 0, NO_PAD_CTRL),
137 MX25_PAD_NFCLE__GPIO_3_29 = IOMUX_PAD(0x000, 0x07c, 0x05, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]138
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]139 MX25_PAD_NFWP_B__NFWP_B = IOMUX_PAD(0x000, 0x080, 0x00, 0, 0, NO_PAD_CTRL),
140 MX25_PAD_NFWP_B__GPIO_3_30 = IOMUX_PAD(0x000, 0x080, 0x05, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]141
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]142 MX25_PAD_NFRB__NFRB = IOMUX_PAD(0x27c, 0x084, 0x00, 0, 0, PAD_CTL_PKE),
143 MX25_PAD_NFRB__GPIO_3_31 = IOMUX_PAD(0x27c, 0x084, 0x05, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]144
145 MX25_PAD_D15__D15 = IOMUX_PAD(0x280, 0x088, 0x00, 0, 0, NO_PAD_CTRL),
146 MX25_PAD_D15__LD16 = IOMUX_PAD(0x280, 0x088, 0x01, 0, 0, PAD_CTL_SRE_FAST),
147 MX25_PAD_D15__GPIO_4_5 = IOMUX_PAD(0x280, 0x088, 0x05, 0, 0, NO_PAD_CTRL),
148
149 MX25_PAD_D14__D14 = IOMUX_PAD(0x284, 0x08c, 0x00, 0, 0, NO_PAD_CTRL),
150 MX25_PAD_D14__LD17 = IOMUX_PAD(0x284, 0x08c, 0x01, 0, 0, PAD_CTL_SRE_FAST),
151 MX25_PAD_D14__GPIO_4_6 = IOMUX_PAD(0x284, 0x08c, 0x05, 0, 0, NO_PAD_CTRL),
152
153 MX25_PAD_D13__D13 = IOMUX_PAD(0x288, 0x090, 0x00, 0, 0, NO_PAD_CTRL),
154 MX25_PAD_D13__LD18 = IOMUX_PAD(0x288, 0x090, 0x01, 0, 0, PAD_CTL_SRE_FAST),
155 MX25_PAD_D13__GPIO_4_7 = IOMUX_PAD(0x288, 0x090, 0x05, 0, 0, NO_PAD_CTRL),
156
157 MX25_PAD_D12__D12 = IOMUX_PAD(0x28c, 0x094, 0x00, 0, 0, NO_PAD_CTRL),
158 MX25_PAD_D12__GPIO_4_8 = IOMUX_PAD(0x28c, 0x094, 0x05, 0, 0, NO_PAD_CTRL),
159
160 MX25_PAD_D11__D11 = IOMUX_PAD(0x290, 0x098, 0x00, 0, 0, NO_PAD_CTRL),
161 MX25_PAD_D11__GPIO_4_9 = IOMUX_PAD(0x290, 0x098, 0x05, 0, 0, NO_PAD_CTRL),
162
163 MX25_PAD_D10__D10 = IOMUX_PAD(0x294, 0x09c, 0x00, 0, 0, NO_PAD_CTRL),
164 MX25_PAD_D10__GPIO_4_10 = IOMUX_PAD(0x294, 0x09c, 0x05, 0, 0, NO_PAD_CTRL),
165 MX25_PAD_D10__USBOTG_OC = IOMUX_PAD(0x294, 0x09c, 0x06, 0x57c, 0, PAD_CTL_PUS_100K_UP),
166
167 MX25_PAD_D9__D9 = IOMUX_PAD(0x298, 0x0a0, 0x00, 0, 0, NO_PAD_CTRL),
168 MX25_PAD_D9__GPIO_4_11 = IOMUX_PAD(0x298, 0x0a0, 0x05, 0, 0, NO_PAD_CTRL),
169 MX25_PAD_D9__USBH2_PWR = IOMUX_PAD(0x298, 0x0a0, 0x06, 0, 0, PAD_CTL_PKE),
170
171 MX25_PAD_D8__D8 = IOMUX_PAD(0x29c, 0x0a4, 0x00, 0, 0, NO_PAD_CTRL),
172 MX25_PAD_D8__GPIO_4_12 = IOMUX_PAD(0x29c, 0x0a4, 0x05, 0, 0, NO_PAD_CTRL),
173 MX25_PAD_D8__USBH2_OC = IOMUX_PAD(0x29c, 0x0a4, 0x06, 0x580, 0, PAD_CTL_PUS_100K_UP),
174
175 MX25_PAD_D7__D7 = IOMUX_PAD(0x2a0, 0x0a8, 0x00, 0, 0, NO_PAD_CTRL),
176 MX25_PAD_D7__GPIO_4_13 = IOMUX_PAD(0x2a0, 0x0a8, 0x05, 0, 0, NO_PAD_CTRL),
177
178 MX25_PAD_D6__D6 = IOMUX_PAD(0x2a4, 0x0ac, 0x00, 0, 0, NO_PAD_CTRL),
179 MX25_PAD_D6__GPIO_4_14 = IOMUX_PAD(0x2a4, 0x0ac, 0x05, 0, 0, NO_PAD_CTRL),
180
181 MX25_PAD_D5__D5 = IOMUX_PAD(0x2a8, 0x0b0, 0x00, 0, 0, NO_PAD_CTRL),
182 MX25_PAD_D5__GPIO_4_15 = IOMUX_PAD(0x2a8, 0x0b0, 0x05, 0, 0, NO_PAD_CTRL),
183
184 MX25_PAD_D4__D4 = IOMUX_PAD(0x2ac, 0x0b4, 0x00, 0, 0, NO_PAD_CTRL),
185 MX25_PAD_D4__GPIO_4_16 = IOMUX_PAD(0x2ac, 0x0b4, 0x05, 0, 0, NO_PAD_CTRL),
186
187 MX25_PAD_D3__D3 = IOMUX_PAD(0x2b0, 0x0b8, 0x00, 0, 0, NO_PAD_CTRL),
188 MX25_PAD_D3__GPIO_4_17 = IOMUX_PAD(0x2b0, 0x0b8, 0x05, 0, 0, NO_PAD_CTRL),
189
190 MX25_PAD_D2__D2 = IOMUX_PAD(0x2b4, 0x0bc, 0x00, 0, 0, NO_PAD_CTRL),
191 MX25_PAD_D2__GPIO_4_18 = IOMUX_PAD(0x2b4, 0x0bc, 0x05, 0, 0, NO_PAD_CTRL),
192
193 MX25_PAD_D1__D1 = IOMUX_PAD(0x2b8, 0x0c0, 0x00, 0, 0, NO_PAD_CTRL),
194 MX25_PAD_D1__GPIO_4_19 = IOMUX_PAD(0x2b8, 0x0c0, 0x05, 0, 0, NO_PAD_CTRL),
195
196 MX25_PAD_D0__D0 = IOMUX_PAD(0x2bc, 0x0c4, 0x00, 0, 0, NO_PAD_CTRL),
197 MX25_PAD_D0__GPIO_4_20 = IOMUX_PAD(0x2bc, 0x0c4, 0x05, 0, 0, NO_PAD_CTRL),
198
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]199 MX25_PAD_LD0__LD0 = IOMUX_PAD(0x2c0, 0x0c8, 0x00, 0, 0, PAD_CTL_SRE_FAST),
200 MX25_PAD_LD0__CSI_D0 = IOMUX_PAD(0x2c0, 0x0c8, 0x02, 0x488, 0, NO_PAD_CTRL),
201 MX25_PAD_LD0__GPIO_2_15 = IOMUX_PAD(0x2c0, 0x0c8, 0x05, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]202
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]203 MX25_PAD_LD1__LD1 = IOMUX_PAD(0x2c4, 0x0cc, 0x00, 0, 0, PAD_CTL_SRE_FAST),
204 MX25_PAD_LD1__CSI_D1 = IOMUX_PAD(0x2c4, 0x0cc, 0x02, 0x48c, 0, NO_PAD_CTRL),
205 MX25_PAD_LD1__GPIO_2_16 = IOMUX_PAD(0x2c4, 0x0cc, 0x05, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]206
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]207 MX25_PAD_LD2__LD2 = IOMUX_PAD(0x2c8, 0x0d0, 0x00, 0, 0, PAD_CTL_SRE_FAST),
208 MX25_PAD_LD2__GPIO_2_17 = IOMUX_PAD(0x2c8, 0x0d0, 0x05, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]209
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]210 MX25_PAD_LD3__LD3 = IOMUX_PAD(0x2cc, 0x0d4, 0x00, 0, 0, PAD_CTL_SRE_FAST),
211 MX25_PAD_LD3__GPIO_2_18 = IOMUX_PAD(0x2cc, 0x0d4, 0x05, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]212
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]213 MX25_PAD_LD4__LD4 = IOMUX_PAD(0x2d0, 0x0d8, 0x00, 0, 0, PAD_CTL_SRE_FAST),
214 MX25_PAD_LD4__GPIO_2_19 = IOMUX_PAD(0x2d0, 0x0d8, 0x05, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]215
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]216 MX25_PAD_LD5__LD5 = IOMUX_PAD(0x2d4, 0x0dc, 0x00, 0, 0, PAD_CTL_SRE_FAST),
217 MX25_PAD_LD5__GPIO_1_19 = IOMUX_PAD(0x2d4, 0x0dc, 0x05, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]218
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]219 MX25_PAD_LD6__LD6 = IOMUX_PAD(0x2d8, 0x0e0, 0x00, 0, 0, PAD_CTL_SRE_FAST),
220 MX25_PAD_LD6__GPIO_1_20 = IOMUX_PAD(0x2d8, 0x0e0, 0x05, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]221
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]222 MX25_PAD_LD7__LD7 = IOMUX_PAD(0x2dc, 0x0e4, 0x00, 0, 0, PAD_CTL_SRE_FAST),
223 MX25_PAD_LD7__GPIO_1_21 = IOMUX_PAD(0x2dc, 0x0e4, 0x05, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]224
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]225 MX25_PAD_LD8__LD8 = IOMUX_PAD(0x2e0, 0x0e8, 0x00, 0, 0, PAD_CTL_SRE_FAST),
226 MX25_PAD_LD8__FEC_TX_ERR = IOMUX_PAD(0x2e0, 0x0e8, 0x05, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]227
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]228 MX25_PAD_LD9__LD9 = IOMUX_PAD(0x2e4, 0x0ec, 0x00, 0, 0, PAD_CTL_SRE_FAST),
229 MX25_PAD_LD9__FEC_COL = IOMUX_PAD(0x2e4, 0x0ec, 0x05, 0x504, 1, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]230
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]231 MX25_PAD_LD10__LD10 = IOMUX_PAD(0x2e8, 0x0f0, 0x00, 0, 0, PAD_CTL_SRE_FAST),
232 MX25_PAD_LD10__FEC_RX_ER = IOMUX_PAD(0x2e8, 0x0f0, 0x05, 0x518, 1, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]233
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]234 MX25_PAD_LD11__LD11 = IOMUX_PAD(0x2ec, 0x0f4, 0x00, 0, 0, PAD_CTL_SRE_FAST),
235 MX25_PAD_LD11__FEC_RDATA2 = IOMUX_PAD(0x2ec, 0x0f4, 0x05, 0x50c, 1, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]236
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]237 MX25_PAD_LD12__LD12 = IOMUX_PAD(0x2f0, 0x0f8, 0x00, 0, 0, PAD_CTL_SRE_FAST),
238 MX25_PAD_LD12__FEC_RDATA3 = IOMUX_PAD(0x2f0, 0x0f8, 0x05, 0x510, 1, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]239
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]240 MX25_PAD_LD13__LD13 = IOMUX_PAD(0x2f4, 0x0fc, 0x00, 0, 0, PAD_CTL_SRE_FAST),
241 MX25_PAD_LD13__FEC_TDATA2 = IOMUX_PAD(0x2f4, 0x0fc, 0x05, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]242
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]243 MX25_PAD_LD14__LD14 = IOMUX_PAD(0x2f8, 0x100, 0x00, 0, 0, PAD_CTL_SRE_FAST),
244 MX25_PAD_LD14__FEC_TDATA3 = IOMUX_PAD(0x2f8, 0x100, 0x05, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]245
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]246 MX25_PAD_LD15__LD15 = IOMUX_PAD(0x2fc, 0x104, 0x00, 0, 0, PAD_CTL_SRE_FAST),
247 MX25_PAD_LD15__FEC_RX_CLK = IOMUX_PAD(0x2fc, 0x104, 0x05, 0x514, 1, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]248
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]249 MX25_PAD_HSYNC__HSYNC = IOMUX_PAD(0x300, 0x108, 0x00, 0, 0, NO_PAD_CTRL),
250 MX25_PAD_HSYNC__GPIO_1_22 = IOMUX_PAD(0x300, 0x108, 0x05, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]251
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]252 MX25_PAD_VSYNC__VSYNC = IOMUX_PAD(0x304, 0x10c, 0x00, 0, 0, NO_PAD_CTRL),
253 MX25_PAD_VSYNC__GPIO_1_23 = IOMUX_PAD(0x304, 0x10c, 0x05, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]254
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]255 MX25_PAD_LSCLK__LSCLK = IOMUX_PAD(0x308, 0x110, 0x00, 0, 0, NO_PAD_CTRL),
256 MX25_PAD_LSCLK__GPIO_1_24 = IOMUX_PAD(0x308, 0x110, 0x05, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]257
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]258 MX25_PAD_OE_ACD__OE_ACD = IOMUX_PAD(0x30c, 0x114, 0x00, 0, 0, NO_PAD_CTRL),
259 MX25_PAD_OE_ACD__GPIO_1_25 = IOMUX_PAD(0x30c, 0x114, 0x05, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]260
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]261 MX25_PAD_CONTRAST__CONTRAST = IOMUX_PAD(0x310, 0x118, 0x00, 0, 0, NO_PAD_CTRL),
262 MX25_PAD_CONTRAST__PWM4_PWMO = IOMUX_PAD(0x310, 0x118, 0x04, 0, 0, NO_PAD_CTRL),
263 MX25_PAD_CONTRAST__FEC_CRS = IOMUX_PAD(0x310, 0x118, 0x05, 0x508, 1, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]264
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]265 MX25_PAD_PWM__PWM = IOMUX_PAD(0x314, 0x11c, 0x00, 0, 0, NO_PAD_CTRL),
266 MX25_PAD_PWM__GPIO_1_26 = IOMUX_PAD(0x314, 0x11c, 0x05, 0, 0, NO_PAD_CTRL),
267 MX25_PAD_PWM__USBH2_OC = IOMUX_PAD(0x314, 0x11c, 0x06, 0x580, 1, PAD_CTL_PUS_100K_UP),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]268
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]269 MX25_PAD_CSI_D2__CSI_D2 = IOMUX_PAD(0x318, 0x120, 0x00, 0, 0, NO_PAD_CTRL),
270 MX25_PAD_CSI_D2__UART5_RXD_MUX = IOMUX_PAD(0x318, 0x120, 0x01, 0x578, 1, NO_PAD_CTRL),
271 MX25_PAD_CSI_D2__GPIO_1_27 = IOMUX_PAD(0x318, 0x120, 0x05, 0, 0, NO_PAD_CTRL),
272 MX25_PAD_CSI_D2__CSPI3_MOSI = IOMUX_PAD(0x318, 0x120, 0x07, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]273
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]274 MX25_PAD_CSI_D3__CSI_D3 = IOMUX_PAD(0x31c, 0x124, 0x00, 0, 0, NO_PAD_CTRL),
275 MX25_PAD_CSI_D3__GPIO_1_28 = IOMUX_PAD(0x31c, 0x124, 0x05, 0, 0, NO_PAD_CTRL),
276 MX25_PAD_CSI_D3__CSPI3_MISO = IOMUX_PAD(0x31c, 0x124, 0x07, 0x4b4, 1, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]277
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]278 MX25_PAD_CSI_D4__CSI_D4 = IOMUX_PAD(0x320, 0x128, 0x00, 0, 0, NO_PAD_CTRL),
279 MX25_PAD_CSI_D4__UART5_RTS = IOMUX_PAD(0x320, 0x128, 0x01, 0x574, 1, NO_PAD_CTRL),
280 MX25_PAD_CSI_D4__GPIO_1_29 = IOMUX_PAD(0x320, 0x128, 0x05, 0, 0, NO_PAD_CTRL),
281 MX25_PAD_CSI_D4__CSPI3_SCLK = IOMUX_PAD(0x320, 0x128, 0x07, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]282
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]283 MX25_PAD_CSI_D5__CSI_D5 = IOMUX_PAD(0x324, 0x12c, 0x00, 0, 0, NO_PAD_CTRL),
284 MX25_PAD_CSI_D5__GPIO_1_30 = IOMUX_PAD(0x324, 0x12c, 0x05, 0, 0, NO_PAD_CTRL),
285 MX25_PAD_CSI_D5__CSPI3_RDY = IOMUX_PAD(0x324, 0x12c, 0x07, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]286
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]287 MX25_PAD_CSI_D6__CSI_D6 = IOMUX_PAD(0x328, 0x130, 0x00, 0, 0, NO_PAD_CTRL),
288 MX25_PAD_CSI_D6__GPIO_1_31 = IOMUX_PAD(0x328, 0x130, 0x05, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]289
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]290 MX25_PAD_CSI_D7__CSI_D7 = IOMUX_PAD(0x32c, 0x134, 0x00, 0, 0, NO_PAD_CTRL),
291 MX25_PAD_CSI_D7__GPIO_1_6 = IOMUX_PAD(0x32c, 0x134, 0x05, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]292
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]293 MX25_PAD_CSI_D8__CSI_D8 = IOMUX_PAD(0x330, 0x138, 0x00, 0, 0, NO_PAD_CTRL),
294 MX25_PAD_CSI_D8__GPIO_1_7 = IOMUX_PAD(0x330, 0x138, 0x05, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]295
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]296 MX25_PAD_CSI_D9__CSI_D9 = IOMUX_PAD(0x334, 0x13c, 0x00, 0, 0, NO_PAD_CTRL),
297 MX25_PAD_CSI_D9__GPIO_4_21 = IOMUX_PAD(0x334, 0x13c, 0x05, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]298
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]299 MX25_PAD_CSI_MCLK__CSI_MCLK = IOMUX_PAD(0x338, 0x140, 0x00, 0, 0, NO_PAD_CTRL),
300 MX25_PAD_CSI_MCLK__GPIO_1_8 = IOMUX_PAD(0x338, 0x140, 0x05, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]301
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]302 MX25_PAD_CSI_VSYNC__CSI_VSYNC = IOMUX_PAD(0x33c, 0x144, 0x00, 0, 0, NO_PAD_CTRL),
303 MX25_PAD_CSI_VSYNC__GPIO_1_9 = IOMUX_PAD(0x33c, 0x144, 0x05, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]304
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]305 MX25_PAD_CSI_HSYNC__CSI_HSYNC = IOMUX_PAD(0x340, 0x148, 0x00, 0, 0, NO_PAD_CTRL),
306 MX25_PAD_CSI_HSYNC__GPIO_1_10 = IOMUX_PAD(0x340, 0x148, 0x05, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]307
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]308 MX25_PAD_CSI_PIXCLK__CSI_PIXCLK = IOMUX_PAD(0x344, 0x14c, 0x00, 0, 0, NO_PAD_CTRL),
309 MX25_PAD_CSI_PIXCLK__GPIO_1_11 = IOMUX_PAD(0x344, 0x14c, 0x05, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]310
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]311 MX25_PAD_I2C1_CLK__I2C1_CLK = IOMUX_PAD(0x348, 0x150, 0x00, 0, 0, NO_PAD_CTRL),
312 MX25_PAD_I2C1_CLK__GPIO_1_12 = IOMUX_PAD(0x348, 0x150, 0x05, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]313
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]314 MX25_PAD_I2C1_DAT__I2C1_DAT = IOMUX_PAD(0x34c, 0x154, 0x00, 0, 0, NO_PAD_CTRL),
315 MX25_PAD_I2C1_DAT__GPIO_1_13 = IOMUX_PAD(0x34c, 0x154, 0x05, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]316
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]317 MX25_PAD_CSPI1_MOSI__CSPI1_MOSI = IOMUX_PAD(0x350, 0x158, 0x00, 0, 0, NO_PAD_CTRL),
318 MX25_PAD_CSPI1_MOSI__GPIO_1_14 = IOMUX_PAD(0x350, 0x158, 0x05, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]319
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]320 MX25_PAD_CSPI1_MISO__CSPI1_MISO = IOMUX_PAD(0x354, 0x15c, 0x00, 0, 0, NO_PAD_CTRL),
321 MX25_PAD_CSPI1_MISO__GPIO_1_15 = IOMUX_PAD(0x354, 0x15c, 0x05, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]322
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]323 MX25_PAD_CSPI1_SS0__CSPI1_SS0 = IOMUX_PAD(0x358, 0x160, 0x00, 0, 0, NO_PAD_CTRL),
324 MX25_PAD_CSPI1_SS0__GPIO_1_16 = IOMUX_PAD(0x358, 0x160, 0x05, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]325
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]326 MX25_PAD_CSPI1_SS1__CSPI1_SS1 = IOMUX_PAD(0x35c, 0x164, 0x00, 0, 0, NO_PAD_CTRL),
327 MX25_PAD_CSPI1_SS1__I2C3_DAT = IOMUX_PAD(0x35c, 0x164, 0x01, 0x528, 1, NO_PAD_CTRL),
328 MX25_PAD_CSPI1_SS1__GPIO_1_17 = IOMUX_PAD(0x35c, 0x164, 0x05, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]329
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]330 MX25_PAD_CSPI1_SCLK__CSPI1_SCLK = IOMUX_PAD(0x360, 0x168, 0x00, 0, 0, NO_PAD_CTRL),
331 MX25_PAD_CSPI1_SCLK__GPIO_1_18 = IOMUX_PAD(0x360, 0x168, 0x05, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]332
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]333 MX25_PAD_CSPI1_RDY__CSPI1_RDY = IOMUX_PAD(0x364, 0x16c, 0x00, 0, 0, PAD_CTL_PKE),
334 MX25_PAD_CSPI1_RDY__GPIO_2_22 = IOMUX_PAD(0x364, 0x16c, 0x05, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]335
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]336 MX25_PAD_UART1_RXD__UART1_RXD = IOMUX_PAD(0x368, 0x170, 0x00, 0, 0, PAD_CTL_PUS_100K_DOWN),
337 MX25_PAD_UART1_RXD__GPIO_4_22 = IOMUX_PAD(0x368, 0x170, 0x05, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]338
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]339 MX25_PAD_UART1_TXD__UART1_TXD = IOMUX_PAD(0x36c, 0x174, 0x00, 0, 0, NO_PAD_CTRL),
340 MX25_PAD_UART1_TXD__GPIO_4_23 = IOMUX_PAD(0x36c, 0x174, 0x05, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]341
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]342 MX25_PAD_UART1_RTS__UART1_RTS = IOMUX_PAD(0x370, 0x178, 0x00, 0, 0, PAD_CTL_PUS_100K_UP),
343 MX25_PAD_UART1_RTS__CSI_D0 = IOMUX_PAD(0x370, 0x178, 0x01, 0x488, 1, NO_PAD_CTRL),
344 MX25_PAD_UART1_RTS__GPIO_4_24 = IOMUX_PAD(0x370, 0x178, 0x05, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]345
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]346 MX25_PAD_UART1_CTS__UART1_CTS = IOMUX_PAD(0x374, 0x17c, 0x00, 0, 0, PAD_CTL_PUS_100K_UP),
347 MX25_PAD_UART1_CTS__CSI_D1 = IOMUX_PAD(0x374, 0x17c, 0x01, 0x48c, 1, NO_PAD_CTRL),
348 MX25_PAD_UART1_CTS__GPIO_4_25 = IOMUX_PAD(0x374, 0x17c, 0x05, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]349
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]350 MX25_PAD_UART2_RXD__UART2_RXD = IOMUX_PAD(0x378, 0x180, 0x00, 0, 0, NO_PAD_CTRL),
351 MX25_PAD_UART2_RXD__GPIO_4_26 = IOMUX_PAD(0x378, 0x180, 0x05, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]352
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]353 MX25_PAD_UART2_TXD__UART2_TXD = IOMUX_PAD(0x37c, 0x184, 0x00, 0, 0, NO_PAD_CTRL),
354 MX25_PAD_UART2_TXD__GPIO_4_27 = IOMUX_PAD(0x37c, 0x184, 0x05, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]355
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]356 MX25_PAD_UART2_RTS__UART2_RTS = IOMUX_PAD(0x380, 0x188, 0x00, 0, 0, NO_PAD_CTRL),
357 MX25_PAD_UART2_RTS__FEC_COL = IOMUX_PAD(0x380, 0x188, 0x02, 0x504, 2, NO_PAD_CTRL),
358 MX25_PAD_UART2_RTS__GPIO_4_28 = IOMUX_PAD(0x380, 0x188, 0x05, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]359
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]360 MX25_PAD_UART2_CTS__FEC_RX_ER = IOMUX_PAD(0x384, 0x18c, 0x02, 0x518, 2, NO_PAD_CTRL),
361 MX25_PAD_UART2_CTS__UART2_CTS = IOMUX_PAD(0x384, 0x18c, 0x00, 0, 0, NO_PAD_CTRL),
362 MX25_PAD_UART2_CTS__GPIO_4_29 = IOMUX_PAD(0x384, 0x18c, 0x05, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]363
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]364 /*
365 * Removing the SION bit from MX25_PAD_SD1_CMD__SD1_CMD breaks detecting an SD
366 * card. According to the i.MX25 reference manual (e.g. Figure 23-2 in IMX25RM
367 * Rev. 2 from 01/2011) this pin is bidirectional. So it seems to be a silicon
368 * bug that configuring the SD1_CMD function doesn't enable the input path for
369 * this pin.
370 * This might have side effects for other hardware units that are connected to
371 * that pin and use the respective function as input.
372 */
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]373 MX25_PAD_SD1_CMD__SD1_CMD = IOMUX_PAD(0x388, 0x190, 0x10, 0, 0, PAD_CTL_PUS_47K_UP),
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]374 MX25_PAD_SD1_CMD__FEC_RDATA2 = IOMUX_PAD(0x388, 0x190, 0x02, 0x50c, 2, NO_PAD_CTRL),
375 MX25_PAD_SD1_CMD__GPIO_2_23 = IOMUX_PAD(0x388, 0x190, 0x05, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]376
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]377 MX25_PAD_SD1_CLK__SD1_CLK = IOMUX_PAD(0x38c, 0x194, 0x00, 0, 0, PAD_CTL_PUS_47K_UP),
378 MX25_PAD_SD1_CLK__FEC_RDATA3 = IOMUX_PAD(0x38c, 0x194, 0x02, 0x510, 2, NO_PAD_CTRL),
379 MX25_PAD_SD1_CLK__GPIO_2_24 = IOMUX_PAD(0x38c, 0x194, 0x05, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]380
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]381 MX25_PAD_SD1_DATA0__SD1_DATA0 = IOMUX_PAD(0x390, 0x198, 0x00, 0, 0, PAD_CTL_PUS_47K_UP),
382 MX25_PAD_SD1_DATA0__GPIO_2_25 = IOMUX_PAD(0x390, 0x198, 0x05, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]383
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]384 MX25_PAD_SD1_DATA1__SD1_DATA1 = IOMUX_PAD(0x394, 0x19c, 0x00, 0, 0, PAD_CTL_PUS_47K_UP),
385 MX25_PAD_SD1_DATA1__AUD7_RXD = IOMUX_PAD(0x394, 0x19c, 0x03, 0x478, 0, NO_PAD_CTRL),
386 MX25_PAD_SD1_DATA1__GPIO_2_26 = IOMUX_PAD(0x394, 0x19c, 0x05, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]387
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]388 MX25_PAD_SD1_DATA2__SD1_DATA2 = IOMUX_PAD(0x398, 0x1a0, 0x00, 0, 0, PAD_CTL_PUS_47K_UP),
389 MX25_PAD_SD1_DATA2__FEC_RX_CLK = IOMUX_PAD(0x398, 0x1a0, 0x05, 0x514, 2, NO_PAD_CTRL),
390 MX25_PAD_SD1_DATA2__GPIO_2_27 = IOMUX_PAD(0x398, 0x1a0, 0x05, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]391
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]392 MX25_PAD_SD1_DATA3__SD1_DATA3 = IOMUX_PAD(0x39c, 0x1a4, 0x00, 0, 0, PAD_CTL_PUS_47K_UP),
393 MX25_PAD_SD1_DATA3__FEC_CRS = IOMUX_PAD(0x39c, 0x1a4, 0x00, 0x508, 2, NO_PAD_CTRL),
394 MX25_PAD_SD1_DATA3__GPIO_2_28 = IOMUX_PAD(0x39c, 0x1a4, 0x05, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]395
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]396 MX25_PAD_KPP_ROW0__KPP_ROW0 = IOMUX_PAD(0x3a0, 0x1a8, 0x00, 0, 0, MX25_KPP_ROW_PAD_CTRL),
397 MX25_PAD_KPP_ROW0__GPIO_2_29 = IOMUX_PAD(0x3a0, 0x1a8, 0x05, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]398
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]399 MX25_PAD_KPP_ROW1__KPP_ROW1 = IOMUX_PAD(0x3a4, 0x1ac, 0x00, 0, 0, MX25_KPP_ROW_PAD_CTRL),
400 MX25_PAD_KPP_ROW1__GPIO_2_30 = IOMUX_PAD(0x3a4, 0x1ac, 0x05, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]401
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]402 MX25_PAD_KPP_ROW2__KPP_ROW2 = IOMUX_PAD(0x3a8, 0x1b0, 0x00, 0, 0, MX25_KPP_ROW_PAD_CTRL),
403 MX25_PAD_KPP_ROW2__CSI_D0 = IOMUX_PAD(0x3a8, 0x1b0, 0x03, 0x488, 2, NO_PAD_CTRL),
404 MX25_PAD_KPP_ROW2__GPIO_2_31 = IOMUX_PAD(0x3a8, 0x1b0, 0x05, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]405
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]406 MX25_PAD_KPP_ROW3__KPP_ROW3 = IOMUX_PAD(0x3ac, 0x1b4, 0x00, 0, 0, MX25_KPP_ROW_PAD_CTRL),
407 MX25_PAD_KPP_ROW3__CSI_LD1 = IOMUX_PAD(0x3ac, 0x1b4, 0x03, 0x48c, 2, NO_PAD_CTRL),
408 MX25_PAD_KPP_ROW3__GPIO_3_0 = IOMUX_PAD(0x3ac, 0x1b4, 0x05, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]409
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]410 MX25_PAD_KPP_COL0__KPP_COL0 = IOMUX_PAD(0x3b0, 0x1b8, 0x00, 0, 0, MX25_KPP_COL_PAD_CTRL),
411 MX25_PAD_KPP_COL0__UART4_RXD_MUX = IOMUX_PAD(0x3b0, 0x1b8, 0x01, 0x570, 1, NO_PAD_CTRL),
412 MX25_PAD_KPP_COL0__AUD5_TXD = IOMUX_PAD(0x3b0, 0x1b8, 0x02, 0, 0, PAD_CTL_PUS_100K_UP),
413 MX25_PAD_KPP_COL0__GPIO_3_1 = IOMUX_PAD(0x3b0, 0x1b8, 0x05, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]414
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]415 MX25_PAD_KPP_COL1__KPP_COL1 = IOMUX_PAD(0x3b4, 0x1bc, 0x00, 0, 0, MX25_KPP_COL_PAD_CTRL),
416 MX25_PAD_KPP_COL1__UART4_TXD_MUX = IOMUX_PAD(0x3b4, 0x1bc, 0x01, 0, 0, NO_PAD_CTRL),
417 MX25_PAD_KPP_COL1__AUD5_RXD = IOMUX_PAD(0x3b4, 0x1bc, 0x02, 0, 0, PAD_CTL_PUS_100K_UP),
418 MX25_PAD_KPP_COL1__GPIO_3_2 = IOMUX_PAD(0x3b4, 0x1bc, 0x05, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]419
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]420 MX25_PAD_KPP_COL2__KPP_COL2 = IOMUX_PAD(0x3b8, 0x1c0, 0x00, 0, 0, MX25_KPP_COL_PAD_CTRL),
421 MX25_PAD_KPP_COL2__UART4_RTS = IOMUX_PAD(0x3b8, 0x1c0, 0x01, 0, 0, NO_PAD_CTRL),
422 MX25_PAD_KPP_COL2__AUD5_TXC = IOMUX_PAD(0x3b8, 0x1c0, 0x02, 0, 0, PAD_CTL_PUS_100K_UP),
423 MX25_PAD_KPP_COL2__GPIO_3_3 = IOMUX_PAD(0x3b8, 0x1c0, 0x05, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]424
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]425 MX25_PAD_KPP_COL3__KPP_COL3 = IOMUX_PAD(0x3bc, 0x1c4, 0x00, 0, 0, MX25_KPP_COL_PAD_CTRL),
426 MX25_PAD_KPP_COL3__UART4_CTS = IOMUX_PAD(0x3bc, 0x1c4, 0x01, 0, 0, NO_PAD_CTRL),
427 MX25_PAD_KPP_COL3__AUD5_TXFS = IOMUX_PAD(0x3bc, 0x1c4, 0x02, 0, 0, PAD_CTL_PUS_100K_UP),
428 MX25_PAD_KPP_COL3__GPIO_3_4 = IOMUX_PAD(0x3bc, 0x1c4, 0x05, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]429
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]430 MX25_PAD_FEC_MDC__FEC_MDC = IOMUX_PAD(0x3c0, 0x1c8, 0x00, 0, 0, NO_PAD_CTRL),
431 MX25_PAD_FEC_MDC__AUD4_TXD = IOMUX_PAD(0x3c0, 0x1c8, 0x02, 0x464, 1, NO_PAD_CTRL),
432 MX25_PAD_FEC_MDC__GPIO_3_5 = IOMUX_PAD(0x3c0, 0x1c8, 0x05, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]433
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]434 MX25_PAD_FEC_MDIO__FEC_MDIO = IOMUX_PAD(0x3c4, 0x1cc, 0x00, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_22K_UP),
435 MX25_PAD_FEC_MDIO__AUD4_RXD = IOMUX_PAD(0x3c4, 0x1cc, 0x02, 0x460, 1, NO_PAD_CTRL),
436 MX25_PAD_FEC_MDIO__GPIO_3_6 = IOMUX_PAD(0x3c4, 0x1cc, 0x05, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]437
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]438 MX25_PAD_FEC_TDATA0__FEC_TDATA0 = IOMUX_PAD(0x3c8, 0x1d0, 0x00, 0, 0, NO_PAD_CTRL),
439 MX25_PAD_FEC_TDATA0__GPIO_3_7 = IOMUX_PAD(0x3c8, 0x1d0, 0x05, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]440
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]441 MX25_PAD_FEC_TDATA1__FEC_TDATA1 = IOMUX_PAD(0x3cc, 0x1d4, 0x00, 0, 0, NO_PAD_CTRL),
442 MX25_PAD_FEC_TDATA1__AUD4_TXFS = IOMUX_PAD(0x3cc, 0x1d4, 0x02, 0x474, 1, NO_PAD_CTRL),
443 MX25_PAD_FEC_TDATA1__GPIO_3_8 = IOMUX_PAD(0x3cc, 0x1d4, 0x05, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]444
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]445 MX25_PAD_FEC_TX_EN__FEC_TX_EN = IOMUX_PAD(0x3d0, 0x1d8, 0x00, 0, 0, NO_PAD_CTRL),
446 MX25_PAD_FEC_TX_EN__GPIO_3_9 = IOMUX_PAD(0x3d0, 0x1d8, 0x05, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]447
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]448 MX25_PAD_FEC_RDATA0__FEC_RDATA0 = IOMUX_PAD(0x3d4, 0x1dc, 0x00, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
449 MX25_PAD_FEC_RDATA0__GPIO_3_10 = IOMUX_PAD(0x3d4, 0x1dc, 0x05, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]450
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]451 MX25_PAD_FEC_RDATA1__FEC_RDATA1 = IOMUX_PAD(0x3d8, 0x1e0, 0x00, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
452 MX25_PAD_FEC_RDATA1__GPIO_3_11 = IOMUX_PAD(0x3d8, 0x1e0, 0x05, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]453
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]454 MX25_PAD_FEC_RX_DV__FEC_RX_DV = IOMUX_PAD(0x3dc, 0x1e4, 0x00, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
455 MX25_PAD_FEC_RX_DV__CAN2_RX = IOMUX_PAD(0x3dc, 0x1e4, 0x04, 0x484, 0, PAD_CTL_PUS_22K_UP),
456 MX25_PAD_FEC_RX_DV__GPIO_3_12 = IOMUX_PAD(0x3dc, 0x1e4, 0x05, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]457
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]458 MX25_PAD_FEC_TX_CLK__FEC_TX_CLK = IOMUX_PAD(0x3e0, 0x1e8, 0x00, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
459 MX25_PAD_FEC_TX_CLK__GPIO_3_13 = IOMUX_PAD(0x3e0, 0x1e8, 0x05, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]460
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]461 MX25_PAD_RTCK__RTCK = IOMUX_PAD(0x3e4, 0x1ec, 0x00, 0, 0, NO_PAD_CTRL),
462 MX25_PAD_RTCK__OWIRE = IOMUX_PAD(0x3e4, 0x1ec, 0x01, 0, 0, NO_PAD_CTRL),
463 MX25_PAD_RTCK__GPIO_3_14 = IOMUX_PAD(0x3e4, 0x1ec, 0x05, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]464
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]465 MX25_PAD_DE_B__DE_B = IOMUX_PAD(0x3ec, 0x1f0, 0x00, 0, 0, NO_PAD_CTRL),
466 MX25_PAD_DE_B__GPIO_2_20 = IOMUX_PAD(0x3ec, 0x1f0, 0x05, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]467
468 MX25_PAD_TDO__TDO = IOMUX_PAD(0x3e8, 0x000, 0x00, 0, 0, NO_PAD_CTRL),
469
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]470 MX25_PAD_GPIO_A__GPIO_A = IOMUX_PAD(0x3f0, 0x1f4, 0x00, 0, 0, NO_PAD_CTRL),
471 MX25_PAD_GPIO_A__CAN1_TX = IOMUX_PAD(0x3f0, 0x1f4, 0x06, 0, 0, PAD_CTL_PUS_22K_UP),
472 MX25_PAD_GPIO_A__USBOTG_PWR = IOMUX_PAD(0x3f0, 0x1f4, 0x02, 0, 0, PAD_CTL_PKE),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]473
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]474 MX25_PAD_GPIO_B__GPIO_B = IOMUX_PAD(0x3f4, 0x1f8, 0x00, 0, 0, NO_PAD_CTRL),
475 MX25_PAD_GPIO_B__CAN1_RX = IOMUX_PAD(0x3f4, 0x1f8, 0x06, 0x480, 1, PAD_CTL_PUS_22K_UP),
476 MX25_PAD_GPIO_B__USBOTG_OC = IOMUX_PAD(0x3f4, 0x1f8, 0x02, 0x57c, 1, PAD_CTL_PUS_100K_UP),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]477
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]478 MX25_PAD_GPIO_C__GPIO_C = IOMUX_PAD(0x3f8, 0x1fc, 0x00, 0, 0, NO_PAD_CTRL),
479 MX25_PAD_GPIO_C__CAN2_TX = IOMUX_PAD(0x3f8, 0x1fc, 0x06, 0, 0, PAD_CTL_PUS_22K_UP),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]480
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]481 MX25_PAD_GPIO_D__GPIO_D = IOMUX_PAD(0x3fc, 0x200, 0x00, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]482 MX25_PAD_GPIO_E__LD16 = IOMUX_PAD(0x400, 0x204, 0x02, 0, 0, PAD_CTL_SRE_FAST),
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]483 MX25_PAD_GPIO_D__CAN2_RX = IOMUX_PAD(0x3fc, 0x200, 0x06, 0x484, 1, PAD_CTL_PUS_22K_UP),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]484
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]485 MX25_PAD_GPIO_E__GPIO_E = IOMUX_PAD(0x400, 0x204, 0x00, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]486 MX25_PAD_GPIO_F__LD17 = IOMUX_PAD(0x404, 0x208, 0x02, 0, 0, PAD_CTL_SRE_FAST),
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]487 MX25_PAD_GPIO_E__I2C3_CLK = IOMUX_PAD(0x400, 0x204, 0x01, 0x524, 2, NO_PAD_CTRL),
488 MX25_PAD_GPIO_E__AUD7_TXD = IOMUX_PAD(0x400, 0x204, 0x04, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]489
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]490 MX25_PAD_GPIO_F__GPIO_F = IOMUX_PAD(0x404, 0x208, 0x00, 0, 0, NO_PAD_CTRL),
491 MX25_PAD_GPIO_F__AUD7_TXC = IOMUX_PAD(0x404, 0x208, 0x04, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]492
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]493 MX25_PAD_EXT_ARMCLK__EXT_ARMCLK = IOMUX_PAD(0x000, 0x20c, 0x00, 0, 0, NO_PAD_CTRL),
494 MX25_PAD_EXT_ARMCLK__GPIO_3_15 = IOMUX_PAD(0x000, 0x20c, 0x05, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]495
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]496 MX25_PAD_UPLL_BYPCLK__UPLL_BYPCLK = IOMUX_PAD(0x000, 0x210, 0x00, 0, 0, NO_PAD_CTRL),
497 MX25_PAD_UPLL_BYPCLK__GPIO_3_16 = IOMUX_PAD(0x000, 0x210, 0x05, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]498
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]499 MX25_PAD_VSTBY_REQ__VSTBY_REQ = IOMUX_PAD(0x408, 0x214, 0x00, 0, 0, NO_PAD_CTRL),
500 MX25_PAD_VSTBY_REQ__AUD7_TXFS = IOMUX_PAD(0x408, 0x214, 0x04, 0, 0, NO_PAD_CTRL),
501 MX25_PAD_VSTBY_REQ__GPIO_3_17 = IOMUX_PAD(0x408, 0x214, 0x05, 0, 0, NO_PAD_CTRL),
502 MX25_PAD_VSTBY_ACK__VSTBY_ACK = IOMUX_PAD(0x40c, 0x218, 0x00, 0, 0, NO_PAD_CTRL),
503 MX25_PAD_VSTBY_ACK__GPIO_3_18 = IOMUX_PAD(0x40c, 0x218, 0x05, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]504
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]505 MX25_PAD_POWER_FAIL__POWER_FAIL = IOMUX_PAD(0x410, 0x21c, 0x00, 0, 0, NO_PAD_CTRL),
506 MX25_PAD_POWER_FAIL__AUD7_RXD = IOMUX_PAD(0x410, 0x21c, 0x04, 0x478, 1, NO_PAD_CTRL),
507 MX25_PAD_POWER_FAIL__GPIO_3_19 = IOMUX_PAD(0x410, 0x21c, 0x05, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]508
Michael Trimarchi43b1ba32018-01-25 14:06:11 +0100[diff] [blame]509 MX25_PAD_CLKO__CLKO = IOMUX_PAD(0x414, 0x220, 0x00, 0, 0, NO_PAD_CTRL),
510 MX25_PAD_CLKO__GPIO_2_21 = IOMUX_PAD(0x414, 0x220, 0x05, 0, 0, NO_PAD_CTRL),
Benoît Thébaudeau689a1582013-05-03 10:32:13 +0000[diff] [blame]511
512 MX25_PAD_BOOT_MODE0__BOOT_MODE0 = IOMUX_PAD(0x000, 0x224, 0x00, 0, 0, NO_PAD_CTRL),
513 MX25_PAD_BOOT_MODE0__GPIO_4_30 = IOMUX_PAD(0x000, 0x224, 0x05, 0, 0, NO_PAD_CTRL),
514 MX25_PAD_BOOT_MODE1__BOOT_MODE1 = IOMUX_PAD(0x000, 0x228, 0x00, 0, 0, NO_PAD_CTRL),
515 MX25_PAD_BOOT_MODE1__GPIO_4_31 = IOMUX_PAD(0x000, 0x228, 0x05, 0, 0, NO_PAD_CTRL),
516
517 MX25_PAD_CTL_GRP_DVS_MISC = IOMUX_PAD(0x418, 0x000, 0, 0, 0, NO_PAD_CTRL),
518 MX25_PAD_CTL_GRP_DSE_FEC = IOMUX_PAD(0x41c, 0x000, 0, 0, 0, NO_PAD_CTRL),
519 MX25_PAD_CTL_GRP_DVS_JTAG = IOMUX_PAD(0x420, 0x000, 0, 0, 0, NO_PAD_CTRL),
520 MX25_PAD_CTL_GRP_DSE_NFC = IOMUX_PAD(0x424, 0x000, 0, 0, 0, NO_PAD_CTRL),
521 MX25_PAD_CTL_GRP_DSE_CSI = IOMUX_PAD(0x428, 0x000, 0, 0, 0, NO_PAD_CTRL),
522 MX25_PAD_CTL_GRP_DSE_WEIM = IOMUX_PAD(0x42c, 0x000, 0, 0, 0, NO_PAD_CTRL),
523 MX25_PAD_CTL_GRP_DSE_DDR = IOMUX_PAD(0x430, 0x000, 0, 0, 0, NO_PAD_CTRL),
524 MX25_PAD_CTL_GRP_DVS_CRM = IOMUX_PAD(0x434, 0x000, 0, 0, 0, NO_PAD_CTRL),
525 MX25_PAD_CTL_GRP_DSE_KPP = IOMUX_PAD(0x438, 0x000, 0, 0, 0, NO_PAD_CTRL),
526 MX25_PAD_CTL_GRP_DSE_SDHC1 = IOMUX_PAD(0x43c, 0x000, 0, 0, 0, NO_PAD_CTRL),
527 MX25_PAD_CTL_GRP_DSE_LCD = IOMUX_PAD(0x440, 0x000, 0, 0, 0, NO_PAD_CTRL),
528 MX25_PAD_CTL_GRP_DSE_UART = IOMUX_PAD(0x444, 0x000, 0, 0, 0, NO_PAD_CTRL),
529 MX25_PAD_CTL_GRP_DVS_NFC = IOMUX_PAD(0x448, 0x000, 0, 0, 0, NO_PAD_CTRL),
530 MX25_PAD_CTL_GRP_DVS_CSI = IOMUX_PAD(0x44c, 0x000, 0, 0, 0, NO_PAD_CTRL),
531 MX25_PAD_CTL_GRP_DSE_CSPI1 = IOMUX_PAD(0x450, 0x000, 0, 0, 0, NO_PAD_CTRL),
532 MX25_PAD_CTL_GRP_DDRTYPE = IOMUX_PAD(0x454, 0x000, 0, 0, 0, NO_PAD_CTRL),
533 MX25_PAD_CTL_GRP_DVS_SDHC1 = IOMUX_PAD(0x458, 0x000, 0, 0, 0, NO_PAD_CTRL),
534 MX25_PAD_CTL_GRP_DVS_LCD = IOMUX_PAD(0x45c, 0x000, 0, 0, 0, NO_PAD_CTRL),
535};
536
537#endif /* __IOMUX_MX25_H__ */