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Apurva Nandan67ebc302024-02-24 01:51:41 +05301// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * J784S4: SoC specific initialization
4 *
5 * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
6 * Hari Nagalla <hnagalla@ti.com>
7 */
8
9#include <init.h>
10#include <spl.h>
11#include <asm/io.h>
12#include <asm/armv7_mpu.h>
13#include <asm/arch/hardware.h>
Apurva Nandan67ebc302024-02-24 01:51:41 +053014#include <linux/soc/ti/ti_sci_protocol.h>
15#include <dm.h>
16#include <dm/uclass-internal.h>
17#include <dm/pinctrl.h>
18#include <mmc.h>
19#include <remoteproc.h>
20
Andrew Davis336b0792024-05-10 15:21:24 -050021#include "../sysfw-loader.h"
22#include "../common.h"
23
Apurva Nandan67ebc302024-02-24 01:51:41 +053024#define J784S4_MAX_DDR_CONTROLLERS 4
25
26struct fwl_data infra_cbass0_fwls[] = {
27 { "PSC0", 5, 1 },
28 { "PLL_CTRL0", 6, 1 },
29 { "PLL_MMR0", 8, 26 },
30 { "CTRL_MMR0", 9, 16 },
31 { "GPIO0", 16, 1 },
32}, wkup_cbass0_fwls[] = {
33 { "WKUP_PSC0", 129, 1 },
34 { "WKUP_PLL_CTRL0", 130, 1 },
35 { "WKUP_CTRL_MMR0", 131, 16 },
36 { "WKUP_GPIO0", 132, 1 },
37 { "WKUP_I2C0", 144, 1 },
38 { "WKUP_USART0", 160, 1 },
39}, mcu_cbass0_fwls[] = {
40 { "MCU_R5FSS0_CORE0", 1024, 4 },
41 { "MCU_R5FSS0_CORE0_CFG", 1025, 3 },
42 { "MCU_R5FSS0_CORE1", 1028, 4 },
43 { "MCU_R5FSS0_CORE1_CFG", 1029, 1 },
44 { "MCU_FSS0_CFG", 1032, 12 },
45 { "MCU_FSS0_S1", 1033, 8 },
46 { "MCU_FSS0_S0", 1036, 8 },
47 { "MCU_PSROM49152X32", 1048, 1 },
48 { "MCU_MSRAM128KX64", 1050, 8 },
49 { "MCU_MSRAM128KX64_CFG", 1051, 1 },
50 { "MCU_TIMER0", 1056, 1 },
51 { "MCU_TIMER9", 1065, 1 },
52 { "MCU_USART0", 1120, 1 },
53 { "MCU_I2C0", 1152, 1 },
54 { "MCU_CTRL_MMR0", 1200, 8 },
55 { "MCU_PLL_MMR0", 1201, 3 },
56 { "MCU_CPSW0", 1220, 2 },
57}, cbass_rc_cfg0_fwls[] = {
58 { "EMMCSD4SS0_CFG", 2400, 4 },
59}, cbass_hc2_fwls[] = {
60 { "PCIE0", 2547, 24 },
61}, cbass_hc_cfg0_fwls[] = {
62 { "PCIE0_CFG", 2577, 7 },
63 { "EMMC8SS0_CFG", 2579, 4 },
64 { "USB3SS0_CORE", 2580, 4 },
65 { "USB3SS1_CORE", 2581, 1 },
66}, navss_cbass0_fwls[] = {
67 { "NACSS_VIRT0", 6253, 1 },
68};
69
70static void ctrl_mmr_unlock(void)
71{
72 /* Unlock all WKUP_CTRL_MMR0 module registers */
73 mmr_unlock(WKUP_CTRL_MMR0_BASE, 0);
74 mmr_unlock(WKUP_CTRL_MMR0_BASE, 1);
75 mmr_unlock(WKUP_CTRL_MMR0_BASE, 2);
76 mmr_unlock(WKUP_CTRL_MMR0_BASE, 3);
77 mmr_unlock(WKUP_CTRL_MMR0_BASE, 4);
78 mmr_unlock(WKUP_CTRL_MMR0_BASE, 6);
79 mmr_unlock(WKUP_CTRL_MMR0_BASE, 7);
80
81 /* Unlock all MCU_CTRL_MMR0 module registers */
82 mmr_unlock(MCU_CTRL_MMR0_BASE, 0);
83 mmr_unlock(MCU_CTRL_MMR0_BASE, 1);
84 mmr_unlock(MCU_CTRL_MMR0_BASE, 2);
85 mmr_unlock(MCU_CTRL_MMR0_BASE, 3);
86 mmr_unlock(MCU_CTRL_MMR0_BASE, 4);
87
88 /* Unlock all CTRL_MMR0 module registers */
89 mmr_unlock(CTRL_MMR0_BASE, 0);
90 mmr_unlock(CTRL_MMR0_BASE, 1);
91 mmr_unlock(CTRL_MMR0_BASE, 2);
92 mmr_unlock(CTRL_MMR0_BASE, 3);
93 mmr_unlock(CTRL_MMR0_BASE, 5);
94 mmr_unlock(CTRL_MMR0_BASE, 7);
95}
96
97/*
98 * This uninitialized global variable would normal end up in the .bss section,
99 * but the .bss is cleared between writing and reading this variable, so move
100 * it to the .data section.
101 */
102u32 bootindex __section(".data");
103static struct rom_extended_boot_data bootdata __section(".data");
104
105static void store_boot_info_from_rom(void)
106{
107 bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX);
108 memcpy(&bootdata, (uintptr_t *)ROM_EXTENDED_BOOT_DATA_INFO,
109 sizeof(struct rom_extended_boot_data));
110}
111
112void k3_spl_init(void)
113{
114 struct udevice *dev;
115 int ret;
116
117 /*
118 * Cannot delay this further as there is a chance that
119 * K3_BOOT_PARAM_TABLE_INDEX can be over written by SPL MALLOC section.
120 */
121 store_boot_info_from_rom();
122
123 /* Make all control module registers accessible */
124 ctrl_mmr_unlock();
125
126 if (IS_ENABLED(CONFIG_CPU_V7R)) {
127 disable_linefill_optimization();
128 setup_k3_mpu_regions();
129 }
130
131 /* Init DM early */
132 ret = spl_early_init();
133
134 /* Prepare console output */
135 preloader_console_init();
136
137 if (IS_ENABLED(CONFIG_CPU_V7R)) {
138 /*
139 * Process pinctrl for the serial0 a.k.a. WKUP_UART0 module and continue
140 * regardless of the result of pinctrl. Do this without probing the
141 * device, but instead by searching the device that would request the
142 * given sequence number if probed. The UART will be used by the system
143 * firmware (TIFS) image for various purposes and TIFS depends on us
144 * to initialize its pin settings.
145 */
146 ret = uclass_find_device_by_seq(UCLASS_SERIAL, 0, &dev);
147 if (!ret)
148 pinctrl_select_state(dev, "default");
149
150 /*
151 * Load, start up, and configure system controller firmware. Provide
152 * the U-Boot console init function to the TIFS post-PM configuration
153 * callback hook, effectively switching on (or over) the console
154 * output.
155 */
156 k3_sysfw_loader(is_rom_loaded_sysfw(&bootdata), NULL, NULL);
157
158 if (IS_ENABLED(CONFIG_SPL_CLK_K3)) {
159 /*
160 * Force probe of clk_k3 driver here to ensure basic default clock
161 * configuration is always done for enabling PM services.
162 */
163 ret = uclass_get_device_by_driver(UCLASS_CLK,
164 DM_DRIVER_GET(ti_clk),
165 &dev);
166 if (ret)
167 panic("Failed to initialize clk-k3!\n");
168 }
169
170 remove_fwl_configs(cbass_hc_cfg0_fwls, ARRAY_SIZE(cbass_hc_cfg0_fwls));
171 remove_fwl_configs(cbass_hc2_fwls, ARRAY_SIZE(cbass_hc2_fwls));
172 remove_fwl_configs(cbass_rc_cfg0_fwls, ARRAY_SIZE(cbass_rc_cfg0_fwls));
173 remove_fwl_configs(infra_cbass0_fwls, ARRAY_SIZE(infra_cbass0_fwls));
174 remove_fwl_configs(mcu_cbass0_fwls, ARRAY_SIZE(mcu_cbass0_fwls));
175 remove_fwl_configs(wkup_cbass0_fwls, ARRAY_SIZE(wkup_cbass0_fwls));
176 remove_fwl_configs(navss_cbass0_fwls, ARRAY_SIZE(navss_cbass0_fwls));
177 }
178
179 /* Output System Firmware version info */
180 k3_sysfw_print_ver();
181}
182
183void k3_mem_init(void)
184{
185 struct udevice *dev;
186 int ret, ctrl = 0;
187
188 if (IS_ENABLED(CONFIG_K3_J721E_DDRSS)) {
189 ret = uclass_get_device(UCLASS_RAM, 0, &dev);
190 if (ret)
191 panic("DRAM 0 init failed: %d\n", ret);
192 ctrl++;
193
194 while (ctrl < J784S4_MAX_DDR_CONTROLLERS) {
195 ret = uclass_next_device_err(&dev);
196 if (ret == -ENODEV)
197 break;
198
199 if (ret)
200 panic("DRAM %d init failed: %d\n", ctrl, ret);
201 ctrl++;
202 }
203 printf("Initialized %d DRAM controllers\n", ctrl);
204 }
205
206 spl_enable_cache();
207}
208
209void board_init_f(ulong dummy)
210{
211 k3_spl_init();
212 k3_mem_init();
213}
214
215u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)
216{
217 switch (boot_device) {
218 case BOOT_DEVICE_MMC1:
219 if (IS_ENABLED(CONFIG_SUPPORT_EMMC_BOOT))
220 return MMCSD_MODE_EMMCBOOT;
221 if (IS_ENABLED(CONFIG_SPL_FS_FAT) || IS_ENABLED(CONFIG_SPL_FS_EXT4))
222 return MMCSD_MODE_FS;
223 return MMCSD_MODE_EMMCBOOT;
224 case BOOT_DEVICE_MMC2:
225 return MMCSD_MODE_FS;
226 default:
227 return MMCSD_MODE_RAW;
228 }
229}
230
231static u32 __get_backup_bootmedia(u32 main_devstat)
232{
233 u32 bkup_boot = (main_devstat & MAIN_DEVSTAT_BKUP_BOOTMODE_MASK) >>
234 MAIN_DEVSTAT_BKUP_BOOTMODE_SHIFT;
235
236 switch (bkup_boot) {
237 case BACKUP_BOOT_DEVICE_USB:
238 return BOOT_DEVICE_DFU;
239 case BACKUP_BOOT_DEVICE_UART:
240 return BOOT_DEVICE_UART;
241 case BACKUP_BOOT_DEVICE_ETHERNET:
242 return BOOT_DEVICE_ETHERNET;
243 case BACKUP_BOOT_DEVICE_MMC2:
244 {
245 u32 port = (main_devstat & MAIN_DEVSTAT_BKUP_MMC_PORT_MASK) >>
246 MAIN_DEVSTAT_BKUP_MMC_PORT_SHIFT;
247 if (port == 0x0)
248 return BOOT_DEVICE_MMC1;
249 return BOOT_DEVICE_MMC2;
250 }
251 case BACKUP_BOOT_DEVICE_SPI:
252 return BOOT_DEVICE_SPI;
253 case BACKUP_BOOT_DEVICE_I2C:
254 return BOOT_DEVICE_I2C;
255 }
256
257 return BOOT_DEVICE_RAM;
258}
259
260static u32 __get_primary_bootmedia(u32 main_devstat, u32 wkup_devstat)
261{
262 u32 bootmode = (wkup_devstat & WKUP_DEVSTAT_PRIMARY_BOOTMODE_MASK) >>
263 WKUP_DEVSTAT_PRIMARY_BOOTMODE_SHIFT;
264
265 bootmode |= (main_devstat & MAIN_DEVSTAT_BOOT_MODE_B_MASK) <<
266 BOOT_MODE_B_SHIFT;
267
268 if (bootmode == BOOT_DEVICE_OSPI || bootmode == BOOT_DEVICE_QSPI ||
269 bootmode == BOOT_DEVICE_XSPI)
270 bootmode = BOOT_DEVICE_SPI;
271
272 if (bootmode == BOOT_DEVICE_MMC2) {
273 u32 port = (main_devstat &
274 MAIN_DEVSTAT_PRIM_BOOTMODE_MMC_PORT_MASK) >>
275 MAIN_DEVSTAT_PRIM_BOOTMODE_PORT_SHIFT;
276 if (port == 0x0)
277 bootmode = BOOT_DEVICE_MMC1;
278 }
279
280 return bootmode;
281}
282
283u32 spl_spi_boot_bus(void)
284{
285 u32 wkup_devstat = readl(CTRLMMR_WKUP_DEVSTAT);
286 u32 main_devstat = readl(CTRLMMR_MAIN_DEVSTAT);
287 u32 bootmode = ((wkup_devstat & WKUP_DEVSTAT_PRIMARY_BOOTMODE_MASK) >>
288 WKUP_DEVSTAT_PRIMARY_BOOTMODE_SHIFT) |
289 ((main_devstat & MAIN_DEVSTAT_BOOT_MODE_B_MASK) << BOOT_MODE_B_SHIFT);
290
291 return (bootmode == BOOT_DEVICE_QSPI) ? 1 : 0;
292}
293
294u32 spl_boot_device(void)
295{
296 u32 wkup_devstat = readl(CTRLMMR_WKUP_DEVSTAT);
297 u32 main_devstat;
298
299 if (wkup_devstat & WKUP_DEVSTAT_MCU_ONLY_MASK) {
300 printf("ERROR: MCU only boot is not yet supported\n");
301 return BOOT_DEVICE_RAM;
302 }
303
304 /* MAIN CTRL MMR can only be read if MCU ONLY is 0 */
305 main_devstat = readl(CTRLMMR_MAIN_DEVSTAT);
306
307 if (bootindex == K3_PRIMARY_BOOTMODE)
308 return __get_primary_bootmedia(main_devstat, wkup_devstat);
309 else
310 return __get_backup_bootmedia(main_devstat);
311}