Jon Loeliger | 3e2d091 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2007 Freescale Semiconductor, Inc. |
| 3 | * |
| 4 | * See file CREDITS for list of people who contributed to this |
| 5 | * project. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
| 9 | * published by the Free Software Foundation; either version 2 of |
| 10 | * the License, or (at your option) any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 20 | * MA 02111-1307 USA |
| 21 | */ |
| 22 | |
| 23 | /* |
| 24 | * mpc8544ds board configuration file |
| 25 | * |
| 26 | */ |
| 27 | #ifndef __CONFIG_H |
| 28 | #define __CONFIG_H |
| 29 | |
| 30 | /* High Level Configuration Options */ |
| 31 | #define CONFIG_BOOKE 1 /* BOOKE */ |
| 32 | #define CONFIG_E500 1 /* BOOKE e500 family */ |
| 33 | #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ |
| 34 | #define CONFIG_MPC8544 1 |
| 35 | #define CONFIG_MPC8544DS 1 |
| 36 | |
Ed Swarthout | 52b9852 | 2007-07-27 01:50:51 -0500 | [diff] [blame] | 37 | #define CONFIG_PCI 1 /* Enable PCI/PCIE */ |
| 38 | #define CONFIG_PCI1 1 /* PCI controller 1 */ |
| 39 | #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ |
| 40 | #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ |
| 41 | #define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */ |
| 42 | #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ |
Kumar Gala | 93166d2 | 2007-12-07 12:17:34 -0600 | [diff] [blame] | 43 | #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ |
Jon Loeliger | 3e2d091 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 44 | |
Kumar Gala | 85af2b5 | 2008-01-16 01:16:16 -0600 | [diff] [blame] | 45 | #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ |
| 46 | |
Ed Swarthout | 52b9852 | 2007-07-27 01:50:51 -0500 | [diff] [blame] | 47 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ |
Jon Loeliger | 3e2d091 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 48 | #define CONFIG_ENV_OVERWRITE |
Ed Swarthout | 52b9852 | 2007-07-27 01:50:51 -0500 | [diff] [blame] | 49 | #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ |
Jon Loeliger | 3e2d091 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 50 | |
| 51 | /* |
| 52 | * When initializing flash, if we cannot find the manufacturer ID, |
| 53 | * assume this is the AMD flash associated with the CDS board. |
| 54 | * This allows booting from a promjet. |
| 55 | */ |
| 56 | #define CONFIG_ASSUME_AMD_FLASH |
| 57 | |
Jon Loeliger | 3e2d091 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 58 | #ifndef __ASSEMBLY__ |
| 59 | extern unsigned long get_board_sys_clk(unsigned long dummy); |
| 60 | #endif |
| 61 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */ |
| 62 | |
| 63 | /* |
| 64 | * These can be toggled for performance analysis, otherwise use default. |
| 65 | */ |
Ed Swarthout | 52b9852 | 2007-07-27 01:50:51 -0500 | [diff] [blame] | 66 | #define CONFIG_L2_CACHE /* toggle L2 cache */ |
Jon Loeliger | 3e2d091 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 67 | #define CONFIG_BTB /* toggle branch predition */ |
| 68 | #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ |
Jon Loeliger | 3e2d091 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 69 | |
| 70 | /* |
| 71 | * Only possible on E500 Version 2 or newer cores. |
| 72 | */ |
| 73 | #define CONFIG_ENABLE_36BIT_PHYS 1 |
| 74 | |
Jon Loeliger | 3e2d091 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 75 | #define CFG_MEMTEST_START 0x00200000 /* memtest works on */ |
| 76 | #define CFG_MEMTEST_END 0x00400000 |
Ed Swarthout | 52b9852 | 2007-07-27 01:50:51 -0500 | [diff] [blame] | 77 | #define CONFIG_PANIC_HANG /* do not reset board on panic */ |
Jon Loeliger | 3e2d091 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 78 | |
| 79 | /* |
| 80 | * Base addresses -- Note these are effective addresses where the |
| 81 | * actual resources get mapped (not physical addresses) |
| 82 | */ |
Ed Swarthout | 52b9852 | 2007-07-27 01:50:51 -0500 | [diff] [blame] | 83 | #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ |
Jon Loeliger | 3e2d091 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 84 | #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ |
Kumar Gala | d33a55f | 2008-01-30 14:55:14 -0600 | [diff] [blame] | 85 | #define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ |
Jon Loeliger | 3e2d091 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 86 | #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ |
| 87 | |
| 88 | #define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000) |
| 89 | #define CFG_PCIE1_ADDR (CFG_CCSRBAR+0xa000) |
| 90 | #define CFG_PCIE2_ADDR (CFG_CCSRBAR+0x9000) |
| 91 | #define CFG_PCIE3_ADDR (CFG_CCSRBAR+0xb000) |
| 92 | |
Kumar Gala | 573ad30 | 2008-08-26 08:02:30 -0500 | [diff] [blame] | 93 | /* DDR Setup */ |
| 94 | #define CONFIG_FSL_DDR2 |
| 95 | #undef CONFIG_FSL_DDR_INTERACTIVE |
| 96 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ |
| 97 | #define CONFIG_DDR_SPD |
| 98 | |
| 99 | #undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ |
| 100 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef |
| 101 | |
| 102 | #define CFG_DDR_SDRAM_BASE 0x00000000 |
Jon Loeliger | 3e2d091 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 103 | #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE |
Kumar Gala | 573ad30 | 2008-08-26 08:02:30 -0500 | [diff] [blame] | 104 | #define CONFIG_VERY_BIG_RAM |
| 105 | |
| 106 | #define CONFIG_NUM_DDR_CONTROLLERS 1 |
| 107 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 |
| 108 | #define CONFIG_CHIP_SELECTS_PER_CTRL 2 |
Jon Loeliger | 3e2d091 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 109 | |
Kumar Gala | 573ad30 | 2008-08-26 08:02:30 -0500 | [diff] [blame] | 110 | /* I2C addresses of SPD EEPROMs */ |
Jon Loeliger | 3e2d091 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 111 | #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ |
| 112 | |
Kumar Gala | 573ad30 | 2008-08-26 08:02:30 -0500 | [diff] [blame] | 113 | /* Make sure required options are set */ |
Jon Loeliger | 3e2d091 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 114 | #ifndef CONFIG_SPD_EEPROM |
| 115 | #error ("CONFIG_SPD_EEPROM is required") |
| 116 | #endif |
| 117 | |
| 118 | #undef CONFIG_CLOCKS_IN_MHZ |
| 119 | |
| 120 | /* |
| 121 | * Memory map |
| 122 | * |
| 123 | * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable |
| 124 | * |
| 125 | * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable |
| 126 | * |
| 127 | * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable |
| 128 | * |
| 129 | * 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable |
| 130 | * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable |
| 131 | * |
| 132 | * Localbus cacheable |
| 133 | * |
| 134 | * 0xf000_0000 0xf3ff_ffff SDRAM 64M Cacheable |
| 135 | * 0xf401_0000 0xf401_3fff L1 for stack 4K Cacheable TLB0 |
| 136 | * |
| 137 | * Localbus non-cacheable |
| 138 | * |
| 139 | * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M non-cacheable |
| 140 | * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable |
| 141 | * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable |
| 142 | * |
| 143 | */ |
| 144 | |
| 145 | /* |
| 146 | * Local Bus Definitions |
| 147 | */ |
| 148 | #define CFG_BOOT_BLOCK 0xfc000000 /* boot TLB */ |
| 149 | |
Jon Loeliger | 3e2d091 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 150 | #define CFG_FLASH_BASE 0xff800000 /* start of FLASH 8M */ |
| 151 | |
| 152 | #define CFG_BR0_PRELIM 0xff801001 |
| 153 | #define CFG_BR1_PRELIM 0xfe801001 |
| 154 | |
| 155 | #define CFG_OR0_PRELIM 0xff806e65 |
| 156 | #define CFG_OR1_PRELIM 0xff806e65 |
| 157 | |
Andy Fleming | d4cba1e | 2008-07-14 20:26:57 -0500 | [diff] [blame] | 158 | #define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE} |
Jon Loeliger | 3e2d091 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 159 | |
Roy Zang | fd2896b | 2008-04-25 00:55:09 -0500 | [diff] [blame] | 160 | #define CFG_FLASH_QUIET_TEST |
Andy Fleming | d4cba1e | 2008-07-14 20:26:57 -0500 | [diff] [blame] | 161 | #define CFG_MAX_FLASH_BANKS 1 /* number of banks */ |
Jon Loeliger | 3e2d091 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 162 | #define CFG_MAX_FLASH_SECT 128 /* sectors per device */ |
| 163 | #undef CFG_FLASH_CHECKSUM |
| 164 | #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ |
| 165 | #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ |
Kumar Gala | ded59a1 | 2008-06-09 18:55:38 -0500 | [diff] [blame] | 166 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ |
Jon Loeliger | 3e2d091 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 167 | |
| 168 | #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ |
| 169 | |
Jean-Christophe PLAGNIOL-VILLARD | 8d94c23 | 2008-08-13 01:40:42 +0200 | [diff] [blame] | 170 | #define CONFIG_FLASH_CFI_DRIVER |
Jon Loeliger | 3e2d091 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 171 | #define CFG_FLASH_CFI |
| 172 | #define CFG_FLASH_EMPTY_INFO |
| 173 | |
| 174 | #define CFG_LBC_NONCACHE_BASE 0xf8000000 |
| 175 | |
| 176 | #define CFG_BR2_PRELIM 0xf8201001 /* port size 16bit */ |
| 177 | #define CFG_OR2_PRELIM 0xfff06ff7 /* 1MB Compact Flash area*/ |
| 178 | |
| 179 | #define CFG_BR3_PRELIM 0xf8100801 /* port size 8bit */ |
| 180 | #define CFG_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/ |
| 181 | |
Kim Phillips | 53b3498 | 2007-08-21 17:00:17 -0500 | [diff] [blame] | 182 | #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ |
Jon Loeliger | 3e2d091 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 183 | #define PIXIS_BASE 0xf8100000 /* PIXIS registers */ |
| 184 | #define PIXIS_ID 0x0 /* Board ID at offset 0 */ |
| 185 | #define PIXIS_VER 0x1 /* Board version at offset 1 */ |
| 186 | #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ |
| 187 | #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ |
| 188 | #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch |
| 189 | * register */ |
| 190 | #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ |
| 191 | #define PIXIS_VCTL 0x10 /* VELA Control Register */ |
| 192 | #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ |
| 193 | #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ |
| 194 | #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ |
| 195 | #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ |
| 196 | #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ |
| 197 | #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ |
| 198 | #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ |
Jason Jin | f08899a | 2007-10-29 19:26:21 +0800 | [diff] [blame] | 199 | #define CFG_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/ |
Jon Loeliger | 3e2d091 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 200 | |
| 201 | |
| 202 | /* define to use L1 as initial stack */ |
Andy Fleming | b4b02c0 | 2008-07-14 20:29:07 -0500 | [diff] [blame] | 203 | #define CONFIG_L1_INIT_RAM |
| 204 | #define CFG_INIT_RAM_LOCK 1 |
| 205 | #define CFG_INIT_RAM_ADDR 0xf4010000 /* Initial L1 address */ |
| 206 | #define CFG_INIT_RAM_END 0x00004000 /* End of used area in RAM */ |
Jon Loeliger | 3e2d091 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 207 | |
Jon Loeliger | 3e2d091 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 208 | |
| 209 | #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ |
| 210 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
| 211 | #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
| 212 | |
| 213 | #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
Kumar Gala | 559e531 | 2008-07-14 14:07:03 -0500 | [diff] [blame] | 214 | #define CFG_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ |
Jon Loeliger | 3e2d091 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 215 | |
| 216 | /* Serial Port - controlled on board with jumper J8 |
| 217 | * open - index 2 |
| 218 | * shorted - index 1 |
| 219 | */ |
| 220 | #define CONFIG_CONS_INDEX 1 |
| 221 | #undef CONFIG_SERIAL_SOFTWARE_FIFO |
| 222 | #define CFG_NS16550 |
| 223 | #define CFG_NS16550_SERIAL |
| 224 | #define CFG_NS16550_REG_SIZE 1 |
| 225 | #define CFG_NS16550_CLK get_bus_freq(0) |
| 226 | |
| 227 | #define CFG_BAUDRATE_TABLE \ |
| 228 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
| 229 | |
| 230 | #define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) |
| 231 | #define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) |
| 232 | |
| 233 | /* Use the HUSH parser */ |
| 234 | #define CFG_HUSH_PARSER |
| 235 | #ifdef CFG_HUSH_PARSER |
| 236 | #define CFG_PROMPT_HUSH_PS2 "> " |
| 237 | #endif |
| 238 | |
| 239 | /* pass open firmware flat tree */ |
Kumar Gala | 67b349b | 2007-11-26 17:12:24 -0600 | [diff] [blame] | 240 | #define CONFIG_OF_LIBFDT 1 |
| 241 | #define CONFIG_OF_BOARD_SETUP 1 |
| 242 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 |
Jon Loeliger | 3e2d091 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 243 | |
Kumar Gala | 573ad30 | 2008-08-26 08:02:30 -0500 | [diff] [blame] | 244 | #define CFG_64BIT_STRTOUL 1 |
| 245 | #define CFG_64BIT_VSPRINTF 1 |
| 246 | |
Jon Loeliger | 3e2d091 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 247 | /* I2C */ |
| 248 | #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ |
| 249 | #define CONFIG_HARD_I2C /* I2C with hardware support */ |
| 250 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ |
| 251 | #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ |
| 252 | #define CFG_I2C_EEPROM_ADDR 0x57 |
| 253 | #define CFG_I2C_SLAVE 0x7F |
| 254 | #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ |
| 255 | #define CFG_I2C_OFFSET 0x3100 |
| 256 | |
| 257 | /* |
| 258 | * General PCI |
| 259 | * Memory space is mapped 1-1, but I/O space must start from 0. |
| 260 | */ |
| 261 | #define CFG_PCIE_PHYS 0x80000000 /* 1G PCIE TLB */ |
| 262 | #define CFG_PCI_PHYS 0xc0000000 /* 512M PCI TLB */ |
| 263 | |
| 264 | #define CFG_PCI1_MEM_BASE 0xc0000000 |
| 265 | #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE |
| 266 | #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ |
| 267 | #define CFG_PCI1_IO_BASE 0x00000000 |
| 268 | #define CFG_PCI1_IO_PHYS 0xe1000000 |
Kumar Gala | ace11d8 | 2007-08-16 15:05:04 -0500 | [diff] [blame] | 269 | #define CFG_PCI1_IO_SIZE 0x00010000 /* 64k */ |
Jon Loeliger | 3e2d091 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 270 | |
| 271 | /* PCI view of System Memory */ |
| 272 | #define CFG_PCI_MEMORY_BUS 0x00000000 |
| 273 | #define CFG_PCI_MEMORY_PHYS 0x00000000 |
| 274 | #define CFG_PCI_MEMORY_SIZE 0x80000000 |
| 275 | |
| 276 | /* controller 2, Slot 1, tgtid 1, Base address 9000 */ |
| 277 | #define CFG_PCIE2_MEM_BASE 0x80000000 |
| 278 | #define CFG_PCIE2_MEM_PHYS CFG_PCIE2_MEM_BASE |
| 279 | #define CFG_PCIE2_MEM_SIZE 0x20000000 /* 512M */ |
| 280 | #define CFG_PCIE2_IO_BASE 0x00000000 |
Kumar Gala | ace11d8 | 2007-08-16 15:05:04 -0500 | [diff] [blame] | 281 | #define CFG_PCIE2_IO_PHYS 0xe1010000 |
| 282 | #define CFG_PCIE2_IO_SIZE 0x00010000 /* 64k */ |
Jon Loeliger | 3e2d091 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 283 | |
| 284 | /* controller 1, Slot 2,tgtid 2, Base address a000 */ |
| 285 | #define CFG_PCIE1_MEM_BASE 0xa0000000 |
| 286 | #define CFG_PCIE1_MEM_PHYS CFG_PCIE1_MEM_BASE |
Kumar Gala | ace11d8 | 2007-08-16 15:05:04 -0500 | [diff] [blame] | 287 | #define CFG_PCIE1_MEM_SIZE 0x10000000 /* 256M */ |
| 288 | #define CFG_PCIE1_IO_BASE 0x00000000 |
| 289 | #define CFG_PCIE1_IO_PHYS 0xe1020000 |
| 290 | #define CFG_PCIE1_IO_SIZE 0x00010000 /* 64k */ |
Jon Loeliger | 3e2d091 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 291 | |
| 292 | /* controller 3, direct to uli, tgtid 3, Base address b000 */ |
| 293 | #define CFG_PCIE3_MEM_BASE 0xb0000000 |
| 294 | #define CFG_PCIE3_MEM_PHYS CFG_PCIE3_MEM_BASE |
Kumar Gala | ace11d8 | 2007-08-16 15:05:04 -0500 | [diff] [blame] | 295 | #define CFG_PCIE3_MEM_SIZE 0x00100000 /* 1M */ |
Jon Loeliger | 3e2d091 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 296 | #define CFG_PCIE3_IO_BASE 0x00000000 |
Kumar Gala | ace11d8 | 2007-08-16 15:05:04 -0500 | [diff] [blame] | 297 | #define CFG_PCIE3_IO_PHYS 0xb0100000 /* reuse mem LAW */ |
Jon Loeliger | 3e2d091 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 298 | #define CFG_PCIE3_IO_SIZE 0x00100000 /* 1M */ |
Kumar Gala | e1e870a | 2007-08-30 16:18:18 -0500 | [diff] [blame] | 299 | #define CFG_PCIE3_MEM_BASE2 0xb0200000 |
| 300 | #define CFG_PCIE3_MEM_PHYS2 CFG_PCIE3_MEM_BASE2 |
| 301 | #define CFG_PCIE3_MEM_SIZE2 0x00200000 /* 1M */ |
Jon Loeliger | 3e2d091 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 302 | |
| 303 | #if defined(CONFIG_PCI) |
| 304 | |
Kumar Gala | 559e531 | 2008-07-14 14:07:03 -0500 | [diff] [blame] | 305 | /*PCIE video card used*/ |
| 306 | #define VIDEO_IO_OFFSET CFG_PCIE2_IO_PHYS |
| 307 | |
| 308 | /*PCI video card used*/ |
| 309 | /*#define VIDEO_IO_OFFSET CFG_PCI1_IO_PHYS*/ |
| 310 | |
| 311 | /* video */ |
| 312 | #define CONFIG_VIDEO |
| 313 | |
| 314 | #if defined(CONFIG_VIDEO) |
| 315 | #define CONFIG_BIOSEMU |
| 316 | #define CONFIG_CFB_CONSOLE |
| 317 | #define CONFIG_VIDEO_SW_CURSOR |
| 318 | #define CONFIG_VGA_AS_SINGLE_DEVICE |
| 319 | #define CONFIG_ATI_RADEON_FB |
| 320 | #define CONFIG_VIDEO_LOGO |
| 321 | /*#define CONFIG_CONSOLE_CURSOR*/ |
| 322 | #define CFG_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET |
| 323 | #endif |
| 324 | |
Jon Loeliger | 3e2d091 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 325 | #define CONFIG_NET_MULTI |
| 326 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
| 327 | |
| 328 | #undef CONFIG_EEPRO100 |
| 329 | #undef CONFIG_TULIP |
| 330 | #define CONFIG_RTL8139 |
| 331 | |
| 332 | #ifdef CONFIG_RTL8139 |
| 333 | /* This macro is used by RTL8139 but not defined in PPC architecture */ |
| 334 | #define KSEG1ADDR(x) (x) |
| 335 | #define _IO_BASE 0x00000000 |
| 336 | #endif |
| 337 | |
| 338 | #ifndef CONFIG_PCI_PNP |
| 339 | #define PCI_ENET0_IOADDR CFG_PCI1_IO_BASE |
| 340 | #define PCI_ENET0_MEMADDR CFG_PCI1_IO_BASE |
| 341 | #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ |
| 342 | #endif |
| 343 | |
| 344 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
| 345 | #define CONFIG_DOS_PARTITION |
| 346 | #define CONFIG_SCSI_AHCI |
| 347 | |
| 348 | #ifdef CONFIG_SCSI_AHCI |
| 349 | #define CONFIG_SATA_ULI5288 |
| 350 | #define CFG_SCSI_MAX_SCSI_ID 4 |
| 351 | #define CFG_SCSI_MAX_LUN 1 |
Ed Swarthout | 52b9852 | 2007-07-27 01:50:51 -0500 | [diff] [blame] | 352 | #define CFG_SCSI_MAX_DEVICE (CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN) |
Jon Loeliger | 3e2d091 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 353 | #define CFG_SCSI_MAXDEVICE CFG_SCSI_MAX_DEVICE |
| 354 | #endif /* SCSCI */ |
| 355 | |
| 356 | #endif /* CONFIG_PCI */ |
| 357 | |
| 358 | |
| 359 | #if defined(CONFIG_TSEC_ENET) |
| 360 | |
| 361 | #ifndef CONFIG_NET_MULTI |
Ed Swarthout | 52b9852 | 2007-07-27 01:50:51 -0500 | [diff] [blame] | 362 | #define CONFIG_NET_MULTI 1 |
Jon Loeliger | 3e2d091 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 363 | #endif |
| 364 | |
| 365 | #define CONFIG_MII 1 /* MII PHY management */ |
| 366 | #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ |
Kim Phillips | 177e58f | 2007-05-16 16:52:19 -0500 | [diff] [blame] | 367 | #define CONFIG_TSEC1 1 |
| 368 | #define CONFIG_TSEC1_NAME "eTSEC1" |
| 369 | #define CONFIG_TSEC3 1 |
| 370 | #define CONFIG_TSEC3_NAME "eTSEC3" |
Ed Swarthout | 52b9852 | 2007-07-27 01:50:51 -0500 | [diff] [blame] | 371 | |
Jon Loeliger | 3e2d091 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 372 | #define TSEC1_PHY_ADDR 0 |
| 373 | #define TSEC3_PHY_ADDR 1 |
| 374 | |
Andy Fleming | 09b88df | 2007-08-15 20:03:25 -0500 | [diff] [blame] | 375 | #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) |
| 376 | #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) |
| 377 | |
Jon Loeliger | 3e2d091 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 378 | #define TSEC1_PHYIDX 0 |
| 379 | #define TSEC3_PHYIDX 0 |
| 380 | |
| 381 | #define CONFIG_ETHPRIME "eTSEC1" |
| 382 | |
| 383 | #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ |
Jon Loeliger | 3e2d091 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 384 | #endif /* CONFIG_TSEC_ENET */ |
| 385 | |
| 386 | /* |
| 387 | * Environment |
| 388 | */ |
| 389 | #define CFG_ENV_IS_IN_FLASH 1 |
| 390 | #if CFG_MONITOR_BASE > 0xfff80000 |
| 391 | #define CFG_ENV_ADDR 0xfff80000 |
| 392 | #else |
Kumar Gala | 559e531 | 2008-07-14 14:07:03 -0500 | [diff] [blame] | 393 | #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x70000) |
Jon Loeliger | 3e2d091 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 394 | #endif |
| 395 | #define CFG_ENV_SIZE 0x2000 |
| 396 | #define CFG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) */ |
| 397 | |
| 398 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
| 399 | #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
| 400 | |
Jon Loeliger | e63319f | 2007-06-13 13:22:08 -0500 | [diff] [blame] | 401 | /* |
Jon Loeliger | ed26c74 | 2007-07-10 09:10:49 -0500 | [diff] [blame] | 402 | * BOOTP options |
| 403 | */ |
| 404 | #define CONFIG_BOOTP_BOOTFILESIZE |
| 405 | #define CONFIG_BOOTP_BOOTPATH |
| 406 | #define CONFIG_BOOTP_GATEWAY |
| 407 | #define CONFIG_BOOTP_HOSTNAME |
| 408 | |
| 409 | |
| 410 | /* |
Jon Loeliger | e63319f | 2007-06-13 13:22:08 -0500 | [diff] [blame] | 411 | * Command line configuration. |
| 412 | */ |
| 413 | #include <config_cmd_default.h> |
| 414 | |
| 415 | #define CONFIG_CMD_PING |
| 416 | #define CONFIG_CMD_I2C |
| 417 | #define CONFIG_CMD_MII |
Kumar Gala | 260fac3 | 2007-12-07 12:04:30 -0600 | [diff] [blame] | 418 | #define CONFIG_CMD_ELF |
Jon Loeliger | e63319f | 2007-06-13 13:22:08 -0500 | [diff] [blame] | 419 | |
Jon Loeliger | 3e2d091 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 420 | #if defined(CONFIG_PCI) |
Jon Loeliger | e63319f | 2007-06-13 13:22:08 -0500 | [diff] [blame] | 421 | #define CONFIG_CMD_PCI |
| 422 | #define CONFIG_CMD_BEDBUG |
| 423 | #define CONFIG_CMD_NET |
Ed Swarthout | 52b9852 | 2007-07-27 01:50:51 -0500 | [diff] [blame] | 424 | #define CONFIG_CMD_SCSI |
| 425 | #define CONFIG_CMD_EXT2 |
Jon Loeliger | 3e2d091 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 426 | #endif |
Jon Loeliger | e63319f | 2007-06-13 13:22:08 -0500 | [diff] [blame] | 427 | |
Jon Loeliger | 3e2d091 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 428 | |
| 429 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
| 430 | |
| 431 | /* |
| 432 | * Miscellaneous configurable options |
| 433 | */ |
| 434 | #define CFG_LONGHELP /* undef to save memory */ |
Kumar Gala | 937176b | 2007-11-27 22:42:34 -0600 | [diff] [blame] | 435 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ |
Jon Loeliger | 3e2d091 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 436 | #define CFG_LOAD_ADDR 0x2000000 /* default load address */ |
| 437 | #define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
Jon Loeliger | e63319f | 2007-06-13 13:22:08 -0500 | [diff] [blame] | 438 | #if defined(CONFIG_CMD_KGDB) |
Jon Loeliger | 3e2d091 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 439 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
| 440 | #else |
| 441 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
| 442 | #endif |
| 443 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
| 444 | #define CFG_MAXARGS 16 /* max number of command args */ |
| 445 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
| 446 | #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ |
| 447 | |
| 448 | /* |
| 449 | * For booting Linux, the board info and command line data |
| 450 | * have to be in the first 8 MB of memory, since this is |
| 451 | * the maximum mapped by the Linux kernel during initialization. |
| 452 | */ |
Ed Swarthout | 52b9852 | 2007-07-27 01:50:51 -0500 | [diff] [blame] | 453 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ |
Jon Loeliger | 3e2d091 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 454 | |
Jon Loeliger | 3e2d091 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 455 | /* |
| 456 | * Internal Definitions |
| 457 | * |
| 458 | * Boot Flags |
| 459 | */ |
| 460 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
| 461 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ |
| 462 | |
Jon Loeliger | e63319f | 2007-06-13 13:22:08 -0500 | [diff] [blame] | 463 | #if defined(CONFIG_CMD_KGDB) |
Jon Loeliger | 3e2d091 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 464 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
| 465 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ |
| 466 | #endif |
| 467 | |
| 468 | /* |
| 469 | * Environment Configuration |
| 470 | */ |
| 471 | |
| 472 | /* The mac addresses for all ethernet interface */ |
| 473 | #if defined(CONFIG_TSEC_ENET) |
Kumar Gala | 0eb6191 | 2007-08-16 11:01:21 -0500 | [diff] [blame] | 474 | #define CONFIG_HAS_ETH0 |
Jon Loeliger | 3e2d091 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 475 | #define CONFIG_ETHADDR 00:E0:0C:02:00:FD |
| 476 | #define CONFIG_HAS_ETH1 |
| 477 | #define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD |
Jon Loeliger | 3e2d091 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 478 | #endif |
| 479 | |
| 480 | #define CONFIG_IPADDR 192.168.1.251 |
| 481 | |
| 482 | #define CONFIG_HOSTNAME 8544ds_unknown |
| 483 | #define CONFIG_ROOTPATH /nfs/mpc85xx |
Ed Swarthout | 52b9852 | 2007-07-27 01:50:51 -0500 | [diff] [blame] | 484 | #define CONFIG_BOOTFILE 8544ds/uImage.uboot |
| 485 | #define CONFIG_UBOOTPATH 8544ds/u-boot.bin /* TFTP server */ |
Jon Loeliger | 3e2d091 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 486 | |
Kumar Gala | 937176b | 2007-11-27 22:42:34 -0600 | [diff] [blame] | 487 | #define CONFIG_SERVERIP 192.168.1.1 |
| 488 | #define CONFIG_GATEWAYIP 192.168.1.1 |
Jon Loeliger | 3e2d091 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 489 | #define CONFIG_NETMASK 255.255.0.0 |
| 490 | |
| 491 | #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ |
| 492 | |
| 493 | #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ |
Ed Swarthout | 52b9852 | 2007-07-27 01:50:51 -0500 | [diff] [blame] | 494 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ |
Jon Loeliger | 3e2d091 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 495 | |
| 496 | #define CONFIG_BAUDRATE 115200 |
| 497 | |
Ed Swarthout | 52b9852 | 2007-07-27 01:50:51 -0500 | [diff] [blame] | 498 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 499 | "netdev=eth0\0" \ |
| 500 | "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ |
| 501 | "tftpflash=tftpboot $loadaddr $uboot; " \ |
| 502 | "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ |
| 503 | "erase " MK_STR(TEXT_BASE) " +$filesize; " \ |
| 504 | "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ |
| 505 | "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ |
| 506 | "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ |
Jon Loeliger | 3e2d091 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 507 | "consoledev=ttyS0\0" \ |
| 508 | "ramdiskaddr=2000000\0" \ |
Ed Swarthout | 52b9852 | 2007-07-27 01:50:51 -0500 | [diff] [blame] | 509 | "ramdiskfile=8544ds/ramdisk.uboot\0" \ |
Kumar Gala | 937176b | 2007-11-27 22:42:34 -0600 | [diff] [blame] | 510 | "fdtaddr=c00000\0" \ |
| 511 | "fdtfile=8544ds/mpc8544ds.dtb\0" \ |
| 512 | "bdev=sda3\0" |
Jon Loeliger | 3e2d091 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 513 | |
| 514 | #define CONFIG_NFSBOOTCOMMAND \ |
| 515 | "setenv bootargs root=/dev/nfs rw " \ |
| 516 | "nfsroot=$serverip:$rootpath " \ |
| 517 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ |
| 518 | "console=$consoledev,$baudrate $othbootargs;" \ |
| 519 | "tftp $loadaddr $bootfile;" \ |
Kumar Gala | 937176b | 2007-11-27 22:42:34 -0600 | [diff] [blame] | 520 | "tftp $fdtaddr $fdtfile;" \ |
| 521 | "bootm $loadaddr - $fdtaddr" |
Jon Loeliger | 3e2d091 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 522 | |
Ed Swarthout | 52b9852 | 2007-07-27 01:50:51 -0500 | [diff] [blame] | 523 | #define CONFIG_RAMBOOTCOMMAND \ |
Jon Loeliger | 3e2d091 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 524 | "setenv bootargs root=/dev/ram rw " \ |
| 525 | "console=$consoledev,$baudrate $othbootargs;" \ |
| 526 | "tftp $ramdiskaddr $ramdiskfile;" \ |
| 527 | "tftp $loadaddr $bootfile;" \ |
Kumar Gala | 937176b | 2007-11-27 22:42:34 -0600 | [diff] [blame] | 528 | "tftp $fdtaddr $fdtfile;" \ |
| 529 | "bootm $loadaddr $ramdiskaddr $fdtaddr" |
Jon Loeliger | 3e2d091 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 530 | |
Ed Swarthout | 52b9852 | 2007-07-27 01:50:51 -0500 | [diff] [blame] | 531 | #define CONFIG_BOOTCOMMAND \ |
| 532 | "setenv bootargs root=/dev/$bdev rw " \ |
Jon Loeliger | 3e2d091 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 533 | "console=$consoledev,$baudrate $othbootargs;" \ |
| 534 | "tftp $loadaddr $bootfile;" \ |
Kumar Gala | 937176b | 2007-11-27 22:42:34 -0600 | [diff] [blame] | 535 | "tftp $fdtaddr $fdtfile;" \ |
| 536 | "bootm $loadaddr - $fdtaddr" |
Jon Loeliger | 3e2d091 | 2007-04-11 16:50:57 -0500 | [diff] [blame] | 537 | |
| 538 | #endif /* __CONFIG_H */ |