| Wolfgang Denk | 97caf67 | 2006-03-12 02:12:27 +0100 | [diff] [blame] | 1 | /* |
| 2 | * defBF533_extn.h |
| 3 | * |
| 4 | * This file is subject to the terms and conditions of the GNU Public |
| 5 | * License. See the file "COPYING" in the main directory of this archive |
| 6 | * for more details. |
| 7 | * |
| 8 | * Non-GPL License also available as part of VisualDSP++ |
| 9 | * |
| 10 | * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html |
| 11 | * |
| 12 | * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved |
| 13 | * |
| 14 | * This file under source code control, please send bugs or changes to: |
| 15 | * dsptools.support@analog.com |
| 16 | * |
| 17 | */ |
| 18 | |
| 19 | #ifndef _DEF_BF533_EXTN_H |
| 20 | #define _DEF_BF533_EXTN_H |
| 21 | |
| Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 22 | /* define macro for offset */ |
| 23 | #define OFFSET_( x ) ((x) & 0x0000FFFF) |
| Wolfgang Denk | 97caf67 | 2006-03-12 02:12:27 +0100 | [diff] [blame] | 24 | /* Delay inserted for PLL transition */ |
| Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 25 | #define PLL_DELAY 0x1000 |
| Wolfgang Denk | 97caf67 | 2006-03-12 02:12:27 +0100 | [diff] [blame] | 26 | |
| 27 | #define L1_ISRAM 0xFFA00000 |
| 28 | #define L1_ISRAM_END 0xFFA10000 |
| 29 | #define DATA_BANKA_SRAM 0xFF800000 |
| 30 | #define DATA_BANKA_SRAM_END 0xFF808000 |
| 31 | #define DATA_BANKB_SRAM 0xFF900000 |
| 32 | #define DATA_BANKB_SRAM_END 0xFF908000 |
| 33 | #define SYSMMR_BASE 0xFFC00000 |
| 34 | #define WDSIZE16 0x00000004 |
| 35 | |
| 36 | /* Event Vector Table Address */ |
| 37 | #define EVT_EMULATION_ADDR 0xffe02000 |
| 38 | #define EVT_RESET_ADDR 0xffe02004 |
| 39 | #define EVT_NMI_ADDR 0xffe02008 |
| 40 | #define EVT_EXCEPTION_ADDR 0xffe0200c |
| 41 | #define EVT_GLOBAL_INT_ENB_ADDR 0xffe02010 |
| 42 | #define EVT_HARDWARE_ERROR_ADDR 0xffe02014 |
| 43 | #define EVT_TIMER_ADDR 0xffe02018 |
| 44 | #define EVT_IVG7_ADDR 0xffe0201c |
| 45 | #define EVT_IVG8_ADDR 0xffe02020 |
| 46 | #define EVT_IVG9_ADDR 0xffe02024 |
| 47 | #define EVT_IVG10_ADDR 0xffe02028 |
| 48 | #define EVT_IVG11_ADDR 0xffe0202c |
| 49 | #define EVT_IVG12_ADDR 0xffe02030 |
| 50 | #define EVT_IVG13_ADDR 0xffe02034 |
| 51 | #define EVT_IVG14_ADDR 0xffe02038 |
| 52 | #define EVT_IVG15_ADDR 0xffe0203c |
| 53 | #define EVT_OVERRIDE_ADDR 0xffe02100 |
| 54 | |
| 55 | /* IMASK Bit values */ |
| 56 | #define IVG15_POS 0x00008000 |
| 57 | #define IVG14_POS 0x00004000 |
| 58 | #define IVG13_POS 0x00002000 |
| 59 | #define IVG12_POS 0x00001000 |
| 60 | #define IVG11_POS 0x00000800 |
| 61 | #define IVG10_POS 0x00000400 |
| 62 | #define IVG9_POS 0x00000200 |
| 63 | #define IVG8_POS 0x00000100 |
| 64 | #define IVG7_POS 0x00000080 |
| 65 | #define IVGTMR_POS 0x00000040 |
| 66 | #define IVGHW_POS 0x00000020 |
| 67 | |
| 68 | #define WDOG_TMR_DISABLE (0xAD << 4) |
| 69 | #define ICTL_RST 0x00000000 |
| 70 | #define ICTL_NMI 0x00000002 |
| 71 | #define ICTL_GP 0x00000004 |
| 72 | #define ICTL_DISABLE 0x00000003 |
| 73 | |
| 74 | /* Watch Dog timer values setup */ |
| 75 | #define WATCHDOG_DISABLE WDOG_TMR_DISABLE | ICTL_DISABLE |
| 76 | |
| 77 | #endif /* _DEF_BF533_EXTN_H */ |