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git01.mediatek.com / filogic / uboot / 33279fe3378c513759596bc1344b0070a1c492bc / . / drivers / misc / ns87308.c
blob: 8a92ccb884b752905098d9db1e472f585e775999 [file] [log] [blame]
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]1/*
2 * (C) Copyright 2000
3 * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
4 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]5 * SPDX-License-Identifier: GPL-2.0+
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]6 */
7
8#include <config.h>
9
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]10#include <ns87308.h>
11
12void initialise_ns87308 (void)
13{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]14#ifdef CONFIG_SYS_NS87308_PS2MOD
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]15 unsigned char data;
16
17 /*
18 * Switch floppy drive to PS/2 mode.
19 */
20 read_pnp_config(SUPOERIO_CONF1, &data);
21 data &= 0xFB;
22 write_pnp_config(SUPOERIO_CONF1, data);
23#endif
24
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]25#if (CONFIG_SYS_NS87308_DEVS & CONFIG_SYS_NS87308_KBC1)
26 PNP_SET_DEVICE_BASE(LDEV_KBC1, CONFIG_SYS_NS87308_KBC1_BASE);
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]27 write_pnp_config(LUN_CONFIG_REG, 0);
28 write_pnp_config(CBASE_HIGH, 0x00);
29 write_pnp_config(CBASE_LOW, 0x64);
30#endif
31
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]32#if (CONFIG_SYS_NS87308_DEVS & CONFIG_SYS_NS87308_MOUSE)
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]33 PNP_ACTIVATE_DEVICE(LDEV_MOUSE);
34#endif
35
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]36#if (CONFIG_SYS_NS87308_DEVS & CONFIG_SYS_NS87308_RTC_APC)
37 PNP_SET_DEVICE_BASE(LDEV_RTC_APC, CONFIG_SYS_NS87308_RTC_BASE);
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]38#endif
39
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]40#if (CONFIG_SYS_NS87308_DEVS & CONFIG_SYS_NS87308_FDC)
41 PNP_SET_DEVICE_BASE(LDEV_FDC, CONFIG_SYS_NS87308_FDC_BASE);
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]42 write_pnp_config(LUN_CONFIG_REG, 0x40);
43#endif
44
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]45#if (CONFIG_SYS_NS87308_DEVS & CONFIG_SYS_NS87308_RARP)
46 PNP_SET_DEVICE_BASE(LDEV_PARP, CONFIG_SYS_NS87308_LPT_BASE);
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]47#endif
48
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]49#if (CONFIG_SYS_NS87308_DEVS & CONFIG_SYS_NS87308_UART1)
50 PNP_SET_DEVICE_BASE(LDEV_UART1, CONFIG_SYS_NS87308_UART1_BASE);
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]51#endif
52
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]53#if (CONFIG_SYS_NS87308_DEVS & CONFIG_SYS_NS87308_UART2)
54 PNP_SET_DEVICE_BASE(LDEV_UART2, CONFIG_SYS_NS87308_UART2_BASE);
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]55#endif
56
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]57#if (CONFIG_SYS_NS87308_DEVS & CONFIG_SYS_NS87308_GPIO)
58 PNP_SET_DEVICE_BASE(LDEV_GPIO, CONFIG_SYS_NS87308_GPIO_BASE);
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]59#endif
60
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]61#if (CONFIG_SYS_NS87308_DEVS & CONFIG_SYS_NS87308_POWRMAN)
62#ifndef CONFIG_SYS_NS87308_PWMAN_BASE
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]63 PNP_ACTIVATE_DEVICE(LDEV_POWRMAN);
64#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]65 PNP_SET_DEVICE_BASE(LDEV_POWRMAN, CONFIG_SYS_NS87308_PWMAN_BASE);
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]66
67 /*
68 * Enable all units
69 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]70 write_pm_reg(CONFIG_SYS_NS87308_PWMAN_BASE, PWM_FER1, 0x7d);
71 write_pm_reg(CONFIG_SYS_NS87308_PWMAN_BASE, PWM_FER2, 0x87);
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]72
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]73#ifdef CONFIG_SYS_NS87308_PMC1
74 write_pm_reg(CONFIG_SYS_NS87308_PWMAN_BASE, PWM_PMC1, CONFIG_SYS_NS87308_PMC1);
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]75#endif
76
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]77#ifdef CONFIG_SYS_NS87308_PMC2
78 write_pm_reg(CONFIG_SYS_NS87308_PWMAN_BASE, PWM_PMC2, CONFIG_SYS_NS87308_PMC2);
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]79#endif
80
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]81#ifdef CONFIG_SYS_NS87308_PMC3
82 write_pm_reg(CONFIG_SYS_NS87308_PWMAN_BASE, PWM_PMC3, CONFIG_SYS_NS87308_PMC3);
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]83#endif
84#endif
85#endif
86
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]87#ifdef CONFIG_SYS_NS87308_CS0_BASE
88 PNP_PGCS_CSLINE_BASE(0, CONFIG_SYS_NS87308_CS0_BASE);
89 PNP_PGCS_CSLINE_CONF(0, CONFIG_SYS_NS87308_CS0_CONF);
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]90#endif
91
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]92#ifdef CONFIG_SYS_NS87308_CS1_BASE
93 PNP_PGCS_CSLINE_BASE(1, CONFIG_SYS_NS87308_CS1_BASE);
94 PNP_PGCS_CSLINE_CONF(1, CONFIG_SYS_NS87308_CS1_CONF);
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]95#endif
96
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]97#ifdef CONFIG_SYS_NS87308_CS2_BASE
98 PNP_PGCS_CSLINE_BASE(2, CONFIG_SYS_NS87308_CS2_BASE);
99 PNP_PGCS_CSLINE_CONF(2, CONFIG_SYS_NS87308_CS2_CONF);
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]100#endif
101}