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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Soren Brinkmann102ad002013-11-21 13:38:54 -08002/*
3 * Copyright (C) 2013 Soren Brinkmann <soren.brinkmann@xilinx.com>
4 * Copyright (C) 2013 Xilinx, Inc. All rights reserved.
Soren Brinkmann102ad002013-11-21 13:38:54 -08005 */
Stefan Herbrechtsmeiere67c6c42017-01-17 16:27:30 +01006#include <clk.h>
Soren Brinkmann102ad002013-11-21 13:38:54 -08007#include <common.h>
Stefan Herbrechtsmeiere67c6c42017-01-17 16:27:30 +01008#include <dm.h>
Simon Glass97589732020-05-10 11:40:02 -06009#include <init.h>
Simon Glass9bc15642020-02-03 07:36:16 -070010#include <malloc.h>
Soren Brinkmann102ad002013-11-21 13:38:54 -080011#include <asm/arch/clk.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060012#include <asm/global_data.h>
Soren Brinkmann102ad002013-11-21 13:38:54 -080013
Soren Brinkmann102ad002013-11-21 13:38:54 -080014DECLARE_GLOBAL_DATA_PTR;
15
Stefan Herbrechtsmeiere0862e22017-01-17 16:27:27 +010016static const char * const clk_names[clk_max] = {
17 "armpll", "ddrpll", "iopll",
18 "cpu_6or4x", "cpu_3or2x", "cpu_2x", "cpu_1x",
19 "ddr2x", "ddr3x", "dci",
20 "lqspi", "smc", "pcap", "gem0", "gem1",
21 "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
22 "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", "dma",
23 "usb0_aper", "usb1_aper", "gem0_aper", "gem1_aper",
24 "sdio0_aper", "sdio1_aper", "spi0_aper", "spi1_aper",
25 "can0_aper", "can1_aper", "i2c0_aper", "i2c1_aper",
26 "uart0_aper", "uart1_aper", "gpio_aper", "lqspi_aper",
27 "smc_aper", "swdt", "dbg_trc", "dbg_apb"
28};
29
Soren Brinkmann102ad002013-11-21 13:38:54 -080030/**
Stefan Herbrechtsmeiere67c6c42017-01-17 16:27:30 +010031 * set_cpu_clk_info() - Setup clock information
Soren Brinkmann102ad002013-11-21 13:38:54 -080032 *
Stefan Herbrechtsmeiere67c6c42017-01-17 16:27:30 +010033 * This function is called from common code after relocation and sets up the
34 * clock information.
Soren Brinkmann102ad002013-11-21 13:38:54 -080035 */
Stefan Herbrechtsmeiere67c6c42017-01-17 16:27:30 +010036int set_cpu_clk_info(void)
Soren Brinkmann102ad002013-11-21 13:38:54 -080037{
Stefan Herbrechtsmeiere67c6c42017-01-17 16:27:30 +010038 struct clk clk;
39 struct udevice *dev;
40 ulong rate;
41 int i, ret;
Soren Brinkmann102ad002013-11-21 13:38:54 -080042
Stefan Herbrechtsmeiere67c6c42017-01-17 16:27:30 +010043 ret = uclass_get_device_by_driver(UCLASS_CLK,
Simon Glass65130cd2020-12-28 20:34:56 -070044 DM_DRIVER_GET(zynq_clk), &dev);
Stefan Herbrechtsmeiere67c6c42017-01-17 16:27:30 +010045 if (ret)
46 return ret;
Soren Brinkmann102ad002013-11-21 13:38:54 -080047
Stefan Herbrechtsmeiere67c6c42017-01-17 16:27:30 +010048 for (i = 0; i < 2; i++) {
49 clk.id = i ? ddr3x_clk : cpu_6or4x_clk;
50 ret = clk_request(dev, &clk);
51 if (ret < 0)
52 return ret;
Soren Brinkmann102ad002013-11-21 13:38:54 -080053
Stefan Herbrechtsmeiere67c6c42017-01-17 16:27:30 +010054 rate = clk_get_rate(&clk) / 1000000;
Stefan Herbrechtsmeier10ff2882022-08-05 08:16:28 +020055 if (i) {
Stefan Herbrechtsmeiere67c6c42017-01-17 16:27:30 +010056 gd->bd->bi_ddr_freq = rate;
Stefan Herbrechtsmeier10ff2882022-08-05 08:16:28 +020057 } else {
Stefan Herbrechtsmeiere67c6c42017-01-17 16:27:30 +010058 gd->bd->bi_arm_freq = rate;
Stefan Herbrechtsmeier10ff2882022-08-05 08:16:28 +020059 gd->cpu_clk = clk_get_rate(&clk);
60 }
Soren Brinkmann102ad002013-11-21 13:38:54 -080061
Stefan Herbrechtsmeiere67c6c42017-01-17 16:27:30 +010062 clk_free(&clk);
Soren Brinkmann102ad002013-11-21 13:38:54 -080063 }
Michal Simek0ec9d232014-01-20 11:05:37 +010064 gd->bd->bi_dsp_freq = 0;
65
Soren Brinkmann102ad002013-11-21 13:38:54 -080066 return 0;
67}
68
69/**
Soren Brinkmann37523442013-11-21 13:39:03 -080070 * soc_clk_dump() - Print clock frequencies
71 * Returns zero on success
72 *
73 * Implementation for the clk dump command.
74 */
75int soc_clk_dump(void)
76{
Stefan Herbrechtsmeiere67c6c42017-01-17 16:27:30 +010077 struct udevice *dev;
78 int i, ret;
79
80 ret = uclass_get_device_by_driver(UCLASS_CLK,
Simon Glass65130cd2020-12-28 20:34:56 -070081 DM_DRIVER_GET(zynq_clk), &dev);
Stefan Herbrechtsmeiere67c6c42017-01-17 16:27:30 +010082 if (ret)
83 return ret;
Soren Brinkmann37523442013-11-21 13:39:03 -080084
85 printf("clk\t\tfrequency\n");
86 for (i = 0; i < clk_max; i++) {
Stefan Herbrechtsmeierf50bcc82017-01-17 16:27:28 +010087 const char *name = clk_names[i];
Stefan Herbrechtsmeiere67c6c42017-01-17 16:27:30 +010088 if (name) {
89 struct clk clk;
90 unsigned long rate;
91
92 clk.id = i;
93 ret = clk_request(dev, &clk);
94 if (ret < 0)
95 return ret;
96
97 rate = clk_get_rate(&clk);
98
99 clk_free(&clk);
100
Michal Simek23728722018-02-23 13:39:37 +0100101 if ((rate == (unsigned long)-ENOSYS) ||
102 (rate == (unsigned long)-ENXIO))
Stefan Herbrechtsmeiere67c6c42017-01-17 16:27:30 +0100103 printf("%10s%20s\n", name, "unknown");
104 else
105 printf("%10s%20lu\n", name, rate);
106 }
Soren Brinkmann37523442013-11-21 13:39:03 -0800107 }
108
109 return 0;
110}