blob: a53e1632f6cff5bcc4ac8e9a6cade4ea89343480 [file] [log] [blame]
Chia-Wei, Wang8f7f4902020-12-14 13:54:28 +08001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (c) Aspeed Technology Inc.
4 */
5#include <common.h>
6#include <dm.h>
7#include <ram.h>
8#include <timer.h>
9#include <asm/io.h>
10#include <asm/arch/timer.h>
11#include <linux/bitops.h>
12#include <linux/err.h>
13#include <dm/uclass.h>
14#include <asm/arch/scu_ast2600.h>
15
16DECLARE_GLOBAL_DATA_PTR;
17
18/* Memory Control registers */
19#define MCR_BASE 0x1e6e0000
20#define MCR_CONF (MCR_BASE + 0x004)
21
22/* bit fields of MCR_CONF */
23#define MCR_CONF_ECC_EN BIT(7)
24#define MCR_CONF_VGA_MEMSZ_MASK GENMASK(3, 2)
25#define MCR_CONF_VGA_MEMSZ_SHIFT 2
26#define MCR_CONF_MEMSZ_MASK GENMASK(1, 0)
27#define MCR_CONF_MEMSZ_SHIFT 0
28
29int dram_init(void)
30{
31 int ret;
32 struct udevice *dev;
33 struct ram_info ram;
34
35 ret = uclass_get_device(UCLASS_RAM, 0, &dev);
36 if (ret) {
37 debug("cannot get DRAM driver\n");
38 return ret;
39 }
40
41 ret = ram_get_info(dev, &ram);
42 if (ret) {
43 debug("cannot get DRAM information\n");
44 return ret;
45 }
46
47 gd->ram_size = ram.size;
48 return 0;
49}
50
51int board_init(void)
52{
53 int i = 0, rc;
54 struct udevice *dev;
55
56 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
57
58 while (1) {
59 rc = uclass_get_device(UCLASS_MISC, i++, &dev);
60 if (rc)
61 break;
62 }
63
64 return 0;
65}
66
67void board_add_ram_info(int use_default)
68{
69 int rc;
70 uint32_t conf;
71 uint32_t ecc, act_size, vga_rsvd;
72 struct udevice *scu_dev;
73 struct ast2600_scu *scu;
74
75 rc = uclass_get_device_by_driver(UCLASS_CLK,
76 DM_DRIVER_GET(aspeed_ast2600_scu), &scu_dev);
77 if (rc) {
78 debug("%s: cannot find SCU device, rc=%d\n", __func__, rc);
79 return;
80 }
81
82 scu = devfdt_get_addr_ptr(scu_dev);
83 if (IS_ERR_OR_NULL(scu)) {
84 debug("%s: cannot get SCU address pointer\n", __func__);
85 return;
86 }
87
88 conf = readl(MCR_CONF);
89
90 ecc = conf & MCR_CONF_ECC_EN;
91 act_size = 0x100 << ((conf & MCR_CONF_MEMSZ_MASK) >> MCR_CONF_MEMSZ_SHIFT);
92 vga_rsvd = 0x8 << ((conf & MCR_CONF_VGA_MEMSZ_MASK) >> MCR_CONF_VGA_MEMSZ_SHIFT);
93
94 /* no VGA reservation if efuse VGA disable bit is set */
95 if (readl(scu->efuse) & SCU_EFUSE_DIS_VGA)
96 vga_rsvd = 0;
97
98 printf(" (capacity:%d MiB, VGA:%d MiB), ECC %s", act_size,
99 vga_rsvd, (ecc) ? "on" : "off");
100}
101
102void enable_caches(void)
103{
104 /* get rid of the warning message */
105}