Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Marek Vasut | c140e98 | 2011-11-08 23:18:08 +0000 | [diff] [blame] | 2 | /* |
| 3 | * Freescale i.MX28 timer driver |
| 4 | * |
| 5 | * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> |
| 6 | * on behalf of DENX Software Engineering GmbH |
| 7 | * |
| 8 | * Based on code from LTIB: |
| 9 | * (C) Copyright 2009-2010 Freescale Semiconductor, Inc. |
Marek Vasut | c140e98 | 2011-11-08 23:18:08 +0000 | [diff] [blame] | 10 | */ |
| 11 | |
| 12 | #include <common.h> |
Simon Glass | 9758973 | 2020-05-10 11:40:02 -0600 | [diff] [blame] | 13 | #include <init.h> |
Simon Glass | 495a5dc | 2019-11-14 12:57:30 -0700 | [diff] [blame] | 14 | #include <time.h> |
Marek Vasut | c140e98 | 2011-11-08 23:18:08 +0000 | [diff] [blame] | 15 | #include <asm/io.h> |
| 16 | #include <asm/arch/imx-regs.h> |
| 17 | #include <asm/arch/sys_proto.h> |
Simon Glass | dbd7954 | 2020-05-10 11:40:11 -0600 | [diff] [blame] | 18 | #include <linux/delay.h> |
Marek Vasut | c140e98 | 2011-11-08 23:18:08 +0000 | [diff] [blame] | 19 | |
| 20 | /* Maximum fixed count */ |
Fadil Berisha | d608f6e | 2013-02-27 17:00:07 +0000 | [diff] [blame] | 21 | #if defined(CONFIG_MX23) |
| 22 | #define TIMER_LOAD_VAL 0xffff |
| 23 | #elif defined(CONFIG_MX28) |
| 24 | #define TIMER_LOAD_VAL 0xffffffff |
| 25 | #endif |
Marek Vasut | c140e98 | 2011-11-08 23:18:08 +0000 | [diff] [blame] | 26 | |
| 27 | DECLARE_GLOBAL_DATA_PTR; |
| 28 | |
Simon Glass | 2655ee1 | 2012-12-13 20:48:34 +0000 | [diff] [blame] | 29 | #define timestamp (gd->arch.tbl) |
Simon Glass | a848da5 | 2012-12-13 20:48:35 +0000 | [diff] [blame] | 30 | #define lastdec (gd->arch.lastinc) |
Marek Vasut | c140e98 | 2011-11-08 23:18:08 +0000 | [diff] [blame] | 31 | |
| 32 | /* |
| 33 | * This driver uses 1kHz clock source. |
| 34 | */ |
Fadil Berisha | 69d8ce0 | 2013-02-28 10:03:26 -0500 | [diff] [blame] | 35 | #define MXS_INCREMENTER_HZ 1000 |
Marek Vasut | c140e98 | 2011-11-08 23:18:08 +0000 | [diff] [blame] | 36 | |
| 37 | static inline unsigned long tick_to_time(unsigned long tick) |
| 38 | { |
Fadil Berisha | 69d8ce0 | 2013-02-28 10:03:26 -0500 | [diff] [blame] | 39 | return tick / (MXS_INCREMENTER_HZ / CONFIG_SYS_HZ); |
Marek Vasut | c140e98 | 2011-11-08 23:18:08 +0000 | [diff] [blame] | 40 | } |
| 41 | |
| 42 | static inline unsigned long time_to_tick(unsigned long time) |
| 43 | { |
Fadil Berisha | 69d8ce0 | 2013-02-28 10:03:26 -0500 | [diff] [blame] | 44 | return time * (MXS_INCREMENTER_HZ / CONFIG_SYS_HZ); |
Marek Vasut | c140e98 | 2011-11-08 23:18:08 +0000 | [diff] [blame] | 45 | } |
| 46 | |
| 47 | /* Calculate how many ticks happen in "us" microseconds */ |
| 48 | static inline unsigned long us_to_tick(unsigned long us) |
| 49 | { |
Fadil Berisha | 69d8ce0 | 2013-02-28 10:03:26 -0500 | [diff] [blame] | 50 | return (us * MXS_INCREMENTER_HZ) / 1000000; |
Marek Vasut | c140e98 | 2011-11-08 23:18:08 +0000 | [diff] [blame] | 51 | } |
| 52 | |
| 53 | int timer_init(void) |
| 54 | { |
Otavio Salvador | 22f4ff9 | 2012-08-05 09:05:31 +0000 | [diff] [blame] | 55 | struct mxs_timrot_regs *timrot_regs = |
| 56 | (struct mxs_timrot_regs *)MXS_TIMROT_BASE; |
Marek Vasut | c140e98 | 2011-11-08 23:18:08 +0000 | [diff] [blame] | 57 | |
| 58 | /* Reset Timers and Rotary Encoder module */ |
Otavio Salvador | cbf0bf2 | 2012-08-13 09:53:12 +0000 | [diff] [blame] | 59 | mxs_reset_block(&timrot_regs->hw_timrot_rotctrl_reg); |
Marek Vasut | c140e98 | 2011-11-08 23:18:08 +0000 | [diff] [blame] | 60 | |
| 61 | /* Set fixed_count to 0 */ |
Fadil Berisha | d608f6e | 2013-02-27 17:00:07 +0000 | [diff] [blame] | 62 | #if defined(CONFIG_MX23) |
| 63 | writel(0, &timrot_regs->hw_timrot_timcount0); |
| 64 | #elif defined(CONFIG_MX28) |
Marek Vasut | c140e98 | 2011-11-08 23:18:08 +0000 | [diff] [blame] | 65 | writel(0, &timrot_regs->hw_timrot_fixed_count0); |
Fadil Berisha | d608f6e | 2013-02-27 17:00:07 +0000 | [diff] [blame] | 66 | #endif |
Marek Vasut | c140e98 | 2011-11-08 23:18:08 +0000 | [diff] [blame] | 67 | |
| 68 | /* Set UPDATE bit and 1Khz frequency */ |
| 69 | writel(TIMROT_TIMCTRLn_UPDATE | TIMROT_TIMCTRLn_RELOAD | |
| 70 | TIMROT_TIMCTRLn_SELECT_1KHZ_XTAL, |
| 71 | &timrot_regs->hw_timrot_timctrl0); |
| 72 | |
| 73 | /* Set fixed_count to maximal value */ |
Fadil Berisha | d608f6e | 2013-02-27 17:00:07 +0000 | [diff] [blame] | 74 | #if defined(CONFIG_MX23) |
| 75 | writel(TIMER_LOAD_VAL - 1, &timrot_regs->hw_timrot_timcount0); |
| 76 | #elif defined(CONFIG_MX28) |
Marek Vasut | c140e98 | 2011-11-08 23:18:08 +0000 | [diff] [blame] | 77 | writel(TIMER_LOAD_VAL, &timrot_regs->hw_timrot_fixed_count0); |
Fadil Berisha | d608f6e | 2013-02-27 17:00:07 +0000 | [diff] [blame] | 78 | #endif |
Marek Vasut | c140e98 | 2011-11-08 23:18:08 +0000 | [diff] [blame] | 79 | |
| 80 | return 0; |
| 81 | } |
| 82 | |
Marek Vasut | c142b67 | 2012-02-07 06:47:31 +0000 | [diff] [blame] | 83 | unsigned long long get_ticks(void) |
Marek Vasut | c140e98 | 2011-11-08 23:18:08 +0000 | [diff] [blame] | 84 | { |
Otavio Salvador | 22f4ff9 | 2012-08-05 09:05:31 +0000 | [diff] [blame] | 85 | struct mxs_timrot_regs *timrot_regs = |
| 86 | (struct mxs_timrot_regs *)MXS_TIMROT_BASE; |
Fadil Berisha | d608f6e | 2013-02-27 17:00:07 +0000 | [diff] [blame] | 87 | uint32_t now; |
Marek Vasut | c140e98 | 2011-11-08 23:18:08 +0000 | [diff] [blame] | 88 | |
| 89 | /* Current tick value */ |
Fadil Berisha | d608f6e | 2013-02-27 17:00:07 +0000 | [diff] [blame] | 90 | #if defined(CONFIG_MX23) |
| 91 | /* Upper bits are the valid ones. */ |
| 92 | now = readl(&timrot_regs->hw_timrot_timcount0) >> |
| 93 | TIMROT_RUNNING_COUNTn_RUNNING_COUNT_OFFSET; |
| 94 | #elif defined(CONFIG_MX28) |
| 95 | now = readl(&timrot_regs->hw_timrot_running_count0); |
Wolfgang Denk | 1fc4234 | 2014-11-06 14:03:04 +0100 | [diff] [blame] | 96 | #else |
| 97 | #error "Don't know how to read timrot_regs" |
Fadil Berisha | d608f6e | 2013-02-27 17:00:07 +0000 | [diff] [blame] | 98 | #endif |
Marek Vasut | c140e98 | 2011-11-08 23:18:08 +0000 | [diff] [blame] | 99 | |
| 100 | if (lastdec >= now) { |
| 101 | /* |
| 102 | * normal mode (non roll) |
| 103 | * move stamp forward with absolut diff ticks |
| 104 | */ |
| 105 | timestamp += (lastdec - now); |
| 106 | } else { |
| 107 | /* we have rollover of decrementer */ |
| 108 | timestamp += (TIMER_LOAD_VAL - now) + lastdec; |
| 109 | |
| 110 | } |
| 111 | lastdec = now; |
| 112 | |
Marek Vasut | c142b67 | 2012-02-07 06:47:31 +0000 | [diff] [blame] | 113 | return timestamp; |
| 114 | } |
| 115 | |
Marek Vasut | c142b67 | 2012-02-07 06:47:31 +0000 | [diff] [blame] | 116 | ulong get_timer(ulong base) |
| 117 | { |
Patrick Delaunay | 9858a60 | 2018-10-05 11:33:52 +0200 | [diff] [blame] | 118 | return tick_to_time(get_ticks()) - base; |
Marek Vasut | c142b67 | 2012-02-07 06:47:31 +0000 | [diff] [blame] | 119 | } |
| 120 | |
Marek Vasut | c140e98 | 2011-11-08 23:18:08 +0000 | [diff] [blame] | 121 | /* We use the HW_DIGCTL_MICROSECONDS register for sub-millisecond timer. */ |
Fadil Berisha | 69d8ce0 | 2013-02-28 10:03:26 -0500 | [diff] [blame] | 122 | #define MXS_HW_DIGCTL_MICROSECONDS 0x8001c0c0 |
Marek Vasut | c140e98 | 2011-11-08 23:18:08 +0000 | [diff] [blame] | 123 | |
| 124 | void __udelay(unsigned long usec) |
| 125 | { |
| 126 | uint32_t old, new, incr; |
| 127 | uint32_t counter = 0; |
| 128 | |
Fadil Berisha | 69d8ce0 | 2013-02-28 10:03:26 -0500 | [diff] [blame] | 129 | old = readl(MXS_HW_DIGCTL_MICROSECONDS); |
Marek Vasut | c140e98 | 2011-11-08 23:18:08 +0000 | [diff] [blame] | 130 | |
| 131 | while (counter < usec) { |
Fadil Berisha | 69d8ce0 | 2013-02-28 10:03:26 -0500 | [diff] [blame] | 132 | new = readl(MXS_HW_DIGCTL_MICROSECONDS); |
Marek Vasut | c140e98 | 2011-11-08 23:18:08 +0000 | [diff] [blame] | 133 | |
| 134 | /* Check if the timer wrapped. */ |
| 135 | if (new < old) { |
| 136 | incr = 0xffffffff - old; |
| 137 | incr += new; |
| 138 | } else { |
| 139 | incr = new - old; |
| 140 | } |
| 141 | |
| 142 | /* |
| 143 | * Check if we are close to the maximum time and the counter |
| 144 | * would wrap if incremented. If that's the case, break out |
| 145 | * from the loop as the requested delay time passed. |
| 146 | */ |
| 147 | if (counter + incr < counter) |
| 148 | break; |
| 149 | |
| 150 | counter += incr; |
| 151 | old = new; |
| 152 | } |
| 153 | } |
Marek Vasut | c142b67 | 2012-02-07 06:47:31 +0000 | [diff] [blame] | 154 | |
| 155 | ulong get_tbclk(void) |
| 156 | { |
Fadil Berisha | 69d8ce0 | 2013-02-28 10:03:26 -0500 | [diff] [blame] | 157 | return MXS_INCREMENTER_HZ; |
Marek Vasut | c142b67 | 2012-02-07 06:47:31 +0000 | [diff] [blame] | 158 | } |