Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Patrice Chotard | 5fffeab | 2017-09-13 18:00:06 +0200 | [diff] [blame] | 2 | /* |
Patrice Chotard | 789ee0e | 2017-10-23 09:53:58 +0200 | [diff] [blame] | 3 | * Copyright (C) 2017, STMicroelectronics - All Rights Reserved |
Patrice Chotard | 5d9950d | 2020-12-02 18:47:30 +0100 | [diff] [blame] | 4 | * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics. |
Patrice Chotard | 5fffeab | 2017-09-13 18:00:06 +0200 | [diff] [blame] | 5 | */ |
| 6 | |
Patrick Delaunay | 88c7eb7 | 2020-11-06 19:01:47 +0100 | [diff] [blame] | 7 | #define LOG_CATEGORY UCLASS_CLK |
| 8 | |
Patrice Chotard | 5fffeab | 2017-09-13 18:00:06 +0200 | [diff] [blame] | 9 | #include <clk-uclass.h> |
| 10 | #include <dm.h> |
Simon Glass | 0f2af88 | 2020-05-10 11:40:05 -0600 | [diff] [blame] | 11 | #include <log.h> |
Patrice Chotard | 5fffeab | 2017-09-13 18:00:06 +0200 | [diff] [blame] | 12 | #include <regmap.h> |
| 13 | #include <syscon.h> |
| 14 | #include <asm/io.h> |
Patrick Delaunay | 88c7eb7 | 2020-11-06 19:01:47 +0100 | [diff] [blame] | 15 | #include <dm/device_compat.h> |
Patrice Chotard | 5fffeab | 2017-09-13 18:00:06 +0200 | [diff] [blame] | 16 | #include <dm/root.h> |
Simon Glass | 4dcacfc | 2020-05-10 11:40:13 -0600 | [diff] [blame] | 17 | #include <linux/bitops.h> |
Patrice Chotard | 5fffeab | 2017-09-13 18:00:06 +0200 | [diff] [blame] | 18 | |
| 19 | #include <dt-bindings/clock/stm32h7-clks.h> |
| 20 | |
Patrice Chotard | 5fffeab | 2017-09-13 18:00:06 +0200 | [diff] [blame] | 21 | /* RCC CR specific definitions */ |
| 22 | #define RCC_CR_HSION BIT(0) |
| 23 | #define RCC_CR_HSIRDY BIT(2) |
| 24 | |
| 25 | #define RCC_CR_HSEON BIT(16) |
| 26 | #define RCC_CR_HSERDY BIT(17) |
| 27 | #define RCC_CR_HSEBYP BIT(18) |
| 28 | #define RCC_CR_PLL1ON BIT(24) |
| 29 | #define RCC_CR_PLL1RDY BIT(25) |
| 30 | |
| 31 | #define RCC_CR_HSIDIV_MASK GENMASK(4, 3) |
| 32 | #define RCC_CR_HSIDIV_SHIFT 3 |
| 33 | |
| 34 | #define RCC_CFGR_SW_MASK GENMASK(2, 0) |
| 35 | #define RCC_CFGR_SW_HSI 0 |
| 36 | #define RCC_CFGR_SW_CSI 1 |
| 37 | #define RCC_CFGR_SW_HSE 2 |
| 38 | #define RCC_CFGR_SW_PLL1 3 |
Patrice Chotard | 5301635 | 2018-02-07 10:44:47 +0100 | [diff] [blame] | 39 | #define RCC_CFGR_TIMPRE BIT(15) |
Patrice Chotard | 5fffeab | 2017-09-13 18:00:06 +0200 | [diff] [blame] | 40 | |
| 41 | #define RCC_PLLCKSELR_PLLSRC_HSI 0 |
| 42 | #define RCC_PLLCKSELR_PLLSRC_CSI 1 |
| 43 | #define RCC_PLLCKSELR_PLLSRC_HSE 2 |
| 44 | #define RCC_PLLCKSELR_PLLSRC_NO_CLK 3 |
| 45 | |
| 46 | #define RCC_PLLCKSELR_PLLSRC_MASK GENMASK(1, 0) |
| 47 | |
| 48 | #define RCC_PLLCKSELR_DIVM1_SHIFT 4 |
| 49 | #define RCC_PLLCKSELR_DIVM1_MASK GENMASK(9, 4) |
| 50 | |
| 51 | #define RCC_PLL1DIVR_DIVN1_MASK GENMASK(8, 0) |
| 52 | |
| 53 | #define RCC_PLL1DIVR_DIVP1_SHIFT 9 |
| 54 | #define RCC_PLL1DIVR_DIVP1_MASK GENMASK(15, 9) |
| 55 | |
| 56 | #define RCC_PLL1DIVR_DIVQ1_SHIFT 16 |
| 57 | #define RCC_PLL1DIVR_DIVQ1_MASK GENMASK(22, 16) |
| 58 | |
| 59 | #define RCC_PLL1DIVR_DIVR1_SHIFT 24 |
| 60 | #define RCC_PLL1DIVR_DIVR1_MASK GENMASK(30, 24) |
| 61 | |
| 62 | #define RCC_PLL1FRACR_FRACN1_SHIFT 3 |
| 63 | #define RCC_PLL1FRACR_FRACN1_MASK GENMASK(15, 3) |
| 64 | |
| 65 | #define RCC_PLLCFGR_PLL1RGE_SHIFT 2 |
| 66 | #define PLL1RGE_1_2_MHZ 0 |
| 67 | #define PLL1RGE_2_4_MHZ 1 |
| 68 | #define PLL1RGE_4_8_MHZ 2 |
| 69 | #define PLL1RGE_8_16_MHZ 3 |
| 70 | #define RCC_PLLCFGR_DIVP1EN BIT(16) |
| 71 | #define RCC_PLLCFGR_DIVQ1EN BIT(17) |
| 72 | #define RCC_PLLCFGR_DIVR1EN BIT(18) |
| 73 | |
| 74 | #define RCC_D1CFGR_HPRE_MASK GENMASK(3, 0) |
| 75 | #define RCC_D1CFGR_HPRE_DIVIDED BIT(3) |
| 76 | #define RCC_D1CFGR_HPRE_DIVIDER GENMASK(2, 0) |
| 77 | |
| 78 | #define RCC_D1CFGR_HPRE_DIV2 8 |
| 79 | |
| 80 | #define RCC_D1CFGR_D1PPRE_SHIFT 4 |
| 81 | #define RCC_D1CFGR_D1PPRE_DIVIDED BIT(6) |
| 82 | #define RCC_D1CFGR_D1PPRE_DIVIDER GENMASK(5, 4) |
| 83 | |
| 84 | #define RCC_D1CFGR_D1CPRE_SHIFT 8 |
| 85 | #define RCC_D1CFGR_D1CPRE_DIVIDER GENMASK(10, 8) |
| 86 | #define RCC_D1CFGR_D1CPRE_DIVIDED BIT(11) |
| 87 | |
| 88 | #define RCC_D2CFGR_D2PPRE1_SHIFT 4 |
| 89 | #define RCC_D2CFGR_D2PPRE1_DIVIDED BIT(6) |
| 90 | #define RCC_D2CFGR_D2PPRE1_DIVIDER GENMASK(5, 4) |
| 91 | |
| 92 | #define RCC_D2CFGR_D2PPRE2_SHIFT 8 |
| 93 | #define RCC_D2CFGR_D2PPRE2_DIVIDED BIT(10) |
| 94 | #define RCC_D2CFGR_D2PPRE2_DIVIDER GENMASK(9, 8) |
| 95 | |
| 96 | #define RCC_D3CFGR_D3PPRE_SHIFT 4 |
| 97 | #define RCC_D3CFGR_D3PPRE_DIVIDED BIT(6) |
| 98 | #define RCC_D3CFGR_D3PPRE_DIVIDER GENMASK(5, 4) |
| 99 | |
| 100 | #define RCC_D1CCIPR_FMCSRC_MASK GENMASK(1, 0) |
| 101 | #define FMCSRC_HCLKD1 0 |
| 102 | #define FMCSRC_PLL1_Q_CK 1 |
| 103 | #define FMCSRC_PLL2_R_CK 2 |
| 104 | #define FMCSRC_PER_CK 3 |
| 105 | |
| 106 | #define RCC_D1CCIPR_QSPISRC_MASK GENMASK(5, 4) |
| 107 | #define RCC_D1CCIPR_QSPISRC_SHIFT 4 |
| 108 | #define QSPISRC_HCLKD1 0 |
| 109 | #define QSPISRC_PLL1_Q_CK 1 |
| 110 | #define QSPISRC_PLL2_R_CK 2 |
| 111 | #define QSPISRC_PER_CK 3 |
| 112 | |
| 113 | #define PWR_CR3 0x0c |
Patrice Chotard | aa69ee5 | 2017-10-09 11:41:24 +0200 | [diff] [blame] | 114 | #define PWR_CR3_SCUEN BIT(2) |
Patrice Chotard | 5fffeab | 2017-09-13 18:00:06 +0200 | [diff] [blame] | 115 | #define PWR_D3CR 0x18 |
| 116 | #define PWR_D3CR_VOS_MASK GENMASK(15, 14) |
| 117 | #define PWR_D3CR_VOS_SHIFT 14 |
| 118 | #define VOS_SCALE_3 1 |
| 119 | #define VOS_SCALE_2 2 |
| 120 | #define VOS_SCALE_1 3 |
| 121 | #define PWR_D3CR_VOSREADY BIT(13) |
| 122 | |
| 123 | struct stm32_rcc_regs { |
| 124 | u32 cr; /* 0x00 Source Control Register */ |
| 125 | u32 icscr; /* 0x04 Internal Clock Source Calibration Register */ |
| 126 | u32 crrcr; /* 0x08 Clock Recovery RC Register */ |
| 127 | u32 reserved1; /* 0x0c reserved */ |
| 128 | u32 cfgr; /* 0x10 Clock Configuration Register */ |
| 129 | u32 reserved2; /* 0x14 reserved */ |
| 130 | u32 d1cfgr; /* 0x18 Domain 1 Clock Configuration Register */ |
| 131 | u32 d2cfgr; /* 0x1c Domain 2 Clock Configuration Register */ |
| 132 | u32 d3cfgr; /* 0x20 Domain 3 Clock Configuration Register */ |
| 133 | u32 reserved3; /* 0x24 reserved */ |
| 134 | u32 pllckselr; /* 0x28 PLLs Clock Source Selection Register */ |
| 135 | u32 pllcfgr; /* 0x2c PLLs Configuration Register */ |
| 136 | u32 pll1divr; /* 0x30 PLL1 Dividers Configuration Register */ |
| 137 | u32 pll1fracr; /* 0x34 PLL1 Fractional Divider Register */ |
| 138 | u32 pll2divr; /* 0x38 PLL2 Dividers Configuration Register */ |
| 139 | u32 pll2fracr; /* 0x3c PLL2 Fractional Divider Register */ |
| 140 | u32 pll3divr; /* 0x40 PLL3 Dividers Configuration Register */ |
| 141 | u32 pll3fracr; /* 0x44 PLL3 Fractional Divider Register */ |
| 142 | u32 reserved4; /* 0x48 reserved */ |
| 143 | u32 d1ccipr; /* 0x4c Domain 1 Kernel Clock Configuration Register */ |
| 144 | u32 d2ccip1r; /* 0x50 Domain 2 Kernel Clock Configuration Register */ |
| 145 | u32 d2ccip2r; /* 0x54 Domain 2 Kernel Clock Configuration Register */ |
| 146 | u32 d3ccipr; /* 0x58 Domain 3 Kernel Clock Configuration Register */ |
| 147 | u32 reserved5; /* 0x5c reserved */ |
| 148 | u32 cier; /* 0x60 Clock Source Interrupt Enable Register */ |
| 149 | u32 cifr; /* 0x64 Clock Source Interrupt Flag Register */ |
| 150 | u32 cicr; /* 0x68 Clock Source Interrupt Clear Register */ |
| 151 | u32 reserved6; /* 0x6c reserved */ |
| 152 | u32 bdcr; /* 0x70 Backup Domain Control Register */ |
| 153 | u32 csr; /* 0x74 Clock Control and Status Register */ |
| 154 | u32 reserved7; /* 0x78 reserved */ |
| 155 | |
| 156 | u32 ahb3rstr; /* 0x7c AHB3 Peripheral Reset Register */ |
| 157 | u32 ahb1rstr; /* 0x80 AHB1 Peripheral Reset Register */ |
| 158 | u32 ahb2rstr; /* 0x84 AHB2 Peripheral Reset Register */ |
| 159 | u32 ahb4rstr; /* 0x88 AHB4 Peripheral Reset Register */ |
| 160 | |
| 161 | u32 apb3rstr; /* 0x8c APB3 Peripheral Reset Register */ |
| 162 | u32 apb1lrstr; /* 0x90 APB1 low Peripheral Reset Register */ |
| 163 | u32 apb1hrstr; /* 0x94 APB1 high Peripheral Reset Register */ |
| 164 | u32 apb2rstr; /* 0x98 APB2 Clock Register */ |
| 165 | u32 apb4rstr; /* 0x9c APB4 Clock Register */ |
| 166 | |
| 167 | u32 gcr; /* 0xa0 Global Control Register */ |
| 168 | u32 reserved8; /* 0xa4 reserved */ |
| 169 | u32 d3amr; /* 0xa8 D3 Autonomous mode Register */ |
| 170 | u32 reserved9[9];/* 0xac to 0xcc reserved */ |
| 171 | u32 rsr; /* 0xd0 Reset Status Register */ |
| 172 | u32 ahb3enr; /* 0xd4 AHB3 Clock Register */ |
| 173 | u32 ahb1enr; /* 0xd8 AHB1 Clock Register */ |
| 174 | u32 ahb2enr; /* 0xdc AHB2 Clock Register */ |
| 175 | u32 ahb4enr; /* 0xe0 AHB4 Clock Register */ |
| 176 | |
| 177 | u32 apb3enr; /* 0xe4 APB3 Clock Register */ |
| 178 | u32 apb1lenr; /* 0xe8 APB1 low Clock Register */ |
| 179 | u32 apb1henr; /* 0xec APB1 high Clock Register */ |
| 180 | u32 apb2enr; /* 0xf0 APB2 Clock Register */ |
| 181 | u32 apb4enr; /* 0xf4 APB4 Clock Register */ |
| 182 | }; |
| 183 | |
| 184 | #define RCC_AHB3ENR offsetof(struct stm32_rcc_regs, ahb3enr) |
| 185 | #define RCC_AHB1ENR offsetof(struct stm32_rcc_regs, ahb1enr) |
| 186 | #define RCC_AHB2ENR offsetof(struct stm32_rcc_regs, ahb2enr) |
| 187 | #define RCC_AHB4ENR offsetof(struct stm32_rcc_regs, ahb4enr) |
| 188 | #define RCC_APB3ENR offsetof(struct stm32_rcc_regs, apb3enr) |
| 189 | #define RCC_APB1LENR offsetof(struct stm32_rcc_regs, apb1lenr) |
| 190 | #define RCC_APB1HENR offsetof(struct stm32_rcc_regs, apb1henr) |
| 191 | #define RCC_APB2ENR offsetof(struct stm32_rcc_regs, apb2enr) |
| 192 | #define RCC_APB4ENR offsetof(struct stm32_rcc_regs, apb4enr) |
| 193 | |
| 194 | struct clk_cfg { |
| 195 | u32 gate_offset; |
| 196 | u8 gate_bit_idx; |
| 197 | const char *name; |
| 198 | }; |
| 199 | |
Patrice Chotard | 5fffeab | 2017-09-13 18:00:06 +0200 | [diff] [blame] | 200 | /* |
| 201 | * the way all these entries are sorted in this array could seem |
| 202 | * unlogical, but we are dependant of kernel DT_bindings, |
| 203 | * where clocks are separate in 2 banks, peripheral clocks and |
| 204 | * kernel clocks. |
| 205 | */ |
| 206 | |
| 207 | static const struct clk_cfg clk_map[] = { |
Patrice Chotard | bb698ea | 2017-10-09 11:41:23 +0200 | [diff] [blame] | 208 | {RCC_AHB3ENR, 31, "d1sram1"}, /* peripheral clocks */ |
| 209 | {RCC_AHB3ENR, 30, "itcm"}, |
| 210 | {RCC_AHB3ENR, 29, "dtcm2"}, |
| 211 | {RCC_AHB3ENR, 28, "dtcm1"}, |
| 212 | {RCC_AHB3ENR, 8, "flitf"}, |
| 213 | {RCC_AHB3ENR, 5, "jpgdec"}, |
| 214 | {RCC_AHB3ENR, 4, "dma2d"}, |
| 215 | {RCC_AHB3ENR, 0, "mdma"}, |
| 216 | {RCC_AHB1ENR, 28, "usb2ulpi"}, |
| 217 | {RCC_AHB1ENR, 17, "eth1rx"}, |
| 218 | {RCC_AHB1ENR, 16, "eth1tx"}, |
| 219 | {RCC_AHB1ENR, 15, "eth1mac"}, |
| 220 | {RCC_AHB1ENR, 14, "art"}, |
| 221 | {RCC_AHB1ENR, 26, "usb1ulpi"}, |
| 222 | {RCC_AHB1ENR, 1, "dma2"}, |
| 223 | {RCC_AHB1ENR, 0, "dma1"}, |
| 224 | {RCC_AHB2ENR, 31, "d2sram3"}, |
| 225 | {RCC_AHB2ENR, 30, "d2sram2"}, |
| 226 | {RCC_AHB2ENR, 29, "d2sram1"}, |
| 227 | {RCC_AHB2ENR, 5, "hash"}, |
| 228 | {RCC_AHB2ENR, 4, "crypt"}, |
| 229 | {RCC_AHB2ENR, 0, "camitf"}, |
| 230 | {RCC_AHB4ENR, 28, "bkpram"}, |
| 231 | {RCC_AHB4ENR, 25, "hsem"}, |
| 232 | {RCC_AHB4ENR, 21, "bdma"}, |
| 233 | {RCC_AHB4ENR, 19, "crc"}, |
| 234 | {RCC_AHB4ENR, 10, "gpiok"}, |
| 235 | {RCC_AHB4ENR, 9, "gpioj"}, |
| 236 | {RCC_AHB4ENR, 8, "gpioi"}, |
| 237 | {RCC_AHB4ENR, 7, "gpioh"}, |
| 238 | {RCC_AHB4ENR, 6, "gpiog"}, |
| 239 | {RCC_AHB4ENR, 5, "gpiof"}, |
| 240 | {RCC_AHB4ENR, 4, "gpioe"}, |
| 241 | {RCC_AHB4ENR, 3, "gpiod"}, |
| 242 | {RCC_AHB4ENR, 2, "gpioc"}, |
| 243 | {RCC_AHB4ENR, 1, "gpiob"}, |
| 244 | {RCC_AHB4ENR, 0, "gpioa"}, |
| 245 | {RCC_APB3ENR, 6, "wwdg1"}, |
| 246 | {RCC_APB1LENR, 29, "dac12"}, |
| 247 | {RCC_APB1LENR, 11, "wwdg2"}, |
| 248 | {RCC_APB1LENR, 8, "tim14"}, |
| 249 | {RCC_APB1LENR, 7, "tim13"}, |
| 250 | {RCC_APB1LENR, 6, "tim12"}, |
| 251 | {RCC_APB1LENR, 5, "tim7"}, |
| 252 | {RCC_APB1LENR, 4, "tim6"}, |
| 253 | {RCC_APB1LENR, 3, "tim5"}, |
| 254 | {RCC_APB1LENR, 2, "tim4"}, |
| 255 | {RCC_APB1LENR, 1, "tim3"}, |
| 256 | {RCC_APB1LENR, 0, "tim2"}, |
| 257 | {RCC_APB1HENR, 5, "mdios"}, |
| 258 | {RCC_APB1HENR, 4, "opamp"}, |
| 259 | {RCC_APB1HENR, 1, "crs"}, |
| 260 | {RCC_APB2ENR, 18, "tim17"}, |
| 261 | {RCC_APB2ENR, 17, "tim16"}, |
| 262 | {RCC_APB2ENR, 16, "tim15"}, |
| 263 | {RCC_APB2ENR, 1, "tim8"}, |
| 264 | {RCC_APB2ENR, 0, "tim1"}, |
| 265 | {RCC_APB4ENR, 26, "tmpsens"}, |
| 266 | {RCC_APB4ENR, 16, "rtcapb"}, |
| 267 | {RCC_APB4ENR, 15, "vref"}, |
| 268 | {RCC_APB4ENR, 14, "comp12"}, |
| 269 | {RCC_APB4ENR, 1, "syscfg"}, |
| 270 | {RCC_AHB3ENR, 16, "sdmmc1"}, /* kernel clocks */ |
| 271 | {RCC_AHB3ENR, 14, "quadspi"}, |
| 272 | {RCC_AHB3ENR, 12, "fmc"}, |
| 273 | {RCC_AHB1ENR, 27, "usb2otg"}, |
| 274 | {RCC_AHB1ENR, 25, "usb1otg"}, |
| 275 | {RCC_AHB1ENR, 5, "adc12"}, |
| 276 | {RCC_AHB2ENR, 9, "sdmmc2"}, |
| 277 | {RCC_AHB2ENR, 6, "rng"}, |
| 278 | {RCC_AHB4ENR, 24, "adc3"}, |
| 279 | {RCC_APB3ENR, 4, "dsi"}, |
| 280 | {RCC_APB3ENR, 3, "ltdc"}, |
| 281 | {RCC_APB1LENR, 31, "usart8"}, |
| 282 | {RCC_APB1LENR, 30, "usart7"}, |
| 283 | {RCC_APB1LENR, 27, "hdmicec"}, |
| 284 | {RCC_APB1LENR, 23, "i2c3"}, |
| 285 | {RCC_APB1LENR, 22, "i2c2"}, |
| 286 | {RCC_APB1LENR, 21, "i2c1"}, |
| 287 | {RCC_APB1LENR, 20, "uart5"}, |
| 288 | {RCC_APB1LENR, 19, "uart4"}, |
| 289 | {RCC_APB1LENR, 18, "usart3"}, |
| 290 | {RCC_APB1LENR, 17, "usart2"}, |
| 291 | {RCC_APB1LENR, 16, "spdifrx"}, |
| 292 | {RCC_APB1LENR, 15, "spi3"}, |
| 293 | {RCC_APB1LENR, 14, "spi2"}, |
| 294 | {RCC_APB1LENR, 9, "lptim1"}, |
| 295 | {RCC_APB1HENR, 8, "fdcan"}, |
| 296 | {RCC_APB1HENR, 2, "swp"}, |
| 297 | {RCC_APB2ENR, 29, "hrtim"}, |
| 298 | {RCC_APB2ENR, 28, "dfsdm1"}, |
| 299 | {RCC_APB2ENR, 24, "sai3"}, |
| 300 | {RCC_APB2ENR, 23, "sai2"}, |
| 301 | {RCC_APB2ENR, 22, "sai1"}, |
| 302 | {RCC_APB2ENR, 20, "spi5"}, |
| 303 | {RCC_APB2ENR, 13, "spi4"}, |
| 304 | {RCC_APB2ENR, 12, "spi1"}, |
| 305 | {RCC_APB2ENR, 5, "usart6"}, |
| 306 | {RCC_APB2ENR, 4, "usart1"}, |
| 307 | {RCC_APB4ENR, 21, "sai4a"}, |
| 308 | {RCC_APB4ENR, 21, "sai4b"}, |
| 309 | {RCC_APB4ENR, 12, "lptim5"}, |
| 310 | {RCC_APB4ENR, 11, "lptim4"}, |
| 311 | {RCC_APB4ENR, 10, "lptim3"}, |
| 312 | {RCC_APB4ENR, 9, "lptim2"}, |
| 313 | {RCC_APB4ENR, 7, "i2c4"}, |
| 314 | {RCC_APB4ENR, 5, "spi6"}, |
| 315 | {RCC_APB4ENR, 3, "lpuart1"}, |
Patrice Chotard | 5fffeab | 2017-09-13 18:00:06 +0200 | [diff] [blame] | 316 | }; |
| 317 | |
| 318 | struct stm32_clk { |
| 319 | struct stm32_rcc_regs *rcc_base; |
| 320 | struct regmap *pwr_regmap; |
| 321 | }; |
| 322 | |
| 323 | struct pll_psc { |
| 324 | u8 divm; |
| 325 | u16 divn; |
| 326 | u8 divp; |
| 327 | u8 divq; |
| 328 | u8 divr; |
| 329 | }; |
| 330 | |
| 331 | /* |
| 332 | * OSC_HSE = 25 MHz |
| 333 | * VCO = 500MHz |
| 334 | * pll1_p = 250MHz / pll1_q = 250MHz pll1_r = 250Mhz |
| 335 | */ |
| 336 | struct pll_psc sys_pll_psc = { |
| 337 | .divm = 4, |
| 338 | .divn = 80, |
| 339 | .divp = 2, |
| 340 | .divq = 2, |
| 341 | .divr = 2, |
| 342 | }; |
| 343 | |
Patrice Chotard | 5301635 | 2018-02-07 10:44:47 +0100 | [diff] [blame] | 344 | enum apb { |
| 345 | APB1, |
| 346 | APB2, |
| 347 | }; |
| 348 | |
Patrice Chotard | 5fffeab | 2017-09-13 18:00:06 +0200 | [diff] [blame] | 349 | int configure_clocks(struct udevice *dev) |
| 350 | { |
| 351 | struct stm32_clk *priv = dev_get_priv(dev); |
| 352 | struct stm32_rcc_regs *regs = priv->rcc_base; |
| 353 | uint8_t *pwr_base = (uint8_t *)regmap_get_range(priv->pwr_regmap, 0); |
| 354 | uint32_t pllckselr = 0; |
| 355 | uint32_t pll1divr = 0; |
| 356 | uint32_t pllcfgr = 0; |
| 357 | |
| 358 | /* Switch on HSI */ |
| 359 | setbits_le32(®s->cr, RCC_CR_HSION); |
| 360 | while (!(readl(®s->cr) & RCC_CR_HSIRDY)) |
| 361 | ; |
| 362 | |
| 363 | /* Reset CFGR, now HSI is the default system clock */ |
| 364 | writel(0, ®s->cfgr); |
| 365 | |
| 366 | /* Set all kernel domain clock registers to reset value*/ |
| 367 | writel(0x0, ®s->d1ccipr); |
| 368 | writel(0x0, ®s->d2ccip1r); |
| 369 | writel(0x0, ®s->d2ccip2r); |
| 370 | |
Patrice Chotard | aa69ee5 | 2017-10-09 11:41:24 +0200 | [diff] [blame] | 371 | /* Set voltage scaling at scale 1 (1,15 - 1,26 Volts) */ |
Patrice Chotard | 5fffeab | 2017-09-13 18:00:06 +0200 | [diff] [blame] | 372 | clrsetbits_le32(pwr_base + PWR_D3CR, PWR_D3CR_VOS_MASK, |
| 373 | VOS_SCALE_1 << PWR_D3CR_VOS_SHIFT); |
Patrice Chotard | aa69ee5 | 2017-10-09 11:41:24 +0200 | [diff] [blame] | 374 | /* Lock supply configuration update */ |
| 375 | clrbits_le32(pwr_base + PWR_CR3, PWR_CR3_SCUEN); |
Patrice Chotard | 5fffeab | 2017-09-13 18:00:06 +0200 | [diff] [blame] | 376 | while (!(readl(pwr_base + PWR_D3CR) & PWR_D3CR_VOSREADY)) |
| 377 | ; |
| 378 | |
| 379 | /* disable HSE to configure it */ |
| 380 | clrbits_le32(®s->cr, RCC_CR_HSEON); |
| 381 | while ((readl(®s->cr) & RCC_CR_HSERDY)) |
| 382 | ; |
| 383 | |
| 384 | /* clear HSE bypass and set it ON */ |
| 385 | clrbits_le32(®s->cr, RCC_CR_HSEBYP); |
| 386 | /* Switch on HSE */ |
| 387 | setbits_le32(®s->cr, RCC_CR_HSEON); |
| 388 | while (!(readl(®s->cr) & RCC_CR_HSERDY)) |
| 389 | ; |
| 390 | |
| 391 | /* pll setup, disable it */ |
| 392 | clrbits_le32(®s->cr, RCC_CR_PLL1ON); |
| 393 | while ((readl(®s->cr) & RCC_CR_PLL1RDY)) |
| 394 | ; |
| 395 | |
| 396 | /* Select HSE as PLL clock source */ |
| 397 | pllckselr |= RCC_PLLCKSELR_PLLSRC_HSE; |
| 398 | pllckselr |= sys_pll_psc.divm << RCC_PLLCKSELR_DIVM1_SHIFT; |
| 399 | writel(pllckselr, ®s->pllckselr); |
| 400 | |
| 401 | pll1divr |= (sys_pll_psc.divr - 1) << RCC_PLL1DIVR_DIVR1_SHIFT; |
| 402 | pll1divr |= (sys_pll_psc.divq - 1) << RCC_PLL1DIVR_DIVQ1_SHIFT; |
| 403 | pll1divr |= (sys_pll_psc.divp - 1) << RCC_PLL1DIVR_DIVP1_SHIFT; |
| 404 | pll1divr |= (sys_pll_psc.divn - 1); |
| 405 | writel(pll1divr, ®s->pll1divr); |
| 406 | |
| 407 | pllcfgr |= PLL1RGE_4_8_MHZ << RCC_PLLCFGR_PLL1RGE_SHIFT; |
| 408 | pllcfgr |= RCC_PLLCFGR_DIVP1EN; |
| 409 | pllcfgr |= RCC_PLLCFGR_DIVQ1EN; |
| 410 | pllcfgr |= RCC_PLLCFGR_DIVR1EN; |
| 411 | writel(pllcfgr, ®s->pllcfgr); |
| 412 | |
| 413 | /* pll setup, enable it */ |
| 414 | setbits_le32(®s->cr, RCC_CR_PLL1ON); |
| 415 | |
| 416 | /* set HPRE (/2) DI clk --> 125MHz */ |
| 417 | clrsetbits_le32(®s->d1cfgr, RCC_D1CFGR_HPRE_MASK, |
| 418 | RCC_D1CFGR_HPRE_DIV2); |
| 419 | |
| 420 | /* select PLL1 as system clock source (sys_ck)*/ |
| 421 | clrsetbits_le32(®s->cfgr, RCC_CFGR_SW_MASK, RCC_CFGR_SW_PLL1); |
| 422 | while ((readl(®s->cfgr) & RCC_CFGR_SW_MASK) != RCC_CFGR_SW_PLL1) |
| 423 | ; |
| 424 | |
| 425 | /* sdram: use pll1_q as fmc_k clk */ |
| 426 | clrsetbits_le32(®s->d1ccipr, RCC_D1CCIPR_FMCSRC_MASK, |
| 427 | FMCSRC_PLL1_Q_CK); |
| 428 | |
| 429 | return 0; |
| 430 | } |
| 431 | |
| 432 | static u32 stm32_get_HSI_divider(struct stm32_rcc_regs *regs) |
| 433 | { |
| 434 | u32 divider; |
| 435 | |
| 436 | /* get HSI divider value */ |
| 437 | divider = readl(®s->cr) & RCC_CR_HSIDIV_MASK; |
| 438 | divider = divider >> RCC_CR_HSIDIV_SHIFT; |
| 439 | |
| 440 | return divider; |
| 441 | }; |
| 442 | |
| 443 | enum pllsrc { |
| 444 | HSE, |
| 445 | LSE, |
| 446 | HSI, |
| 447 | CSI, |
| 448 | I2S, |
| 449 | TIMER, |
| 450 | PLLSRC_NB, |
| 451 | }; |
| 452 | |
| 453 | static const char * const pllsrc_name[PLLSRC_NB] = { |
| 454 | [HSE] = "clk-hse", |
| 455 | [LSE] = "clk-lse", |
| 456 | [HSI] = "clk-hsi", |
| 457 | [CSI] = "clk-csi", |
| 458 | [I2S] = "clk-i2s", |
| 459 | [TIMER] = "timer-clk" |
| 460 | }; |
| 461 | |
| 462 | static ulong stm32_get_rate(struct stm32_rcc_regs *regs, enum pllsrc pllsrc) |
| 463 | { |
| 464 | struct clk clk; |
| 465 | struct udevice *fixed_clock_dev = NULL; |
| 466 | u32 divider; |
| 467 | int ret; |
| 468 | const char *name = pllsrc_name[pllsrc]; |
| 469 | |
Patrick Delaunay | 88c7eb7 | 2020-11-06 19:01:47 +0100 | [diff] [blame] | 470 | log_debug("pllsrc name %s\n", name); |
Patrice Chotard | 5fffeab | 2017-09-13 18:00:06 +0200 | [diff] [blame] | 471 | |
| 472 | clk.id = 0; |
| 473 | ret = uclass_get_device_by_name(UCLASS_CLK, name, &fixed_clock_dev); |
| 474 | if (ret) { |
Patrick Delaunay | 88c7eb7 | 2020-11-06 19:01:47 +0100 | [diff] [blame] | 475 | log_err("Can't find clk %s (%d)", name, ret); |
Patrice Chotard | 5fffeab | 2017-09-13 18:00:06 +0200 | [diff] [blame] | 476 | return 0; |
| 477 | } |
| 478 | |
| 479 | ret = clk_request(fixed_clock_dev, &clk); |
| 480 | if (ret) { |
Patrick Delaunay | 88c7eb7 | 2020-11-06 19:01:47 +0100 | [diff] [blame] | 481 | log_err("Can't request %s clk (%d)", name, ret); |
Patrice Chotard | 5fffeab | 2017-09-13 18:00:06 +0200 | [diff] [blame] | 482 | return 0; |
| 483 | } |
| 484 | |
| 485 | divider = 0; |
| 486 | if (pllsrc == HSI) |
| 487 | divider = stm32_get_HSI_divider(regs); |
| 488 | |
Patrick Delaunay | 88c7eb7 | 2020-11-06 19:01:47 +0100 | [diff] [blame] | 489 | log_debug("divider %d rate %ld\n", divider, clk_get_rate(&clk)); |
Patrice Chotard | 5fffeab | 2017-09-13 18:00:06 +0200 | [diff] [blame] | 490 | |
| 491 | return clk_get_rate(&clk) >> divider; |
| 492 | }; |
| 493 | |
| 494 | enum pll1_output { |
| 495 | PLL1_P_CK, |
| 496 | PLL1_Q_CK, |
| 497 | PLL1_R_CK, |
| 498 | }; |
| 499 | |
| 500 | static u32 stm32_get_PLL1_rate(struct stm32_rcc_regs *regs, |
| 501 | enum pll1_output output) |
| 502 | { |
| 503 | ulong pllsrc = 0; |
| 504 | u32 divm1, divn1, divp1, divq1, divr1, fracn1; |
| 505 | ulong vco, rate; |
| 506 | |
| 507 | /* get the PLLSRC */ |
| 508 | switch (readl(®s->pllckselr) & RCC_PLLCKSELR_PLLSRC_MASK) { |
| 509 | case RCC_PLLCKSELR_PLLSRC_HSI: |
| 510 | pllsrc = stm32_get_rate(regs, HSI); |
| 511 | break; |
| 512 | case RCC_PLLCKSELR_PLLSRC_CSI: |
| 513 | pllsrc = stm32_get_rate(regs, CSI); |
| 514 | break; |
| 515 | case RCC_PLLCKSELR_PLLSRC_HSE: |
| 516 | pllsrc = stm32_get_rate(regs, HSE); |
| 517 | break; |
| 518 | case RCC_PLLCKSELR_PLLSRC_NO_CLK: |
| 519 | /* shouldn't happen */ |
Patrick Delaunay | 88c7eb7 | 2020-11-06 19:01:47 +0100 | [diff] [blame] | 520 | log_err("wrong value for RCC_PLLCKSELR register\n"); |
Patrice Chotard | 5fffeab | 2017-09-13 18:00:06 +0200 | [diff] [blame] | 521 | pllsrc = 0; |
| 522 | break; |
| 523 | } |
| 524 | |
| 525 | /* pllsrc = 0 ? no need to go ahead */ |
| 526 | if (!pllsrc) |
| 527 | return pllsrc; |
| 528 | |
| 529 | /* get divm1, divp1, divn1 and divr1 */ |
| 530 | divm1 = readl(®s->pllckselr) & RCC_PLLCKSELR_DIVM1_MASK; |
| 531 | divm1 = divm1 >> RCC_PLLCKSELR_DIVM1_SHIFT; |
| 532 | |
| 533 | divn1 = (readl(®s->pll1divr) & RCC_PLL1DIVR_DIVN1_MASK) + 1; |
| 534 | |
| 535 | divp1 = readl(®s->pll1divr) & RCC_PLL1DIVR_DIVP1_MASK; |
| 536 | divp1 = (divp1 >> RCC_PLL1DIVR_DIVP1_SHIFT) + 1; |
| 537 | |
| 538 | divq1 = readl(®s->pll1divr) & RCC_PLL1DIVR_DIVQ1_MASK; |
| 539 | divq1 = (divq1 >> RCC_PLL1DIVR_DIVQ1_SHIFT) + 1; |
| 540 | |
| 541 | divr1 = readl(®s->pll1divr) & RCC_PLL1DIVR_DIVR1_MASK; |
| 542 | divr1 = (divr1 >> RCC_PLL1DIVR_DIVR1_SHIFT) + 1; |
| 543 | |
| 544 | fracn1 = readl(®s->pll1fracr) & RCC_PLL1DIVR_DIVR1_MASK; |
| 545 | fracn1 = fracn1 & RCC_PLL1DIVR_DIVR1_SHIFT; |
| 546 | |
| 547 | vco = (pllsrc / divm1) * divn1; |
| 548 | rate = (pllsrc * fracn1) / (divm1 * 8192); |
| 549 | |
Patrick Delaunay | 88c7eb7 | 2020-11-06 19:01:47 +0100 | [diff] [blame] | 550 | log_debug("divm1 = %d divn1 = %d divp1 = %d divq1 = %d divr1 = %d\n", |
| 551 | divm1, divn1, divp1, divq1, divr1); |
| 552 | log_debug("fracn1 = %d vco = %ld rate = %ld\n", |
| 553 | fracn1, vco, rate); |
Patrice Chotard | 5fffeab | 2017-09-13 18:00:06 +0200 | [diff] [blame] | 554 | |
| 555 | switch (output) { |
| 556 | case PLL1_P_CK: |
| 557 | return (vco + rate) / divp1; |
| 558 | break; |
| 559 | case PLL1_Q_CK: |
| 560 | return (vco + rate) / divq1; |
| 561 | break; |
| 562 | |
| 563 | case PLL1_R_CK: |
| 564 | return (vco + rate) / divr1; |
| 565 | break; |
| 566 | } |
| 567 | |
| 568 | return -EINVAL; |
| 569 | } |
| 570 | |
Patrice Chotard | 5301635 | 2018-02-07 10:44:47 +0100 | [diff] [blame] | 571 | static u32 stm32_get_apb_psc(struct stm32_rcc_regs *regs, enum apb apb) |
| 572 | { |
| 573 | u16 prescaler_table[8] = {2, 4, 8, 16, 64, 128, 256, 512}; |
| 574 | u32 d2cfgr = readl(®s->d2cfgr); |
| 575 | |
| 576 | if (apb == APB1) { |
| 577 | if (d2cfgr & RCC_D2CFGR_D2PPRE1_DIVIDED) |
| 578 | /* get D2 domain APB1 prescaler */ |
| 579 | return prescaler_table[ |
| 580 | ((d2cfgr & RCC_D2CFGR_D2PPRE1_DIVIDER) |
| 581 | >> RCC_D2CFGR_D2PPRE1_SHIFT)]; |
| 582 | } else { /* APB2 */ |
| 583 | if (d2cfgr & RCC_D2CFGR_D2PPRE2_DIVIDED) |
| 584 | /* get D2 domain APB2 prescaler */ |
| 585 | return prescaler_table[ |
| 586 | ((d2cfgr & RCC_D2CFGR_D2PPRE2_DIVIDER) |
| 587 | >> RCC_D2CFGR_D2PPRE2_SHIFT)]; |
| 588 | } |
| 589 | |
| 590 | return 1; |
| 591 | }; |
| 592 | |
| 593 | static u32 stm32_get_timer_rate(struct stm32_clk *priv, u32 sysclk, |
| 594 | enum apb apb) |
| 595 | { |
| 596 | struct stm32_rcc_regs *regs = priv->rcc_base; |
| 597 | u32 psc = stm32_get_apb_psc(regs, apb); |
| 598 | |
| 599 | if (readl(®s->cfgr) & RCC_CFGR_TIMPRE) |
| 600 | /* |
| 601 | * if APB prescaler is configured to a |
| 602 | * division factor of 1, 2 or 4 |
| 603 | */ |
| 604 | switch (psc) { |
| 605 | case 1: |
| 606 | case 2: |
| 607 | case 4: |
| 608 | return sysclk; |
| 609 | case 8: |
| 610 | return sysclk / 2; |
| 611 | case 16: |
| 612 | return sysclk / 4; |
| 613 | default: |
Patrick Delaunay | 88c7eb7 | 2020-11-06 19:01:47 +0100 | [diff] [blame] | 614 | log_err("unexpected prescaler value (%d)\n", psc); |
Patrice Chotard | 5301635 | 2018-02-07 10:44:47 +0100 | [diff] [blame] | 615 | return 0; |
| 616 | } |
| 617 | else |
| 618 | switch (psc) { |
| 619 | case 1: |
| 620 | return sysclk; |
| 621 | case 2: |
| 622 | case 4: |
| 623 | case 8: |
| 624 | case 16: |
| 625 | return sysclk / psc; |
| 626 | default: |
Patrick Delaunay | 88c7eb7 | 2020-11-06 19:01:47 +0100 | [diff] [blame] | 627 | log_err("unexpected prescaler value (%d)\n", psc); |
Patrice Chotard | 5301635 | 2018-02-07 10:44:47 +0100 | [diff] [blame] | 628 | return 0; |
| 629 | } |
| 630 | }; |
| 631 | |
Patrice Chotard | 5fffeab | 2017-09-13 18:00:06 +0200 | [diff] [blame] | 632 | static ulong stm32_clk_get_rate(struct clk *clk) |
| 633 | { |
| 634 | struct stm32_clk *priv = dev_get_priv(clk->dev); |
| 635 | struct stm32_rcc_regs *regs = priv->rcc_base; |
| 636 | ulong sysclk = 0; |
| 637 | u32 gate_offset; |
Patrice Chotard | 78df577 | 2018-02-07 10:44:48 +0100 | [diff] [blame] | 638 | u32 d1cfgr, d3cfgr; |
Patrice Chotard | 5fffeab | 2017-09-13 18:00:06 +0200 | [diff] [blame] | 639 | /* prescaler table lookups for clock computation */ |
| 640 | u16 prescaler_table[8] = {2, 4, 8, 16, 64, 128, 256, 512}; |
| 641 | u8 source, idx; |
| 642 | |
| 643 | /* |
| 644 | * get system clock (sys_ck) source |
| 645 | * can be HSI_CK, CSI_CK, HSE_CK or pll1_p_ck |
| 646 | */ |
| 647 | source = readl(®s->cfgr) & RCC_CFGR_SW_MASK; |
| 648 | switch (source) { |
| 649 | case RCC_CFGR_SW_PLL1: |
| 650 | sysclk = stm32_get_PLL1_rate(regs, PLL1_P_CK); |
| 651 | break; |
| 652 | case RCC_CFGR_SW_HSE: |
| 653 | sysclk = stm32_get_rate(regs, HSE); |
| 654 | break; |
| 655 | |
| 656 | case RCC_CFGR_SW_CSI: |
| 657 | sysclk = stm32_get_rate(regs, CSI); |
| 658 | break; |
| 659 | |
| 660 | case RCC_CFGR_SW_HSI: |
| 661 | sysclk = stm32_get_rate(regs, HSI); |
| 662 | break; |
| 663 | } |
| 664 | |
| 665 | /* sysclk = 0 ? no need to go ahead */ |
| 666 | if (!sysclk) |
| 667 | return sysclk; |
| 668 | |
Patrick Delaunay | 88c7eb7 | 2020-11-06 19:01:47 +0100 | [diff] [blame] | 669 | dev_dbg(clk->dev, "system clock: source = %d freq = %ld\n", |
| 670 | source, sysclk); |
Patrice Chotard | 5fffeab | 2017-09-13 18:00:06 +0200 | [diff] [blame] | 671 | |
| 672 | d1cfgr = readl(®s->d1cfgr); |
| 673 | |
| 674 | if (d1cfgr & RCC_D1CFGR_D1CPRE_DIVIDED) { |
| 675 | /* get D1 domain Core prescaler */ |
| 676 | idx = (d1cfgr & RCC_D1CFGR_D1CPRE_DIVIDER) >> |
| 677 | RCC_D1CFGR_D1CPRE_SHIFT; |
| 678 | sysclk = sysclk / prescaler_table[idx]; |
| 679 | } |
| 680 | |
| 681 | if (d1cfgr & RCC_D1CFGR_HPRE_DIVIDED) { |
| 682 | /* get D1 domain AHB prescaler */ |
| 683 | idx = d1cfgr & RCC_D1CFGR_HPRE_DIVIDER; |
| 684 | sysclk = sysclk / prescaler_table[idx]; |
| 685 | } |
| 686 | |
| 687 | gate_offset = clk_map[clk->id].gate_offset; |
| 688 | |
Patrick Delaunay | 88c7eb7 | 2020-11-06 19:01:47 +0100 | [diff] [blame] | 689 | dev_dbg(clk->dev, "clk->id=%ld gate_offset=0x%x sysclk=%ld\n", |
| 690 | clk->id, gate_offset, sysclk); |
Patrice Chotard | 5fffeab | 2017-09-13 18:00:06 +0200 | [diff] [blame] | 691 | |
| 692 | switch (gate_offset) { |
| 693 | case RCC_AHB3ENR: |
| 694 | case RCC_AHB1ENR: |
| 695 | case RCC_AHB2ENR: |
| 696 | case RCC_AHB4ENR: |
| 697 | return sysclk; |
| 698 | break; |
| 699 | |
| 700 | case RCC_APB3ENR: |
| 701 | if (d1cfgr & RCC_D1CFGR_D1PPRE_DIVIDED) { |
| 702 | /* get D1 domain APB3 prescaler */ |
| 703 | idx = (d1cfgr & RCC_D1CFGR_D1PPRE_DIVIDER) >> |
| 704 | RCC_D1CFGR_D1PPRE_SHIFT; |
| 705 | sysclk = sysclk / prescaler_table[idx]; |
| 706 | } |
| 707 | |
Patrick Delaunay | 88c7eb7 | 2020-11-06 19:01:47 +0100 | [diff] [blame] | 708 | dev_dbg(clk->dev, "system clock: freq after APB3 prescaler = %ld\n", |
| 709 | sysclk); |
Patrice Chotard | 5fffeab | 2017-09-13 18:00:06 +0200 | [diff] [blame] | 710 | |
| 711 | return sysclk; |
| 712 | break; |
| 713 | |
| 714 | case RCC_APB4ENR: |
Patrice Chotard | 78df577 | 2018-02-07 10:44:48 +0100 | [diff] [blame] | 715 | d3cfgr = readl(®s->d3cfgr); |
| 716 | if (d3cfgr & RCC_D3CFGR_D3PPRE_DIVIDED) { |
Patrice Chotard | 5fffeab | 2017-09-13 18:00:06 +0200 | [diff] [blame] | 717 | /* get D3 domain APB4 prescaler */ |
Patrice Chotard | 78df577 | 2018-02-07 10:44:48 +0100 | [diff] [blame] | 718 | idx = (d3cfgr & RCC_D3CFGR_D3PPRE_DIVIDER) >> |
Patrice Chotard | 5fffeab | 2017-09-13 18:00:06 +0200 | [diff] [blame] | 719 | RCC_D3CFGR_D3PPRE_SHIFT; |
| 720 | sysclk = sysclk / prescaler_table[idx]; |
| 721 | } |
| 722 | |
Patrick Delaunay | 88c7eb7 | 2020-11-06 19:01:47 +0100 | [diff] [blame] | 723 | dev_dbg(clk->dev, |
| 724 | "system clock: freq after APB4 prescaler = %ld\n", |
| 725 | sysclk); |
Patrice Chotard | 5fffeab | 2017-09-13 18:00:06 +0200 | [diff] [blame] | 726 | |
| 727 | return sysclk; |
| 728 | break; |
| 729 | |
| 730 | case RCC_APB1LENR: |
| 731 | case RCC_APB1HENR: |
Patrice Chotard | 5301635 | 2018-02-07 10:44:47 +0100 | [diff] [blame] | 732 | /* special case for GPT timers */ |
| 733 | switch (clk->id) { |
| 734 | case TIM14_CK: |
| 735 | case TIM13_CK: |
| 736 | case TIM12_CK: |
| 737 | case TIM7_CK: |
| 738 | case TIM6_CK: |
| 739 | case TIM5_CK: |
| 740 | case TIM4_CK: |
| 741 | case TIM3_CK: |
| 742 | case TIM2_CK: |
| 743 | return stm32_get_timer_rate(priv, sysclk, APB1); |
Patrice Chotard | 5fffeab | 2017-09-13 18:00:06 +0200 | [diff] [blame] | 744 | } |
| 745 | |
Patrick Delaunay | 88c7eb7 | 2020-11-06 19:01:47 +0100 | [diff] [blame] | 746 | dev_dbg(clk->dev, |
| 747 | "system clock: freq after APB1 prescaler = %ld\n", |
| 748 | sysclk); |
Patrice Chotard | 5fffeab | 2017-09-13 18:00:06 +0200 | [diff] [blame] | 749 | |
Patrice Chotard | 5301635 | 2018-02-07 10:44:47 +0100 | [diff] [blame] | 750 | return (sysclk / stm32_get_apb_psc(regs, APB1)); |
Patrice Chotard | 5fffeab | 2017-09-13 18:00:06 +0200 | [diff] [blame] | 751 | break; |
| 752 | |
| 753 | case RCC_APB2ENR: |
Patrice Chotard | 5301635 | 2018-02-07 10:44:47 +0100 | [diff] [blame] | 754 | /* special case for timers */ |
| 755 | switch (clk->id) { |
| 756 | case TIM17_CK: |
| 757 | case TIM16_CK: |
| 758 | case TIM15_CK: |
| 759 | case TIM8_CK: |
| 760 | case TIM1_CK: |
| 761 | return stm32_get_timer_rate(priv, sysclk, APB2); |
Patrice Chotard | 5fffeab | 2017-09-13 18:00:06 +0200 | [diff] [blame] | 762 | } |
| 763 | |
Patrick Delaunay | 88c7eb7 | 2020-11-06 19:01:47 +0100 | [diff] [blame] | 764 | dev_dbg(clk->dev, |
| 765 | "system clock: freq after APB2 prescaler = %ld\n", |
| 766 | sysclk); |
Patrice Chotard | 5fffeab | 2017-09-13 18:00:06 +0200 | [diff] [blame] | 767 | |
Patrice Chotard | 5301635 | 2018-02-07 10:44:47 +0100 | [diff] [blame] | 768 | return (sysclk / stm32_get_apb_psc(regs, APB2)); |
| 769 | |
Patrice Chotard | 5fffeab | 2017-09-13 18:00:06 +0200 | [diff] [blame] | 770 | break; |
| 771 | |
| 772 | default: |
Patrick Delaunay | 88c7eb7 | 2020-11-06 19:01:47 +0100 | [diff] [blame] | 773 | dev_err(clk->dev, "unexpected gate_offset value (0x%x)\n", |
| 774 | gate_offset); |
Patrice Chotard | 5fffeab | 2017-09-13 18:00:06 +0200 | [diff] [blame] | 775 | return -EINVAL; |
| 776 | break; |
| 777 | } |
| 778 | } |
| 779 | |
| 780 | static int stm32_clk_enable(struct clk *clk) |
| 781 | { |
| 782 | struct stm32_clk *priv = dev_get_priv(clk->dev); |
| 783 | struct stm32_rcc_regs *regs = priv->rcc_base; |
| 784 | u32 gate_offset; |
| 785 | u32 gate_bit_index; |
| 786 | unsigned long clk_id = clk->id; |
| 787 | |
| 788 | gate_offset = clk_map[clk_id].gate_offset; |
| 789 | gate_bit_index = clk_map[clk_id].gate_bit_idx; |
| 790 | |
Patrick Delaunay | 88c7eb7 | 2020-11-06 19:01:47 +0100 | [diff] [blame] | 791 | dev_dbg(clk->dev, "clkid=%ld gate offset=0x%x bit_index=%d name=%s\n", |
| 792 | clk->id, gate_offset, gate_bit_index, |
| 793 | clk_map[clk_id].name); |
Patrice Chotard | 5fffeab | 2017-09-13 18:00:06 +0200 | [diff] [blame] | 794 | |
| 795 | setbits_le32(®s->cr + (gate_offset / 4), BIT(gate_bit_index)); |
| 796 | |
| 797 | return 0; |
| 798 | } |
| 799 | |
| 800 | static int stm32_clk_probe(struct udevice *dev) |
| 801 | { |
| 802 | struct stm32_clk *priv = dev_get_priv(dev); |
| 803 | struct udevice *syscon; |
| 804 | fdt_addr_t addr; |
| 805 | int err; |
| 806 | |
| 807 | addr = dev_read_addr(dev); |
| 808 | if (addr == FDT_ADDR_T_NONE) |
| 809 | return -EINVAL; |
| 810 | |
| 811 | priv->rcc_base = (struct stm32_rcc_regs *)addr; |
| 812 | |
| 813 | /* get corresponding syscon phandle */ |
| 814 | err = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, |
| 815 | "st,syscfg", &syscon); |
| 816 | |
| 817 | if (err) { |
Patrick Delaunay | 88c7eb7 | 2020-11-06 19:01:47 +0100 | [diff] [blame] | 818 | dev_err(dev, "unable to find syscon device\n"); |
Patrice Chotard | 5fffeab | 2017-09-13 18:00:06 +0200 | [diff] [blame] | 819 | return err; |
| 820 | } |
| 821 | |
| 822 | priv->pwr_regmap = syscon_get_regmap(syscon); |
| 823 | if (!priv->pwr_regmap) { |
Patrick Delaunay | 88c7eb7 | 2020-11-06 19:01:47 +0100 | [diff] [blame] | 824 | dev_err(dev, "unable to find regmap\n"); |
Patrice Chotard | 5fffeab | 2017-09-13 18:00:06 +0200 | [diff] [blame] | 825 | return -ENODEV; |
| 826 | } |
| 827 | |
| 828 | configure_clocks(dev); |
| 829 | |
| 830 | return 0; |
| 831 | } |
| 832 | |
| 833 | static int stm32_clk_of_xlate(struct clk *clk, |
| 834 | struct ofnode_phandle_args *args) |
| 835 | { |
| 836 | if (args->args_count != 1) { |
Sean Anderson | a1b654b | 2021-12-01 14:26:53 -0500 | [diff] [blame] | 837 | dev_dbg(clk->dev, "Invalid args_count: %d\n", args->args_count); |
Patrice Chotard | 5fffeab | 2017-09-13 18:00:06 +0200 | [diff] [blame] | 838 | return -EINVAL; |
| 839 | } |
| 840 | |
| 841 | if (args->args_count) { |
| 842 | clk->id = args->args[0]; |
| 843 | /* |
| 844 | * this computation convert DT clock index which is used to |
| 845 | * point into 2 separate clock arrays (peripheral and kernel |
| 846 | * clocks bank) (see include/dt-bindings/clock/stm32h7-clks.h) |
| 847 | * into index to point into only one array where peripheral |
| 848 | * and kernel clocks are consecutive |
| 849 | */ |
| 850 | if (clk->id >= KERN_BANK) { |
| 851 | clk->id -= KERN_BANK; |
| 852 | clk->id += LAST_PERIF_BANK - PERIF_BANK + 1; |
| 853 | } else { |
| 854 | clk->id -= PERIF_BANK; |
| 855 | } |
| 856 | } else { |
| 857 | clk->id = 0; |
| 858 | } |
| 859 | |
Patrick Delaunay | 88c7eb7 | 2020-11-06 19:01:47 +0100 | [diff] [blame] | 860 | dev_dbg(clk->dev, "clk->id %ld\n", clk->id); |
Patrice Chotard | 5fffeab | 2017-09-13 18:00:06 +0200 | [diff] [blame] | 861 | |
| 862 | return 0; |
| 863 | } |
| 864 | |
| 865 | static struct clk_ops stm32_clk_ops = { |
| 866 | .of_xlate = stm32_clk_of_xlate, |
| 867 | .enable = stm32_clk_enable, |
| 868 | .get_rate = stm32_clk_get_rate, |
| 869 | }; |
| 870 | |
| 871 | U_BOOT_DRIVER(stm32h7_clk) = { |
| 872 | .name = "stm32h7_rcc_clock", |
| 873 | .id = UCLASS_CLK, |
| 874 | .ops = &stm32_clk_ops, |
| 875 | .probe = stm32_clk_probe, |
Simon Glass | 8a2b47f | 2020-12-03 16:55:17 -0700 | [diff] [blame] | 876 | .priv_auto = sizeof(struct stm32_clk), |
Patrice Chotard | 5fffeab | 2017-09-13 18:00:06 +0200 | [diff] [blame] | 877 | .flags = DM_FLAG_PRE_RELOC, |
| 878 | }; |