Jiaxun Yang | 8b31abf | 2024-06-18 14:56:07 +0100 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * Copyright (C) 2024 Jiaxun Yang <jiaxun.yang@flygoat.com> |
| 4 | */ |
| 5 | |
| 6 | #include <clk.h> |
| 7 | #include <cpu.h> |
| 8 | #include <dm.h> |
| 9 | #include <errno.h> |
| 10 | #include <linux/bitops.h> |
| 11 | #include <linux/err.h> |
| 12 | |
| 13 | #include <asm/arch/core.h> |
| 14 | |
| 15 | static int xtensa_cpu_get_desc(const struct udevice *dev, char *buf, int size) |
| 16 | { |
| 17 | const char *cpu = XCHAL_CORE_ID; |
| 18 | |
| 19 | if (!cpu || size < (strlen(cpu) + 1)) |
| 20 | return -ENOSPC; |
| 21 | |
| 22 | strcpy(buf, cpu); |
| 23 | |
| 24 | return 0; |
| 25 | } |
| 26 | |
| 27 | static int xtensa_cpu_get_info(const struct udevice *dev, struct cpu_info *info) |
| 28 | { |
| 29 | struct cpu_plat *plat = dev_get_parent_plat(dev); |
| 30 | |
| 31 | info->cpu_freq = plat->timebase_freq; |
| 32 | |
| 33 | #if XCHAL_HAVE_PTP_MMU |
| 34 | info->features |= BIT(CPU_FEAT_MMU); |
| 35 | #endif |
| 36 | #if XCHAL_ICACHE_SIZE || XCHAL_DCACHE_SIZE |
| 37 | info->features |= BIT(CPU_FEAT_L1_CACHE); |
| 38 | #endif |
| 39 | |
| 40 | return 0; |
| 41 | } |
| 42 | |
| 43 | static int xtensa_cpu_get_count(const struct udevice *dev) |
| 44 | { |
| 45 | ofnode node; |
| 46 | int num = 0; |
| 47 | |
| 48 | ofnode_for_each_subnode(node, dev_ofnode(dev->parent)) { |
| 49 | const char *device_type; |
| 50 | |
| 51 | /* skip if hart is marked as not available in the device tree */ |
| 52 | if (!ofnode_is_enabled(node)) |
| 53 | continue; |
| 54 | |
| 55 | device_type = ofnode_read_string(node, "device_type"); |
| 56 | if (!device_type) |
| 57 | continue; |
| 58 | if (strcmp(device_type, "cpu") == 0) |
| 59 | num++; |
| 60 | } |
| 61 | |
| 62 | return num; |
| 63 | } |
| 64 | |
| 65 | static int xtensa_cpu_bind(struct udevice *dev) |
| 66 | { |
| 67 | struct cpu_plat *plat = dev_get_parent_plat(dev); |
| 68 | |
| 69 | plat->cpu_id = dev_read_addr(dev); |
| 70 | |
| 71 | return 0; |
| 72 | } |
| 73 | |
| 74 | static int xtensa_cpu_probe(struct udevice *dev) |
| 75 | { |
| 76 | int ret = 0; |
| 77 | struct clk clk; |
| 78 | struct cpu_plat *plat = dev_get_parent_plat(dev); |
| 79 | |
| 80 | asm volatile ("rsr %0, 176\n" |
| 81 | "rsr %1, 208\n" |
| 82 | : "=r"(plat->id[0]), "=r"(plat->id[1])); |
| 83 | |
| 84 | /* Get a clock if it exists */ |
| 85 | ret = clk_get_by_index(dev, 0, &clk); |
| 86 | if (!ret) { |
| 87 | ret = clk_enable(&clk); |
| 88 | if (ret && (ret != -ENOSYS || ret != -ENOTSUPP)) |
| 89 | return ret; |
| 90 | ret = clk_get_rate(&clk); |
| 91 | if (!IS_ERR_VALUE(ret)) |
| 92 | plat->timebase_freq = ret; |
| 93 | } |
| 94 | |
| 95 | return 0; |
| 96 | } |
| 97 | |
| 98 | static const struct cpu_ops xtensa_cpu_ops = { |
| 99 | .get_desc = xtensa_cpu_get_desc, |
| 100 | .get_info = xtensa_cpu_get_info, |
| 101 | .get_count = xtensa_cpu_get_count, |
| 102 | }; |
| 103 | |
| 104 | static const struct udevice_id xtensa_cpu_ids[] = { |
| 105 | { .compatible = "cdns,xtensa-cpu" }, |
| 106 | { } |
| 107 | }; |
| 108 | |
| 109 | U_BOOT_DRIVER(xtensa_cpu) = { |
| 110 | .name = "xtensa_cpu", |
| 111 | .id = UCLASS_CPU, |
| 112 | .of_match = xtensa_cpu_ids, |
| 113 | .bind = xtensa_cpu_bind, |
| 114 | .probe = xtensa_cpu_probe, |
| 115 | .ops = &xtensa_cpu_ops, |
| 116 | .flags = DM_FLAG_PRE_RELOC, |
| 117 | }; |