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Lukasz Majewski4de44bb2019-06-24 15:50:45 +02001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2019 DENX Software Engineering
4 * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
5 */
6
Patrick Delaunay8767e792021-11-19 15:12:07 +01007#define LOG_CATEGORY UCLASS_CLK
8
Patrick Delaunay283dadf2021-11-19 15:12:06 +01009#include <clk.h>
Lukasz Majewski4de44bb2019-06-24 15:50:45 +020010#include <clk-uclass.h>
Simon Glass0f2af882020-05-10 11:40:05 -060011#include <log.h>
Lukasz Majewski4de44bb2019-06-24 15:50:45 +020012#include <dm/device.h>
13#include <dm/uclass.h>
14#include <dm/lists.h>
15#include <dm/device-internal.h>
Lukasz Majewski4de44bb2019-06-24 15:50:45 +020016
17int clk_register(struct clk *clk, const char *drv_name,
18 const char *name, const char *parent_name)
19{
Yang Xiwen470fba12023-11-11 03:19:52 +080020 struct udevice *parent = NULL;
Lukasz Majewski4de44bb2019-06-24 15:50:45 +020021 struct driver *drv;
22 int ret;
23
Yang Xiwen470fba12023-11-11 03:19:52 +080024 if (parent_name) {
25 ret = uclass_get_device_by_name(UCLASS_CLK, parent_name, &parent);
26 if (ret) {
27 log_err("%s: failed to get %s device (parent of %s)\n",
28 __func__, parent_name, name);
29 } else {
30 log_debug("%s: name: %s parent: %s [0x%p]\n", __func__, name,
31 parent->name, parent);
32 }
Peng Fanc179a172019-10-22 03:31:08 +000033 }
Lukasz Majewski4de44bb2019-06-24 15:50:45 +020034
Lukasz Majewski4de44bb2019-06-24 15:50:45 +020035 drv = lists_driver_lookup_name(drv_name);
36 if (!drv) {
Patrick Delaunay8767e792021-11-19 15:12:07 +010037 log_err("%s: %s is not a valid driver name\n",
38 __func__, drv_name);
Lukasz Majewski4de44bb2019-06-24 15:50:45 +020039 return -ENOENT;
40 }
41
Simon Glass6996c662020-11-28 17:50:03 -070042 ret = device_bind(parent, drv, name, NULL, ofnode_null(), &clk->dev);
Lukasz Majewski4de44bb2019-06-24 15:50:45 +020043 if (ret) {
Patrick Delaunay8767e792021-11-19 15:12:07 +010044 log_err("%s: CLK: %s driver bind error [%d]!\n", __func__, name,
45 ret);
Lukasz Majewski4de44bb2019-06-24 15:50:45 +020046 return ret;
47 }
48
Peng Fan30a6ebc2019-08-21 13:35:03 +000049 clk->enable_count = 0;
Simon Glass95588622020-12-22 19:30:28 -070050
Lukasz Majewski4de44bb2019-06-24 15:50:45 +020051 /* Store back pointer to clk from udevice */
Simon Glass95588622020-12-22 19:30:28 -070052 /* FIXME: This is not allowed...should be allocated by driver model */
53 dev_set_uclass_priv(clk->dev, clk);
Lukasz Majewski4de44bb2019-06-24 15:50:45 +020054
55 return 0;
56}
57
58ulong clk_generic_get_rate(struct clk *clk)
59{
60 return clk_get_parent_rate(clk);
61}
62
63const char *clk_hw_get_name(const struct clk *hw)
64{
Claudiu Beznead3e49d02020-09-07 17:46:32 +030065 assert(hw);
66 assert(hw->dev);
67
Lukasz Majewski4de44bb2019-06-24 15:50:45 +020068 return hw->dev->name;
69}
Peng Fan1d0a50a2019-07-31 07:01:23 +000070
71bool clk_dev_binded(struct clk *clk)
72{
Simon Glass6211d762020-12-19 10:40:10 -070073 if (clk->dev && (dev_get_flags(clk->dev) & DM_FLAG_BOUND))
Peng Fan1d0a50a2019-07-31 07:01:23 +000074 return true;
75
76 return false;
77}
Sean Anderson46596122022-03-20 16:34:45 -040078
79/* Helper functions for clock ops */
80
81ulong ccf_clk_get_rate(struct clk *clk)
82{
83 struct clk *c;
84 int err = clk_get_by_id(clk->id, &c);
85
86 if (err)
87 return err;
88 return clk_get_rate(c);
89}
90
91ulong ccf_clk_set_rate(struct clk *clk, unsigned long rate)
92{
93 struct clk *c;
94 int err = clk_get_by_id(clk->id, &c);
95
96 if (err)
97 return err;
98 return clk_set_rate(c, rate);
99}
100
101int ccf_clk_set_parent(struct clk *clk, struct clk *parent)
102{
103 struct clk *c, *p;
104 int err = clk_get_by_id(clk->id, &c);
105
106 if (err)
107 return err;
108
109 err = clk_get_by_id(parent->id, &p);
110 if (err)
111 return err;
112
113 return clk_set_parent(c, p);
114}
115
116static int ccf_clk_endisable(struct clk *clk, bool enable)
117{
118 struct clk *c;
119 int err = clk_get_by_id(clk->id, &c);
120
121 if (err)
122 return err;
123 return enable ? clk_enable(c) : clk_disable(c);
124}
125
126int ccf_clk_enable(struct clk *clk)
127{
128 return ccf_clk_endisable(clk, true);
129}
130
131int ccf_clk_disable(struct clk *clk)
132{
133 return ccf_clk_endisable(clk, false);
134}
135
136const struct clk_ops ccf_clk_ops = {
137 .set_rate = ccf_clk_set_rate,
138 .get_rate = ccf_clk_get_rate,
139 .set_parent = ccf_clk_set_parent,
140 .enable = ccf_clk_enable,
141 .disable = ccf_clk_disable,
142};