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git01.mediatek.com / filogic / uboot / 32c544d04a51021ec6e8ec3b18bc4d4ad7b34d9c / . / include / configs / tegra30-common.h
blob: c2096fbe7ec497660f062bdc56498acbe364f1de [file] [log] [blame]
Tom Warren23d7fe92012-12-11 13:34:18 +0000[diff] [blame]1/*
2 * (C) Copyright 2010-2012
3 * NVIDIA Corporation <www.nvidia.com>
4 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]5 * SPDX-License-Identifier: GPL-2.0+
Tom Warren23d7fe92012-12-11 13:34:18 +0000[diff] [blame]6 */
7
8#ifndef _TEGRA30_COMMON_H_
9#define _TEGRA30_COMMON_H_
10#include "tegra-common.h"
11
12/*
13 * NS16550 Configuration
14 */
15#define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */
16
Tom Warren23d7fe92012-12-11 13:34:18 +0000[diff] [blame]17/*
18 * Miscellaneous configurable options
19 */
Tom Warren23d7fe92012-12-11 13:34:18 +0000[diff] [blame]20#define CONFIG_STACKBASE 0x82800000 /* 40MB */
21
22/*-----------------------------------------------------------------------
23 * Physical Memory Map
24 */
Stephen Warrenf5bd7452015-09-23 12:34:01 -0600[diff] [blame]25#define CONFIG_SYS_TEXT_BASE 0x80110000
Tom Warren23d7fe92012-12-11 13:34:18 +0000[diff] [blame]26
27/*
28 * Memory layout for where various images get loaded by boot scripts:
29 *
30 * scriptaddr can be pretty much anywhere that doesn't conflict with something
31 * else. Put it above BOOTMAPSZ to eliminate conflicts.
32 *
Stephen Warren7434dfe2014-02-05 09:24:59 -0700[diff] [blame]33 * pxefile_addr_r can be pretty much anywhere that doesn't conflict with
34 * something else. Put it above BOOTMAPSZ to eliminate conflicts.
35 *
Tom Warren23d7fe92012-12-11 13:34:18 +0000[diff] [blame]36 * kernel_addr_r must be within the first 128M of RAM in order for the
37 * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
38 * decompress itself to 0x8000 after the start of RAM, kernel_addr_r
39 * should not overlap that area, or the kernel will have to copy itself
40 * somewhere else before decompression. Similarly, the address of any other
41 * data passed to the kernel shouldn't overlap the start of RAM. Pushing
42 * this up to 16M allows for a sizable kernel to be decompressed below the
43 * compressed load address.
44 *
45 * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for
46 * the compressed kernel to be up to 16M too.
47 *
48 * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
49 * for the FDT/DTB to be up to 1M, which is hopefully plenty.
50 */
Stephen Warrenf61f1292015-04-01 15:40:53 -0600[diff] [blame]51#define CONFIG_LOADADDR 0x81000000
Tom Warren23d7fe92012-12-11 13:34:18 +0000[diff] [blame]52#define MEM_LAYOUT_ENV_SETTINGS \
53 "scriptaddr=0x90000000\0" \
Stephen Warren7434dfe2014-02-05 09:24:59 -0700[diff] [blame]54 "pxefile_addr_r=0x90100000\0" \
Stephen Warrenf61f1292015-04-01 15:40:53 -0600[diff] [blame]55 "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
Tom Warren23d7fe92012-12-11 13:34:18 +0000[diff] [blame]56 "fdt_addr_r=0x82000000\0" \
57 "ramdisk_addr_r=0x82100000\0"
58
59/* Defines for SPL */
60#define CONFIG_SPL_TEXT_BASE 0x80108000
61#define CONFIG_SYS_SPL_MALLOC_START 0x80090000
62#define CONFIG_SPL_STACK 0x800ffffc
63
Jim Lin68c0c02c2013-06-21 19:05:48 +0800[diff] [blame]64/* For USB EHCI controller */
65#define CONFIG_EHCI_IS_TDI
Jim Lincbb4c5e2013-11-06 14:03:44 +0800[diff] [blame]66#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10
Jim Lin68c0c02c2013-06-21 19:05:48 +0800[diff] [blame]67
Tom Warren23d7fe92012-12-11 13:34:18 +0000[diff] [blame]68#endif /* _TEGRA30_COMMON_H_ */