Vikas Manocha | 33913c5 | 2014-11-18 10:42:22 -0800 | [diff] [blame] | 1 | /* |
Patrice Chotard | cc55116 | 2017-10-23 09:53:59 +0200 | [diff] [blame] | 2 | * Copyright (C) 2014, STMicroelectronics - All Rights Reserved |
| 3 | * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics. |
Vikas Manocha | 33913c5 | 2014-11-18 10:42:22 -0800 | [diff] [blame] | 4 | * |
| 5 | * SPDX-License-Identifier: GPL-2.0+ |
| 6 | */ |
| 7 | |
| 8 | #ifndef __CONFIG_STV0991_H |
| 9 | #define __CONFIG_STV0991_H |
Vikas Manocha | 33913c5 | 2014-11-18 10:42:22 -0800 | [diff] [blame] | 10 | #define CONFIG_SYS_DCACHE_OFF |
Vikas Manocha | 33913c5 | 2014-11-18 10:42:22 -0800 | [diff] [blame] | 11 | #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH |
Vikas Manocha | 32b9e71 | 2014-11-18 10:42:23 -0800 | [diff] [blame] | 12 | |
Vikas Manocha | 33913c5 | 2014-11-18 10:42:22 -0800 | [diff] [blame] | 13 | #define CONFIG_SYS_CORTEX_R4 |
| 14 | |
Vikas Manocha | 33913c5 | 2014-11-18 10:42:22 -0800 | [diff] [blame] | 15 | /* ram memory-related information */ |
| 16 | #define CONFIG_NR_DRAM_BANKS 1 |
| 17 | #define PHYS_SDRAM_1 0x00000000 |
| 18 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 |
| 19 | #define PHYS_SDRAM_1_SIZE 0x00198000 |
| 20 | |
| 21 | #define CONFIG_ENV_SIZE 0x10000 |
Vikas Manocha | f653353 | 2015-07-02 18:29:37 -0700 | [diff] [blame] | 22 | #define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE |
| 23 | #define CONFIG_ENV_OFFSET 0x30000 |
Vikas Manocha | 33913c5 | 2014-11-18 10:42:22 -0800 | [diff] [blame] | 24 | #define CONFIG_ENV_ADDR \ |
| 25 | (PHYS_SDRAM_1_SIZE - CONFIG_ENV_SIZE) |
Vikas Manocha | 33913c5 | 2014-11-18 10:42:22 -0800 | [diff] [blame] | 26 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024) |
| 27 | |
| 28 | /* serial port (PL011) configuration */ |
Vikas Manocha | 0860b6a | 2014-12-01 12:27:54 -0800 | [diff] [blame] | 29 | #define CONFIG_PL01X_SERIAL |
Vikas Manocha | 33913c5 | 2014-11-18 10:42:22 -0800 | [diff] [blame] | 30 | |
| 31 | /* user interface */ |
Vikas Manocha | 7f34a69 | 2014-11-18 10:42:24 -0800 | [diff] [blame] | 32 | #define CONFIG_SYS_CBSIZE 1024 |
Vikas Manocha | 33913c5 | 2014-11-18 10:42:22 -0800 | [diff] [blame] | 33 | |
| 34 | /* MISC */ |
| 35 | #define CONFIG_SYS_LOAD_ADDR 0x00000000 |
Vikas Manocha | d70864c | 2014-12-01 12:27:53 -0800 | [diff] [blame] | 36 | #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 |
Vikas Manocha | 33913c5 | 2014-11-18 10:42:22 -0800 | [diff] [blame] | 37 | #define CONFIG_SYS_INIT_RAM_ADDR 0x00190000 |
| 38 | #define CONFIG_SYS_INIT_SP_OFFSET \ |
| 39 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
Bin Meng | 7557405 | 2016-02-05 19:30:11 -0800 | [diff] [blame] | 40 | /* U-Boot Load Address */ |
Vikas Manocha | 33913c5 | 2014-11-18 10:42:22 -0800 | [diff] [blame] | 41 | #define CONFIG_SYS_TEXT_BASE 0x00010000 |
| 42 | #define CONFIG_SYS_INIT_SP_ADDR \ |
| 43 | (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) |
| 44 | |
Vikas Manocha | 32b9e71 | 2014-11-18 10:42:23 -0800 | [diff] [blame] | 45 | /* GMAC related configs */ |
| 46 | |
| 47 | #define CONFIG_MII |
Vikas Manocha | 32b9e71 | 2014-11-18 10:42:23 -0800 | [diff] [blame] | 48 | #define CONFIG_DW_ALTDESCRIPTOR |
Vikas Manocha | 32b9e71 | 2014-11-18 10:42:23 -0800 | [diff] [blame] | 49 | |
| 50 | /* Command support defines */ |
Vikas Manocha | 32b9e71 | 2014-11-18 10:42:23 -0800 | [diff] [blame] | 51 | #define CONFIG_PHY_RESET_DELAY 10000 /* in usec */ |
| 52 | |
Vikas Manocha | 7f34a69 | 2014-11-18 10:42:24 -0800 | [diff] [blame] | 53 | #define CONFIG_SYS_MEMTEST_START 0x0000 |
| 54 | #define CONFIG_SYS_MEMTEST_END 1024*1024 |
Vikas Manocha | 7f34a69 | 2014-11-18 10:42:24 -0800 | [diff] [blame] | 55 | |
| 56 | /* Misc configuration */ |
| 57 | #define CONFIG_SYS_LONGHELP |
| 58 | #define CONFIG_CMDLINE_EDITING |
| 59 | |
Vikas Manocha | 7f34a69 | 2014-11-18 10:42:24 -0800 | [diff] [blame] | 60 | #define CONFIG_BOOTCOMMAND "go 0x40040000" |
Stefan Roese | 83da3f1 | 2015-05-18 14:08:23 +0200 | [diff] [blame] | 61 | |
Vikas Manocha | 8cc062f | 2015-07-02 18:29:41 -0700 | [diff] [blame] | 62 | /* |
| 63 | + * QSPI support |
| 64 | + */ |
| 65 | #ifdef CONFIG_OF_CONTROL /* QSPI is controlled via DT */ |
Vikas Manocha | 8cc062f | 2015-07-02 18:29:41 -0700 | [diff] [blame] | 66 | #define CONFIG_CQSPI_DECODER 0 |
| 67 | #define CONFIG_CQSPI_REF_CLK ((30/4)/2)*1000*1000 |
Vignesh R | 4f06bf2 | 2016-12-21 10:42:32 +0530 | [diff] [blame] | 68 | #define CONFIG_BOUNCE_BUFFER |
Vikas Manocha | 8cc062f | 2015-07-02 18:29:41 -0700 | [diff] [blame] | 69 | |
Vikas Manocha | 8cc062f | 2015-07-02 18:29:41 -0700 | [diff] [blame] | 70 | #endif |
| 71 | |
Vikas Manocha | 33913c5 | 2014-11-18 10:42:22 -0800 | [diff] [blame] | 72 | #endif /* __CONFIG_H */ |