blob: 827bfad521d47414ff8236bdeb894f4f9ec36411 [file] [log] [blame]
York Sune12abcb2015-03-20 19:28:24 -07001/*
Priyanka Jaind1587182017-04-25 10:12:31 +05302 * Copyright (C) 2017 NXP Semiconductors
York Sune12abcb2015-03-20 19:28:24 -07003 * Copyright 2015 Freescale Semiconductor
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7#include <common.h>
8#include <malloc.h>
9#include <errno.h>
10#include <netdev.h>
11#include <fsl_ifc.h>
12#include <fsl_ddr.h>
13#include <asm/io.h>
Yangbo Lucf005552015-05-28 14:53:55 +053014#include <hwconfig.h>
York Sune12abcb2015-03-20 19:28:24 -070015#include <fdt_support.h>
16#include <libfdt.h>
York Sune12abcb2015-03-20 19:28:24 -070017#include <fsl-mc/fsl_mc.h>
18#include <environment.h>
Alexander Graf34f8e972016-11-17 01:02:59 +010019#include <efi_loader.h>
York Sune12abcb2015-03-20 19:28:24 -070020#include <i2c.h>
York Sun729f2d12017-03-06 09:02:34 -080021#include <asm/arch/mmu.h>
Mingkai Hu0e58b512015-10-26 19:47:50 +080022#include <asm/arch/soc.h>
Santan Kumarc61c6992017-03-07 11:21:03 +053023#include <asm/arch/ppa.h>
Saksham Jainc0c38d22016-03-23 16:24:35 +053024#include <fsl_sec.h>
York Sune12abcb2015-03-20 19:28:24 -070025
Priyanka Jain6720d0a2017-04-28 10:41:34 +053026#ifdef CONFIG_FSL_QIXIS
York Sune12abcb2015-03-20 19:28:24 -070027#include "../common/qixis.h"
Prabhakar Kushwaha122bcfd2015-11-09 16:42:07 +053028#include "ls2080ardb_qixis.h"
Priyanka Jain6720d0a2017-04-28 10:41:34 +053029#endif
Rai Harninder6aa1f3b2016-03-23 17:04:38 +053030#include "../common/vid.h"
York Sune12abcb2015-03-20 19:28:24 -070031
Yangbo Lucf005552015-05-28 14:53:55 +053032#define PIN_MUX_SEL_SDHC 0x00
Haikun.Wang@freescale.comb8a258c2015-06-26 19:58:24 +080033#define PIN_MUX_SEL_DSPI 0x0a
Yangbo Lucf005552015-05-28 14:53:55 +053034
35#define SET_SDHC_MUX_SEL(reg, value) ((reg & 0xf0) | value)
York Sune12abcb2015-03-20 19:28:24 -070036DECLARE_GLOBAL_DATA_PTR;
37
Yangbo Lucf005552015-05-28 14:53:55 +053038enum {
39 MUX_TYPE_SDHC,
Haikun.Wang@freescale.comb8a258c2015-06-26 19:58:24 +080040 MUX_TYPE_DSPI,
Yangbo Lucf005552015-05-28 14:53:55 +053041};
42
York Sune12abcb2015-03-20 19:28:24 -070043unsigned long long get_qixis_addr(void)
44{
45 unsigned long long addr;
46
47 if (gd->flags & GD_FLG_RELOC)
48 addr = QIXIS_BASE_PHYS;
49 else
50 addr = QIXIS_BASE_PHYS_EARLY;
51
52 /*
53 * IFC address under 256MB is mapped to 0x30000000, any address above
54 * is mapped to 0x5_10000000 up to 4GB.
55 */
56 addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
57
58 return addr;
59}
60
61int checkboard(void)
62{
Priyanka Jain6720d0a2017-04-28 10:41:34 +053063#ifdef CONFIG_FSL_QIXIS
York Sune12abcb2015-03-20 19:28:24 -070064 u8 sw;
Priyanka Jain6720d0a2017-04-28 10:41:34 +053065#endif
Prabhakar Kushwaha67f2e9c2015-05-28 14:54:07 +053066 char buf[15];
67
68 cpu_name(buf);
69 printf("Board: %s-RDB, ", buf);
York Sune12abcb2015-03-20 19:28:24 -070070
Priyanka Jain75cd67f2017-04-27 15:08:07 +053071#ifdef CONFIG_TARGET_LS2081ARDB
Priyanka Jain6720d0a2017-04-28 10:41:34 +053072#ifdef CONFIG_FSL_QIXIS
York Sune12abcb2015-03-20 19:28:24 -070073 sw = QIXIS_READ(arch);
York Sune12abcb2015-03-20 19:28:24 -070074 printf("Board Arch: V%d, ", sw >> 4);
Priyanka Jain75cd67f2017-04-27 15:08:07 +053075 printf("Board version: %c, ", (sw & 0xf) + 'A');
76
77 sw = QIXIS_READ(brdcfg[0]);
78 sw = (sw & QIXIS_QMAP_MASK) >> QIXIS_QMAP_SHIFT;
79 switch (sw) {
80 case 0:
81 puts("boot from QSPI DEV#0\n");
82 puts("QSPI_CSA_1 mapped to QSPI DEV#1\n");
83 break;
84 case 1:
85 puts("boot from QSPI DEV#1\n");
86 puts("QSPI_CSA_1 mapped to QSPI DEV#0\n");
87 break;
88 case 2:
89 puts("boot from QSPI EMU\n");
90 puts("QSPI_CSA_1 mapped to QSPI DEV#0\n");
91 break;
92 case 3:
93 puts("boot from QSPI EMU\n");
94 puts("QSPI_CSA_1 mapped to QSPI DEV#1\n");
95 break;
96 case 4:
97 puts("boot from QSPI DEV#0\n");
98 puts("QSPI_CSA_1 mapped to QSPI EMU\n");
99 break;
100 default:
101 printf("invalid setting of SW%u\n", sw);
102 break;
103 }
104#endif
105 puts("SERDES1 Reference : ");
106 printf("Clock1 = 100MHz ");
107 printf("Clock2 = 161.13MHz");
108#else
109#ifdef CONFIG_FSL_QIXIS
110 sw = QIXIS_READ(arch);
111 printf("Board Arch: V%d, ", sw >> 4);
Prabhakar Kushwaha8368a592015-05-28 14:54:04 +0530112 printf("Board version: %c, boot from ", (sw & 0xf) + 'A');
York Sune12abcb2015-03-20 19:28:24 -0700113
114 sw = QIXIS_READ(brdcfg[0]);
115 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
116
117 if (sw < 0x8)
118 printf("vBank: %d\n", sw);
119 else if (sw == 0x9)
120 puts("NAND\n");
121 else
122 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
123
124 printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
Priyanka Jain6720d0a2017-04-28 10:41:34 +0530125#endif
York Sune12abcb2015-03-20 19:28:24 -0700126 puts("SERDES1 Reference : ");
127 printf("Clock1 = 156.25MHz ");
128 printf("Clock2 = 156.25MHz");
Priyanka Jain75cd67f2017-04-27 15:08:07 +0530129#endif
York Sune12abcb2015-03-20 19:28:24 -0700130
131 puts("\nSERDES2 Reference : ");
132 printf("Clock1 = 100MHz ");
133 printf("Clock2 = 100MHz\n");
134
135 return 0;
136}
137
138unsigned long get_board_sys_clk(void)
139{
Priyanka Jain6720d0a2017-04-28 10:41:34 +0530140#ifdef CONFIG_FSL_QIXIS
York Sune12abcb2015-03-20 19:28:24 -0700141 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
142
143 switch (sysclk_conf & 0x0F) {
144 case QIXIS_SYSCLK_83:
145 return 83333333;
146 case QIXIS_SYSCLK_100:
147 return 100000000;
148 case QIXIS_SYSCLK_125:
149 return 125000000;
150 case QIXIS_SYSCLK_133:
151 return 133333333;
152 case QIXIS_SYSCLK_150:
153 return 150000000;
154 case QIXIS_SYSCLK_160:
155 return 160000000;
156 case QIXIS_SYSCLK_166:
157 return 166666666;
158 }
Priyanka Jain6720d0a2017-04-28 10:41:34 +0530159#endif
160 return 100000000;
York Sune12abcb2015-03-20 19:28:24 -0700161}
162
163int select_i2c_ch_pca9547(u8 ch)
164{
165 int ret;
166
167 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
168 if (ret) {
169 puts("PCA: failed to select proper channel\n");
170 return ret;
171 }
172
173 return 0;
174}
175
Rai Harninder6aa1f3b2016-03-23 17:04:38 +0530176int i2c_multiplexer_select_vid_channel(u8 channel)
177{
178 return select_i2c_ch_pca9547(channel);
179}
180
Yangbo Lucf005552015-05-28 14:53:55 +0530181int config_board_mux(int ctrl_type)
182{
Priyanka Jain6720d0a2017-04-28 10:41:34 +0530183#ifdef CONFIG_FSL_QIXIS
Yangbo Lucf005552015-05-28 14:53:55 +0530184 u8 reg5;
185
186 reg5 = QIXIS_READ(brdcfg[5]);
187
188 switch (ctrl_type) {
189 case MUX_TYPE_SDHC:
190 reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC);
191 break;
Haikun.Wang@freescale.comb8a258c2015-06-26 19:58:24 +0800192 case MUX_TYPE_DSPI:
193 reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_DSPI);
194 break;
Yangbo Lucf005552015-05-28 14:53:55 +0530195 default:
196 printf("Wrong mux interface type\n");
197 return -1;
198 }
199
200 QIXIS_WRITE(brdcfg[5], reg5);
Priyanka Jain6720d0a2017-04-28 10:41:34 +0530201#endif
Haikun.Wang@freescale.comb8a258c2015-06-26 19:58:24 +0800202 return 0;
203}
204
205int board_init(void)
206{
York Sun8cbc1952016-05-26 13:59:03 -0700207#ifdef CONFIG_FSL_MC_ENET
Shaohui Xie8c7ce822016-01-28 15:38:15 +0800208 u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
York Sun8cbc1952016-05-26 13:59:03 -0700209#endif
Haikun.Wang@freescale.comb8a258c2015-06-26 19:58:24 +0800210
211 init_final_memctl_regs();
212
Haikun.Wang@freescale.comb8a258c2015-06-26 19:58:24 +0800213#ifdef CONFIG_ENV_IS_NOWHERE
214 gd->env_addr = (ulong)&default_environment[0];
215#endif
216 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
217
Priyanka Jain6720d0a2017-04-28 10:41:34 +0530218#ifdef CONFIG_FSL_QIXIS
Haikun.Wang@freescale.comb8a258c2015-06-26 19:58:24 +0800219 QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN);
Priyanka Jain6720d0a2017-04-28 10:41:34 +0530220#endif
Udit Agarwalc83ea8a2017-08-16 07:13:29 -0400221
222#ifdef CONFIG_FSL_CAAM
223 sec_init();
224#endif
Santan Kumarc61c6992017-03-07 11:21:03 +0530225#ifdef CONFIG_FSL_LS_PPA
226 ppa_init();
227#endif
228
York Sun8cbc1952016-05-26 13:59:03 -0700229#ifdef CONFIG_FSL_MC_ENET
Shaohui Xie8c7ce822016-01-28 15:38:15 +0800230 /* invert AQR405 IRQ pins polarity */
231 out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK);
York Sun8cbc1952016-05-26 13:59:03 -0700232#endif
Udit Agarwal62ed9a82017-02-03 22:53:38 +0530233#ifdef CONFIG_FSL_CAAM
234 sec_init();
235#endif
Shaohui Xie8c7ce822016-01-28 15:38:15 +0800236
Haikun.Wang@freescale.comb8a258c2015-06-26 19:58:24 +0800237 return 0;
238}
239
240int board_early_init_f(void)
241{
Priyanka Jain75cd67f2017-04-27 15:08:07 +0530242#ifdef CONFIG_SYS_I2C_EARLY_INIT
243 i2c_early_init_f();
244#endif
Haikun.Wang@freescale.comb8a258c2015-06-26 19:58:24 +0800245 fsl_lsch3_early_init_f();
Yangbo Lucf005552015-05-28 14:53:55 +0530246 return 0;
247}
248
249int misc_init_r(void)
250{
Santan Kumar0ce3f402017-06-15 17:07:01 +0530251 char *env_hwconfig;
252 u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
253 u32 val;
Priyanka Jain0915dda2017-09-15 10:19:48 +0530254 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
255 u32 svr = gur_in32(&gur->svr);
Santan Kumar0ce3f402017-06-15 17:07:01 +0530256
257 val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4);
258
Simon Glass64b723f2017-08-03 12:22:12 -0600259 env_hwconfig = env_get("hwconfig");
Santan Kumar0ce3f402017-06-15 17:07:01 +0530260
261 if (hwconfig_f("dspi", env_hwconfig) &&
262 DCFG_RCWSR13_DSPI == (val & (u32)(0xf << 8)))
263 config_board_mux(MUX_TYPE_DSPI);
264 else
265 config_board_mux(MUX_TYPE_SDHC);
266
Priyanka Jain75cd67f2017-04-27 15:08:07 +0530267 /*
Santan Kumar20e7f5a2017-06-09 11:48:05 +0530268 * LS2081ARDB RevF board has smart voltage translator
Priyanka Jaind1587182017-04-25 10:12:31 +0530269 * which needs to be programmed to enable high speed SD interface
270 * by setting GPIO4_10 output to zero
271 */
Santan Kumar20e7f5a2017-06-09 11:48:05 +0530272#ifdef CONFIG_TARGET_LS2081ARDB
Priyanka Jaind1587182017-04-25 10:12:31 +0530273 out_le32(GPIO4_GPDIR_ADDR, (1 << 21 |
274 in_le32(GPIO4_GPDIR_ADDR)));
275 out_le32(GPIO4_GPDAT_ADDR, (~(1 << 21) &
276 in_le32(GPIO4_GPDAT_ADDR)));
Priyanka Jain75cd67f2017-04-27 15:08:07 +0530277#endif
Yangbo Lucf005552015-05-28 14:53:55 +0530278 if (hwconfig("sdhc"))
279 config_board_mux(MUX_TYPE_SDHC);
280
Rai Harninder6aa1f3b2016-03-23 17:04:38 +0530281 if (adjust_vdd(0))
282 printf("Warning: Adjusting core voltage failed.\n");
Priyanka Jain0915dda2017-09-15 10:19:48 +0530283 /*
284 * Default value of board env is based on filename which is
285 * ls2080ardb. Modify board env for other supported SoCs
286 */
287 if ((SVR_SOC_VER(svr) == SVR_LS2088A) ||
288 (SVR_SOC_VER(svr) == SVR_LS2048A))
289 env_set("board", "ls2088ardb");
290 else if ((SVR_SOC_VER(svr) == SVR_LS2081A) ||
291 (SVR_SOC_VER(svr) == SVR_LS2041A))
292 env_set("board", "ls2081ardb");
Rai Harninder6aa1f3b2016-03-23 17:04:38 +0530293
Yangbo Lucf005552015-05-28 14:53:55 +0530294 return 0;
295}
296
York Sune12abcb2015-03-20 19:28:24 -0700297void detail_board_ddr_info(void)
298{
299 puts("\nDDR ");
300 print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
301 print_ddr_info(0);
Prabhakar Kushwaha122bcfd2015-11-09 16:42:07 +0530302#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
York Suncbe8e1c2016-04-04 11:41:26 -0700303 if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) {
York Sune12abcb2015-03-20 19:28:24 -0700304 puts("\nDP-DDR ");
305 print_size(gd->bd->bi_dram[2].size, "");
306 print_ddr_info(CONFIG_DP_DDR_CTRL);
307 }
Prabhakar Kushwaha122bcfd2015-11-09 16:42:07 +0530308#endif
York Sune12abcb2015-03-20 19:28:24 -0700309}
310
York Sune12abcb2015-03-20 19:28:24 -0700311#if defined(CONFIG_ARCH_MISC_INIT)
312int arch_misc_init(void)
313{
York Sune12abcb2015-03-20 19:28:24 -0700314 return 0;
315}
316#endif
317
York Sune12abcb2015-03-20 19:28:24 -0700318#ifdef CONFIG_FSL_MC_ENET
319void fdt_fixup_board_enet(void *fdt)
320{
321 int offset;
322
Stuart Yodera3466152016-03-02 16:37:13 -0600323 offset = fdt_path_offset(fdt, "/soc/fsl-mc");
York Sune12abcb2015-03-20 19:28:24 -0700324
325 if (offset < 0)
Stuart Yodera3466152016-03-02 16:37:13 -0600326 offset = fdt_path_offset(fdt, "/fsl-mc");
York Sune12abcb2015-03-20 19:28:24 -0700327
328 if (offset < 0) {
329 printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
330 __func__, offset);
331 return;
332 }
333
334 if (get_mc_boot_status() == 0)
335 fdt_status_okay(fdt, offset);
336 else
337 fdt_status_fail(fdt, offset);
338}
Alexander Graf2ebeb442016-11-17 01:02:57 +0100339
340void board_quiesce_devices(void)
341{
342 fsl_mc_ldpaa_exit(gd->bd);
343}
York Sune12abcb2015-03-20 19:28:24 -0700344#endif
345
346#ifdef CONFIG_OF_BOARD_SETUP
Santan Kumar39ea8bf2017-07-05 18:05:08 +0530347void fsl_fdt_fixup_flash(void *fdt)
348{
349 int offset;
350
351/*
352 * IFC and QSPI are muxed on board.
353 * So disable IFC node in dts if QSPI is enabled or
354 * disable QSPI node in dts in case QSPI is not enabled.
355 */
356#ifdef CONFIG_FSL_QSPI
357 offset = fdt_path_offset(fdt, "/soc/ifc");
358
359 if (offset < 0)
360 offset = fdt_path_offset(fdt, "/ifc");
361#else
362 offset = fdt_path_offset(fdt, "/soc/quadspi");
363
364 if (offset < 0)
365 offset = fdt_path_offset(fdt, "/quadspi");
366#endif
367 if (offset < 0)
368 return;
369
370 fdt_status_disabled(fdt, offset);
371}
372
York Sune12abcb2015-03-20 19:28:24 -0700373int ft_board_setup(void *blob, bd_t *bd)
374{
Bhupesh Sharma0b10a1a2015-05-28 14:54:10 +0530375 u64 base[CONFIG_NR_DRAM_BANKS];
376 u64 size[CONFIG_NR_DRAM_BANKS];
York Sune12abcb2015-03-20 19:28:24 -0700377
378 ft_cpu_setup(blob, bd);
379
Bhupesh Sharma0b10a1a2015-05-28 14:54:10 +0530380 /* fixup DT for the two GPP DDR banks */
381 base[0] = gd->bd->bi_dram[0].start;
382 size[0] = gd->bd->bi_dram[0].size;
383 base[1] = gd->bd->bi_dram[1].start;
384 size[1] = gd->bd->bi_dram[1].size;
385
York Sun4de24ef2017-03-06 09:02:28 -0800386#ifdef CONFIG_RESV_RAM
387 /* reduce size if reserved memory is within this bank */
388 if (gd->arch.resv_ram >= base[0] &&
389 gd->arch.resv_ram < base[0] + size[0])
390 size[0] = gd->arch.resv_ram - base[0];
391 else if (gd->arch.resv_ram >= base[1] &&
392 gd->arch.resv_ram < base[1] + size[1])
393 size[1] = gd->arch.resv_ram - base[1];
394#endif
395
Bhupesh Sharma0b10a1a2015-05-28 14:54:10 +0530396 fdt_fixup_memory_banks(blob, base, size, 2);
York Sune12abcb2015-03-20 19:28:24 -0700397
Sriram Dash9fd465c2016-09-16 17:12:15 +0530398 fsl_fdt_fixup_dr_usb(blob, bd);
Sriram Dash01820952016-06-13 09:58:36 +0530399
Santan Kumar39ea8bf2017-07-05 18:05:08 +0530400 fsl_fdt_fixup_flash(blob);
401
York Sune12abcb2015-03-20 19:28:24 -0700402#ifdef CONFIG_FSL_MC_ENET
403 fdt_fixup_board_enet(blob);
York Sune12abcb2015-03-20 19:28:24 -0700404#endif
405
406 return 0;
407}
408#endif
409
410void qixis_dump_switch(void)
411{
Priyanka Jain6720d0a2017-04-28 10:41:34 +0530412#ifdef CONFIG_FSL_QIXIS
York Sune12abcb2015-03-20 19:28:24 -0700413 int i, nr_of_cfgsw;
414
415 QIXIS_WRITE(cms[0], 0x00);
416 nr_of_cfgsw = QIXIS_READ(cms[1]);
417
418 puts("DIP switch settings dump:\n");
419 for (i = 1; i <= nr_of_cfgsw; i++) {
420 QIXIS_WRITE(cms[0], i);
421 printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
422 }
Priyanka Jain6720d0a2017-04-28 10:41:34 +0530423#endif
York Sune12abcb2015-03-20 19:28:24 -0700424}
York Sunac192a92015-05-28 14:54:09 +0530425
426/*
427 * Board rev C and earlier has duplicated I2C addresses for 2nd controller.
428 * Both slots has 0x54, resulting 2nd slot unusable.
429 */
430void update_spd_address(unsigned int ctrl_num,
431 unsigned int slot,
432 unsigned int *addr)
433{
Priyanka Jain75cd67f2017-04-27 15:08:07 +0530434#ifndef CONFIG_TARGET_LS2081ARDB
Priyanka Jain6720d0a2017-04-28 10:41:34 +0530435#ifdef CONFIG_FSL_QIXIS
York Sunac192a92015-05-28 14:54:09 +0530436 u8 sw;
437
438 sw = QIXIS_READ(arch);
439 if ((sw & 0xf) < 0x3) {
440 if (ctrl_num == 1 && slot == 0)
441 *addr = SPD_EEPROM_ADDRESS4;
442 else if (ctrl_num == 1 && slot == 1)
443 *addr = SPD_EEPROM_ADDRESS3;
444 }
Priyanka Jain6720d0a2017-04-28 10:41:34 +0530445#endif
Priyanka Jain75cd67f2017-04-27 15:08:07 +0530446#endif
York Sunac192a92015-05-28 14:54:09 +0530447}