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git01.mediatek.com / filogic / uboot / 32c25c80bf49970528f92bf8682b81e4e70a6d59 / . / arch / arm / dts / fsl-lx2160a-rdb.dts
blob: 399409776e74395f1b24865528f51ec1b57bb575 [file] [log] [blame]
Priyanka Jainfd45ca02018-11-28 13:04:27 +0000[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+ OR X11
2/*
3 * NXP LX2160ARDB device tree source
4 *
5 * Author: Priyanka Jain <priyanka.jain@nxp.com>
6 * Sriram Dash <sriram.dash@nxp.com>
7 *
8 * Copyright 2018 NXP
9 *
10 */
11
12/dts-v1/;
13
14#include "fsl-lx2160a.dtsi"
15
16/ {
17 model = "NXP Layerscape LX2160ARDB Board";
18 compatible = "fsl,lx2160ardb", "fsl,lx2160a";
Kuldeep Singh6b614242019-11-06 16:38:01 +0530[diff] [blame]19 aliases {
20 spi0 = &fspi;
21 };
Priyanka Jainfd45ca02018-11-28 13:04:27 +0000[diff] [blame]22};
23
Ioana Ciorneibcf6a9d2020-03-18 16:47:44 +0200[diff] [blame]24&dpmac3 {
25 status = "okay";
26 phy-handle = <&aquantia_phy1>;
27 phy-connection-type = "usxgmii";
28};
29
30&dpmac4 {
31 status = "okay";
32 phy-handle = <&aquantia_phy2>;
33 phy-connection-type = "usxgmii";
34};
35
36&dpmac17 {
37 status = "okay";
38 phy-handle = <&rgmii_phy1>;
39 phy-connection-type = "rgmii-id";
40};
41
42&dpmac18 {
43 status = "okay";
44 phy-handle = <&rgmii_phy2>;
45 phy-connection-type = "rgmii-id";
46};
47
48&emdio1 {
49 status = "okay";
50 rgmii_phy1: ethernet-phy@1 {
51 /* AR8035 PHY - "compatible" property not strictly needed */
52 compatible = "ethernet-phy-id004d.d072";
53 reg = <0x1>;
54 /* Poll mode - no "interrupts" property defined */
55 };
56 rgmii_phy2: ethernet-phy@2 {
57 /* AR8035 PHY - "compatible" property not strictly needed */
58 compatible = "ethernet-phy-id004d.d072";
59 reg = <0x2>;
60 /* Poll mode - no "interrupts" property defined */
61 };
62 aquantia_phy1: ethernet-phy@4 {
63 /* AQR107 PHY - "compatible" property not strictly needed */
64 compatible = "ethernet-phy-ieee802.3-c45";
65 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
66 reg = <0x4>;
67 };
68 aquantia_phy2: ethernet-phy@5 {
69 /* AQR107 PHY - "compatible" property not strictly needed */
70 compatible = "ethernet-phy-ieee802.3-c45";
71 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
72 reg = <0x5>;
73 };
74};
75
Priyanka Jainfd45ca02018-11-28 13:04:27 +0000[diff] [blame]76&esdhc0 {
77 status = "okay";
78};
79
80&esdhc1 {
81 status = "okay";
Yinbo Zhud8a7c222019-07-16 15:09:09 +0800[diff] [blame]82 mmc-hs200-1_8v;
Yangbo Lu8b956792020-09-01 16:58:08 +0800[diff] [blame]83 mmc-hs400-1_8v;
84 bus-width = <8>;
Priyanka Jainfd45ca02018-11-28 13:04:27 +0000[diff] [blame]85};
86
Kuldeep Singh6b614242019-11-06 16:38:01 +0530[diff] [blame]87&fspi {
88 status = "okay";
89
90 mt35xu512aba0: flash@0 {
91 #address-cells = <1>;
92 #size-cells = <1>;
93 compatible = "jedec,spi-nor";
94 spi-max-frequency = <50000000>;
95 reg = <0>;
Kuldeep Singh9a3844b2020-03-14 18:23:56 +0530[diff] [blame]96 spi-rx-bus-width = <8>;
97 spi-tx-bus-width = <1>;
Kuldeep Singh6b614242019-11-06 16:38:01 +0530[diff] [blame]98 };
99
100 mt35xu512aba1: flash@1 {
101 #address-cells = <1>;
102 #size-cells = <1>;
103 compatible = "jedec,spi-nor";
104 spi-max-frequency = <50000000>;
105 reg = <1>;
Kuldeep Singh9a3844b2020-03-14 18:23:56 +0530[diff] [blame]106 spi-rx-bus-width = <8>;
107 spi-tx-bus-width = <1>;
Kuldeep Singh6b614242019-11-06 16:38:01 +0530[diff] [blame]108 };
109};
110
Chuanhua Han1a64fb02019-07-10 21:00:26 +0800[diff] [blame]111&i2c0 {
112 status = "okay";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]113 bootph-all;
Chuanhua Han1a64fb02019-07-10 21:00:26 +0800[diff] [blame]114};
115
Chuanhua Han9312dcb2019-07-10 21:00:25 +0800[diff] [blame]116&i2c4 {
117 status = "okay";
118
119 rtc@51 {
Vladimir Oltean20b7d0a2022-01-03 14:47:29 +0200[diff] [blame]120 compatible = "nxp,pcf2129";
Chuanhua Han9312dcb2019-07-10 21:00:25 +0800[diff] [blame]121 reg = <0x51>;
122 };
123};
124
Priyanka Jainfd45ca02018-11-28 13:04:27 +0000[diff] [blame]125&sata0 {
126 status = "okay";
127};
128
129&sata1 {
130 status = "okay";
131};
132
133&sata2 {
134 status = "okay";
135};
136
137&sata3 {
138 status = "okay";
139};