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git01.mediatek.com / filogic / uboot / 32a8db0ca0d4d2d927895fa9e096032081813def / . / arch / arm / mach-uniphier / board_early_init_f.c
blob: 824da25ac77ebd05256697ac5f34a93f869eb583 [file] [log] [blame]
Masahiro Yamada1f3d9c72015-02-05 14:42:54 +0900[diff] [blame]1/*
Masahiro Yamada4e5d28d2015-09-22 00:27:31 +0900[diff] [blame]2 * Copyright (C) 2012-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada1f3d9c72015-02-05 14:42:54 +0900[diff] [blame]3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
Masahiro Yamadaefdf3402016-01-09 01:51:13 +0900[diff] [blame]7#include "init.h"
8#include "micro-support-card.h"
9#include "soc-info.h"
Masahiro Yamada1f3d9c72015-02-05 14:42:54 +0900[diff] [blame]10
11int board_early_init_f(void)
12{
Masahiro Yamada4e5d28d2015-09-22 00:27:31 +0900[diff] [blame]13 led_puts("U0");
Masahiro Yamada1f3d9c72015-02-05 14:42:54 +0900[diff] [blame]14
Masahiro Yamada75f16f82015-09-22 00:27:39 +0900[diff] [blame]15 switch (uniphier_get_soc_type()) {
16#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3)
17 case SOC_UNIPHIER_PH1_SLD3:
18 ph1_sld3_pin_init();
19 led_puts("U1");
20 ph1_ld4_clk_init();
21 break;
22#endif
23#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4)
24 case SOC_UNIPHIER_PH1_LD4:
25 ph1_ld4_pin_init();
26 led_puts("U1");
27 ph1_ld4_clk_init();
28 break;
29#endif
30#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4)
31 case SOC_UNIPHIER_PH1_PRO4:
32 ph1_pro4_pin_init();
33 led_puts("U1");
34 ph1_pro4_clk_init();
35 break;
36#endif
37#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8)
38 case SOC_UNIPHIER_PH1_SLD8:
39 ph1_sld8_pin_init();
40 led_puts("U1");
41 ph1_ld4_clk_init();
42 break;
43#endif
Masahiro Yamadad5167d52015-09-22 00:27:40 +0900[diff] [blame]44#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO5)
45 case SOC_UNIPHIER_PH1_PRO5:
46 ph1_pro5_pin_init();
47 led_puts("U1");
48 ph1_pro5_clk_init();
49 break;
50#endif
Masahiro Yamada1fe65d32015-09-22 00:27:41 +0900[diff] [blame]51#if defined(CONFIG_ARCH_UNIPHIER_PROXSTREAM2)
52 case SOC_UNIPHIER_PROXSTREAM2:
53 proxstream2_pin_init();
54 led_puts("U1");
55 proxstream2_clk_init();
56 break;
57#endif
58#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD6B)
59 case SOC_UNIPHIER_PH1_LD6B:
60 ph1_ld6b_pin_init();
61 led_puts("U1");
62 proxstream2_clk_init();
63 break;
64#endif
Masahiro Yamada75f16f82015-09-22 00:27:39 +0900[diff] [blame]65 default:
66 break;
67 }
Masahiro Yamadac04368f2015-02-27 02:26:51 +0900[diff] [blame]68
Masahiro Yamada4e5d28d2015-09-22 00:27:31 +0900[diff] [blame]69 led_puts("U2");
Masahiro Yamadac04368f2015-02-27 02:26:51 +0900[diff] [blame]70
Masahiro Yamada1f3d9c72015-02-05 14:42:54 +0900[diff] [blame]71 return 0;
72}