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git01.mediatek.com / filogic / uboot / 32a8db0ca0d4d2d927895fa9e096032081813def / . / arch / arm / dts / tegra20-whistler.dts
blob: c4a28eb427deff1bb0c79ada0d1fa857f8acd3da [file] [log] [blame]
Stephen Warren2791a0c2012-05-15 06:45:28 +0000[diff] [blame]1/dts-v1/;
2
Tom Warrenf6236152013-02-21 12:31:27 +0000[diff] [blame]3#include "tegra20.dtsi"
Stephen Warren2791a0c2012-05-15 06:45:28 +0000[diff] [blame]4
5/ {
Allen Martin55d98a12012-08-31 08:30:00 +0000[diff] [blame]6 model = "NVIDIA Tegra20 Whistler evaluation board";
Stephen Warren2791a0c2012-05-15 06:45:28 +0000[diff] [blame]7 compatible = "nvidia,whistler", "nvidia,tegra20";
8
Simon Glass0c24f372014-09-04 16:27:35 -0600[diff] [blame]9 chosen {
10 stdout-path = &uarta;
11 };
12
Stephen Warren2791a0c2012-05-15 06:45:28 +0000[diff] [blame]13 aliases {
14 i2c0 = "/i2c@7000d000";
15 usb0 = "/usb@c5008000";
Tom Warrened955272013-02-21 12:31:29 +0000[diff] [blame]16 sdhci0 = "/sdhci@c8000600";
17 sdhci1 = "/sdhci@c8000400";
Stephen Warren2791a0c2012-05-15 06:45:28 +0000[diff] [blame]18 };
19
20 memory {
21 device_type = "memory";
22 reg = < 0x00000000 0x20000000 >;
23 };
24
Stephen Warren2791a0c2012-05-15 06:45:28 +0000[diff] [blame]25 serial@70006000 {
26 clock-frequency = < 216000000 >;
27 };
28
29 i2c@7000c000 {
30 status = "disabled";
31 };
32
33 i2c@7000c400 {
34 status = "disabled";
35 };
36
37 i2c@7000c500 {
38 status = "disabled";
39 };
40
41 i2c@7000d000 {
42 clock-frequency = <100000>;
43
44 pmic@3c {
45 compatible = "maxim,max8907b";
46 reg = <0x3c>;
47
48 clk_32k: clock {
49 compatible = "fixed-clock";
50 /*
51 * leave out for now due to CPP:
52 * #clock-cells = <0>;
53 */
54 clock-frequency = <32768>;
55 };
56 };
57 };
58
Stephen Warrencafb9b42012-10-12 09:45:50 +0000[diff] [blame]59 usb@c5000000 {
60 status = "disabled";
61 };
62
Stephen Warren2791a0c2012-05-15 06:45:28 +0000[diff] [blame]63 usb@c5004000 {
64 status = "disabled";
65 };
Tom Warrened955272013-02-21 12:31:29 +0000[diff] [blame]66
67 sdhci@c8000400 {
68 status = "okay";
Simon Glass3112fd52015-01-05 20:05:41 -0700[diff] [blame]69 wp-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_HIGH>;
Tom Warrened955272013-02-21 12:31:29 +0000[diff] [blame]70 bus-width = <8>;
71 };
72
73 sdhci@c8000600 {
74 status = "okay";
75 bus-width = <8>;
76 };
Stephen Warren2791a0c2012-05-15 06:45:28 +0000[diff] [blame]77};