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git01.mediatek.com / filogic / uboot / 329a648ba5eadfb3f8885c05165811744e5f42f6 / . / board / advantech / som-db5800-som-6867 / som-db5800-som-6867.c
blob: 8f4c587371d920af5c9d18d28fe745ce4535258c [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
George McCollisteraedc33d2016-06-21 12:07:33 -0500[diff] [blame]2/*
3 * Copyright (C) 2016 Stefan Roese <sr@denx.de>
4 * Copyright (C) 2016 George McCollister <george.mccollister@gmail.com>
George McCollisteraedc33d2016-06-21 12:07:33 -0500[diff] [blame]5 */
6
7#include <common.h>
Simon Glass6c34fc12019-09-25 08:00:11 -0600[diff] [blame]8#include <asm/fsp1/fsp_support.h>
Bin Meng07e245c2017-10-13 01:30:06 -0700[diff] [blame]9
10/* ALC262 Verb Table - 10EC0262 */
11static const u32 verb_table_data13[] = {
12 /* Pin Complex (NID 0x11) */
13 0x01171cf0,
14 0x01171d11,
15 0x01171e11,
16 0x01171f41,
17 /* Pin Complex (NID 0x12) */
18 0x01271cf0,
19 0x01271d11,
20 0x01271e11,
21 0x01271f41,
22 /* Pin Complex (NID 0x14) */
23 0x01471c10,
24 0x01471d40,
25 0x01471e01,
26 0x01471f01,
27 /* Pin Complex (NID 0x15) */
28 0x01571cf0,
29 0x01571d11,
30 0x01571e11,
31 0x01571f41,
32 /* Pin Complex (NID 0x16) */
33 0x01671cf0,
34 0x01671d11,
35 0x01671e11,
36 0x01671f41,
37 /* Pin Complex (NID 0x18) */
38 0x01871c20,
39 0x01871d98,
40 0x01871ea1,
41 0x01871f01,
42 /* Pin Complex (NID 0x19) */
43 0x01971c21,
44 0x01971d98,
45 0x01971ea1,
46 0x01971f02,
47 /* Pin Complex (NID 0x1A) */
48 0x01a71c2f,
49 0x01a71d30,
50 0x01a71e81,
51 0x01a71f01,
52 /* Pin Complex */
53 0x01b71c1f,
54 0x01b71d40,
55 0x01b71e21,
56 0x01b71f02,
57 /* Pin Complex */
58 0x01c71cf0,
59 0x01c71d11,
60 0x01c71e11,
61 0x01c71f41,
62 /* Pin Complex */
63 0x01d71c01,
64 0x01d71dc6,
65 0x01d71e14,
66 0x01d71f40,
67 /* Pin Complex */
68 0x01e71cf0,
69 0x01e71d11,
70 0x01e71e11,
71 0x01e71f41,
72 /* Pin Complex */
73 0x01f71cf0,
74 0x01f71d11,
75 0x01f71e11,
76 0x01f71f41,
77};
78
79/*
80 * This needs to be in ROM since if we put it in CAR, FSP init loses it when
81 * it drops CAR.
82 *
83 * VerbTable: (RealTek ALC262)
84 * Revision ID = 0xFF, support all steps
85 * Codec Verb Table For AZALIA
86 * Codec Address: CAd value (0/1/2)
87 * Codec Vendor: 0x10EC0262
88 */
89static const struct azalia_verb_table azalia_verb_table[] = {
90 {
91 {
92 0x10ec0262,
93 0x0000,
94 0xff,
95 0x01,
96 0x000b,
97 0x0002,
98 },
99 verb_table_data13
100 }
101};
102
103static const struct azalia_config azalia_config = {
104 .pme_enable = 1,
105 .docking_supported = 1,
106 .docking_attached = 0,
107 .hdmi_codec_enable = 1,
108 .azalia_v_ci_enable = 1,
109 .rsvdbits = 0,
110 .verb_table_num = 1,
111 .verb_table = azalia_verb_table,
112 .reset_wait_timer_ms = 300
113};
114
115void update_fsp_azalia_configs(const struct azalia_config **azalia)
116{
117 *azalia = &azalia_config;
118}
George McCollisteraedc33d2016-06-21 12:07:33 -0500[diff] [blame]119
120int board_early_init_f(void)
121{
122 /*
123 * The FSP enables the BayTrail internal legacy UART (again).
124 * Disable it again, so that the one on the EC can be used.
125 */
126 setup_internal_uart(0);
127
128 return 0;
129}