Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / 32822d011e20e14fa069b965cec69486f85e4963 / . / configs / T2081QDS_SPIFLASH_defconfig
blob: 5a273c54f8586d076b9b129413f36bf865c23e2a [file] [log] [blame]
Masahiro Yamadad5f8fee2015-03-12 13:24:39 +0900[diff] [blame]1CONFIG_PPC=y
Tom Rini07edfae2018-02-03 12:10:38 -0500[diff] [blame]2CONFIG_SYS_TEXT_BASE=0x00201000
Simon Glassf2a89462016-09-12 23:18:41 -0600[diff] [blame]3CONFIG_SPL_LIBCOMMON_SUPPORT=y
Simon Glassb16c92c2016-09-12 23:18:43 -0600[diff] [blame]4CONFIG_SPL_LIBGENERIC_SUPPORT=y
Tom Rini5cd7ece2019-11-18 20:02:10 -0500[diff] [blame]5CONFIG_ENV_SIZE=0x2000
6CONFIG_ENV_OFFSET=0x100000
Tom Rini47dece32020-04-28 16:15:47 -0400[diff] [blame]7CONFIG_ENV_SECT_SIZE=0x10000
Tom Rini0332a1a2020-07-06 13:54:25 -0400[diff] [blame]8CONFIG_SPL_TEXT_BASE=0xFFFD8000
Tom Rinif6e6e1a2020-01-22 13:38:00 -0500[diff] [blame]9CONFIG_SPL_SERIAL_SUPPORT=y
10CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
Tom Rinie0056d72018-06-04 11:57:37 -0400[diff] [blame]11CONFIG_SPL=y
Simon Glass219d6122016-09-12 23:18:57 -0600[diff] [blame]12CONFIG_SPL_SPI_FLASH_SUPPORT=y
Simon Glassb24fdca2016-09-12 23:18:58 -0600[diff] [blame]13CONFIG_SPL_SPI_SUPPORT=y
Masahiro Yamadad5f8fee2015-03-12 13:24:39 +0900[diff] [blame]14CONFIG_MPC85xx=y
York Sund1a6c0f2016-11-21 12:46:58 -0800[diff] [blame]15CONFIG_TARGET_T2081QDS=y
Simon Glasse3ee2fb2016-02-22 22:55:43 -0700[diff] [blame]16CONFIG_FIT=y
17CONFIG_FIT_VERBOSE=y
18CONFIG_OF_BOARD_SETUP=y
19CONFIG_OF_STDOUT_VIA_ALIAS=y
Tom Rinie5678e42019-06-01 14:20:25 -0400[diff] [blame]20CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH"
Heiko Schocher0b368b12016-06-07 08:31:14 +0200[diff] [blame]21CONFIG_BOOTDELAY=10
Mario Six75b23ed2018-03-28 14:38:15 +0200[diff] [blame]22CONFIG_BOARD_EARLY_INIT_R=y
Tom Rini623d67e2018-02-06 12:15:38 -0500[diff] [blame]23# CONFIG_SPL_FRAMEWORK is not set
Tom Rinie5678e42019-06-01 14:20:25 -0400[diff] [blame]24CONFIG_SPL_SPI_BOOT=y
25CONFIG_SPL_FSL_PBL=y
Tom Rini9834b902017-03-13 13:48:42 -0400[diff] [blame]26CONFIG_SPL_ENV_SUPPORT=y
27CONFIG_SPL_I2C_SUPPORT=y
Simon Glass7db65a82016-09-12 23:18:45 -0600[diff] [blame]28CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
Tom Rinif852e732016-04-21 21:37:19 -0400[diff] [blame]29CONFIG_HUSH_PARSER=y
Tuomas Tynkkynen28d56bd2017-10-08 21:48:01 +0300[diff] [blame]30CONFIG_CMD_IMLS=y
Tom Rini1d9ac832016-04-24 17:29:26 -0400[diff] [blame]31CONFIG_CMD_GREPENV=y
Tom Rini78873cd2017-08-14 19:58:53 -0400[diff] [blame]32CONFIG_CMD_I2C=y
Tom Rini1d9ac832016-04-24 17:29:26 -0400[diff] [blame]33CONFIG_CMD_MMC=y
Tom Rini0f2dcb92016-04-22 16:41:25 -0400[diff] [blame]34CONFIG_CMD_SF=y
Tom Rini0f2dcb92016-04-22 16:41:25 -0400[diff] [blame]35CONFIG_CMD_USB=y
36CONFIG_CMD_DHCP=y
Tom Rini1d9ac832016-04-24 17:29:26 -0400[diff] [blame]37CONFIG_CMD_MII=y
Tom Rini0f2dcb92016-04-22 16:41:25 -0400[diff] [blame]38CONFIG_CMD_PING=y
Siva Durga Prasad Paladugu8e45f1a2018-06-19 12:24:23 +0200[diff] [blame]39CONFIG_MP=y
Tom Rini1d9ac832016-04-24 17:29:26 -0400[diff] [blame]40CONFIG_CMD_EXT2=y
41CONFIG_CMD_FAT=y
Tom Rinic20bb732017-07-22 18:36:16 -0400[diff] [blame]42CONFIG_CMD_MTDPARTS=y
Tom Rini5ad8e112017-10-22 17:55:07 -0400[diff] [blame]43CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
44CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)"
Adam Ford710966e2020-07-03 06:48:56 -0500[diff] [blame]45CONFIG_ENV_OVERWRITE=y
Tom Rini5b0b0402017-08-28 07:16:32 -0400[diff] [blame]46CONFIG_ENV_IS_IN_SPI_FLASH=y
Tom Rini5cd7ece2019-11-18 20:02:10 -0500[diff] [blame]47CONFIG_ENV_ADDR=0xFFFC9000
Tom Rinia5c4d402017-03-01 16:51:58 -0500[diff] [blame]48CONFIG_FSL_CAAM=y
Mario Six41d7d972018-03-28 14:38:19 +0200[diff] [blame]49CONFIG_FSL_ESDHC=y
Tom Rinie799f922019-12-04 17:18:38 -0500[diff] [blame]50CONFIG_MTD=y
Adam Ford76da1b22018-10-14 15:10:50 -0500[diff] [blame]51CONFIG_MTD_NOR_FLASH=y
52CONFIG_FLASH_CFI_DRIVER=y
53CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
54CONFIG_FLASH_CFI_MTD=y
55CONFIG_SYS_FLASH_CFI=y
Joe Hershberger17491a82015-06-22 16:15:29 -0500[diff] [blame]56CONFIG_SPI_FLASH=y
Patrick Delaunay0df81042019-02-27 15:20:36 +0100[diff] [blame]57CONFIG_SF_DEFAULT_MODE=0
58CONFIG_SF_DEFAULT_SPEED=10000000
Bin Meng27f5b192015-11-25 05:34:54 -0800[diff] [blame]59CONFIG_SPI_FLASH_EON=y
60CONFIG_SPI_FLASH_STMICRO=y
61CONFIG_SPI_FLASH_SST=y
Alexandru Gagniucd83e98c2017-08-01 17:19:59 -0700[diff] [blame]62CONFIG_PHYLIB=y
Jeremy Gebbenabe3edf2018-09-18 15:49:35 -0600[diff] [blame]63CONFIG_PHY_AQUANTIA=y
Tom Rini5d154192020-04-24 15:35:53 -0400[diff] [blame]64CONFIG_PHY_REALTEK=y
65CONFIG_PHY_TERANETICS=y
66CONFIG_PHY_VITESSE=y
Simon Glass9008a5b2015-08-19 09:33:43 -0600[diff] [blame]67CONFIG_E1000=y
Tom Rinifa911f82019-05-12 07:59:12 -0400[diff] [blame]68CONFIG_FMAN_ENET=y
Adam Ford53705472018-07-20 23:03:57 -0500[diff] [blame]69CONFIG_MII=y
Tom Rinifa911f82019-05-12 07:59:12 -0400[diff] [blame]70CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
Thomas Choua6cec012015-11-19 21:48:14 +0800[diff] [blame]71CONFIG_SYS_NS16550=y
Adam Ford4e96ff82018-04-15 13:51:26 -0400[diff] [blame]72CONFIG_SPI=y
Bin Meng72a049d2015-11-25 05:34:53 -0800[diff] [blame]73CONFIG_FSL_ESPI=y
Tom Rini6e9cb112016-09-08 16:31:26 -0400[diff] [blame]74CONFIG_USB=y
75CONFIG_USB_STORAGE=y
Marek Szyprowski795dc7d2020-06-03 14:43:40 +0200[diff] [blame]76CONFIG_ADDR_MAP=y
77CONFIG_SYS_NUM_ADDR_MAP=64
Simon Glassa66c5412016-02-22 22:55:42 -0700[diff] [blame]78CONFIG_OF_LIBFDT=y