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git01.mediatek.com / filogic / uboot / 327c0e95859e7df6b21ff7d0d28e198254d2957a / . / post / lib_powerpc / asm.S
blob: 91b599932ffdb109d51cb18c20d4ab816c316a0a [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Wolfgang Denkb38e0df2007-03-06 18:08:43 +0100[diff] [blame]2/*
3 * Copyright (C) 2002 Wolfgang Denk <wd@denx.de>
Wolfgang Denkb38e0df2007-03-06 18:08:43 +0100[diff] [blame]4 */
5
6#include <config.h>
7
Wolfgang Denkb38e0df2007-03-06 18:08:43 +0100[diff] [blame]8#include <post.h>
9#include <ppc_asm.tmpl>
10#include <ppc_defs.h>
11#include <asm/cache.h>
12
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]13#if CONFIG_POST & CONFIG_SYS_POST_CPU
Wolfgang Denkb38e0df2007-03-06 18:08:43 +0100[diff] [blame]14
15/* void cpu_post_exec_02 (ulong *code, ulong op1, ulong op2); */
16 .global cpu_post_exec_02
17cpu_post_exec_02:
Igor Lisitsin95bcd382007-03-28 19:06:19 +0400[diff] [blame]18 isync
Wolfgang Denkb38e0df2007-03-06 18:08:43 +0100[diff] [blame]19 mflr r0
20 stwu r0, -4(r1)
21
22 subi r1, r1, 104
23 stmw r6, 0(r1)
24
25 mtlr r3
26 mr r3, r4
27 mr r4, r5
28 blrl
29
30 lmw r6, 0(r1)
31 addi r1, r1, 104
32
33 lwz r0, 0(r1)
34 addi r1, r1, 4
35 mtlr r0
36 blr
37
38/* void cpu_post_exec_04 (ulong *code, ulong op1, ulong op2, ulong op3, ulong op4); */
39 .global cpu_post_exec_04
40cpu_post_exec_04:
Igor Lisitsin95bcd382007-03-28 19:06:19 +0400[diff] [blame]41 isync
Wolfgang Denkb38e0df2007-03-06 18:08:43 +0100[diff] [blame]42 mflr r0
43 stwu r0, -4(r1)
44
45 subi r1, r1, 96
46 stmw r8, 0(r1)
47
48 mtlr r3
49 mr r3, r4
50 mr r4, r5
51 mr r5, r6
52 mtxer r7
53 blrl
54
55 lmw r8, 0(r1)
56 addi r1, r1, 96
57
58 lwz r0, 0(r1)
59 addi r1, r1, 4
60 mtlr r0
61 blr
62
63/* void cpu_post_exec_12 (ulong *code, ulong *res, ulong op1, ulong op2); */
64 .global cpu_post_exec_12
65cpu_post_exec_12:
Igor Lisitsin95bcd382007-03-28 19:06:19 +0400[diff] [blame]66 isync
Wolfgang Denkb38e0df2007-03-06 18:08:43 +0100[diff] [blame]67 mflr r0
68 stwu r0, -4(r1)
69 stwu r4, -4(r1)
70
71 mtlr r3
72 mr r3, r5
73 mr r4, r6
74 blrl
75
76 lwz r4, 0(r1)
77 stw r3, 0(r4)
78
79 lwz r0, 4(r1)
80 addi r1, r1, 8
81 mtlr r0
82 blr
83
84/* void cpu_post_exec_11 (ulong *code, ulong *res, ulong op1); */
85 .global cpu_post_exec_11
86cpu_post_exec_11:
Igor Lisitsin95bcd382007-03-28 19:06:19 +0400[diff] [blame]87 isync
Wolfgang Denkb38e0df2007-03-06 18:08:43 +0100[diff] [blame]88 mflr r0
89 stwu r0, -4(r1)
90 stwu r4, -4(r1)
91
92 mtlr r3
93 mr r3, r5
94 blrl
95
96 lwz r4, 0(r1)
97 stw r3, 0(r4)
98
99 lwz r0, 4(r1)
100 addi r1, r1, 8
101 mtlr r0
102 blr
103
104/* void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op1); */
105 .global cpu_post_exec_21
106cpu_post_exec_21:
Igor Lisitsin95bcd382007-03-28 19:06:19 +0400[diff] [blame]107 isync
Wolfgang Denkb38e0df2007-03-06 18:08:43 +0100[diff] [blame]108 mflr r0
109 stwu r0, -4(r1)
110 stwu r4, -4(r1)
111 stwu r5, -4(r1)
112
113 li r0, 0
114 mtxer r0
115 lwz r0, 0(r4)
116 mtcr r0
117
118 mtlr r3
119 mr r3, r6
120 blrl
121
122 mfcr r0
123 lwz r4, 4(r1)
124 stw r0, 0(r4)
125 lwz r4, 0(r1)
126 stw r3, 0(r4)
127
128 lwz r0, 8(r1)
129 addi r1, r1, 12
130 mtlr r0
131 blr
132
133/* void cpu_post_exec_22 (ulong *code, ulong *cr, ulong *res, ulong op1,
134 ulong op2); */
135 .global cpu_post_exec_22
136cpu_post_exec_22:
Igor Lisitsin95bcd382007-03-28 19:06:19 +0400[diff] [blame]137 isync
Wolfgang Denkb38e0df2007-03-06 18:08:43 +0100[diff] [blame]138 mflr r0
139 stwu r0, -4(r1)
140 stwu r4, -4(r1)
141 stwu r5, -4(r1)
142
143 li r0, 0
144 mtxer r0
145 lwz r0, 0(r4)
146 mtcr r0
147
148 mtlr r3
149 mr r3, r6
150 mr r4, r7
151 blrl
152
153 mfcr r0
154 lwz r4, 4(r1)
155 stw r0, 0(r4)
156 lwz r4, 0(r1)
157 stw r3, 0(r4)
158
159 lwz r0, 8(r1)
160 addi r1, r1, 12
161 mtlr r0
162 blr
163
164/* void cpu_post_exec_12w (ulong *code, ulong *op1, ulong op2, ulong op3); */
165 .global cpu_post_exec_12w
166cpu_post_exec_12w:
Igor Lisitsin95bcd382007-03-28 19:06:19 +0400[diff] [blame]167 isync
Wolfgang Denkb38e0df2007-03-06 18:08:43 +0100[diff] [blame]168 mflr r0
169 stwu r0, -4(r1)
170 stwu r4, -4(r1)
171
172 mtlr r3
173 lwz r3, 0(r4)
174 mr r4, r5
175 mr r5, r6
176 blrl
177
178 lwz r4, 0(r1)
179 stw r3, 0(r4)
180
181 lwz r0, 4(r1)
182 addi r1, r1, 8
183 mtlr r0
184 blr
185
186/* void cpu_post_exec_11w (ulong *code, ulong *op1, ulong op2); */
187 .global cpu_post_exec_11w
188cpu_post_exec_11w:
Igor Lisitsin95bcd382007-03-28 19:06:19 +0400[diff] [blame]189 isync
Wolfgang Denkb38e0df2007-03-06 18:08:43 +0100[diff] [blame]190 mflr r0
191 stwu r0, -4(r1)
192 stwu r4, -4(r1)
193
194 mtlr r3
195 lwz r3, 0(r4)
196 mr r4, r5
197 blrl
198
199 lwz r4, 0(r1)
200 stw r3, 0(r4)
201
202 lwz r0, 4(r1)
203 addi r1, r1, 8
204 mtlr r0
205 blr
206
207/* void cpu_post_exec_22w (ulong *code, ulong *op1, ulong op2, ulong *op3); */
208 .global cpu_post_exec_22w
209cpu_post_exec_22w:
Igor Lisitsin95bcd382007-03-28 19:06:19 +0400[diff] [blame]210 isync
Wolfgang Denkb38e0df2007-03-06 18:08:43 +0100[diff] [blame]211 mflr r0
212 stwu r0, -4(r1)
213 stwu r4, -4(r1)
214 stwu r6, -4(r1)
215
216 mtlr r3
217 lwz r3, 0(r4)
218 mr r4, r5
219 blrl
220
221 lwz r4, 4(r1)
222 stw r3, 0(r4)
223 lwz r4, 0(r1)
224 stw r5, 0(r4)
225
226 lwz r0, 8(r1)
227 addi r1, r1, 12
228 mtlr r0
229 blr
230
231/* void cpu_post_exec_21w (ulong *code, ulong *op1, ulong *op2); */
232 .global cpu_post_exec_21w
233cpu_post_exec_21w:
Igor Lisitsin95bcd382007-03-28 19:06:19 +0400[diff] [blame]234 isync
Wolfgang Denkb38e0df2007-03-06 18:08:43 +0100[diff] [blame]235 mflr r0
236 stwu r0, -4(r1)
237 stwu r4, -4(r1)
238 stwu r5, -4(r1)
239
240 mtlr r3
241 lwz r3, 0(r4)
242 blrl
243
244 lwz r5, 4(r1)
245 stw r3, 0(r5)
246 lwz r5, 0(r1)
247 stw r4, 0(r5)
248
249 lwz r0, 8(r1)
250 addi r1, r1, 12
251 mtlr r0
252 blr
253
254/* void cpu_post_exec_21x (ulong *code, ulong *op1, ulong *op2, ulong op3); */
255 .global cpu_post_exec_21x
256cpu_post_exec_21x:
Igor Lisitsin95bcd382007-03-28 19:06:19 +0400[diff] [blame]257 isync
Wolfgang Denkb38e0df2007-03-06 18:08:43 +0100[diff] [blame]258 mflr r0
259 stwu r0, -4(r1)
260 stwu r4, -4(r1)
261 stwu r5, -4(r1)
262
263 mtlr r3
264 mr r3, r6
265 blrl
266
267 lwz r5, 4(r1)
268 stw r3, 0(r5)
269 lwz r5, 0(r1)
270 stw r4, 0(r5)
271
272 lwz r0, 8(r1)
273 addi r1, r1, 12
274 mtlr r0
275 blr
276
277/* void cpu_post_exec_31 (ulong *code, ulong *ctr, ulong *lr, ulong *jump,
278 ulong cr); */
279 .global cpu_post_exec_31
280cpu_post_exec_31:
Igor Lisitsin95bcd382007-03-28 19:06:19 +0400[diff] [blame]281 isync
Wolfgang Denkb38e0df2007-03-06 18:08:43 +0100[diff] [blame]282 mflr r0
283 stwu r0, -4(r1)
284 stwu r4, -4(r1)
285 stwu r5, -4(r1)
286 stwu r6, -4(r1)
287
288 mtlr r3
289 lwz r3, 0(r4)
290 lwz r4, 0(r5)
291 mr r6, r7
Yuri Tikhonov67b41722008-02-21 11:06:07 +0100[diff] [blame]292
293 mfcr r7
Wolfgang Denkb38e0df2007-03-06 18:08:43 +0100[diff] [blame]294 blrl
Yuri Tikhonov67b41722008-02-21 11:06:07 +0100[diff] [blame]295 mtcr r7
Wolfgang Denkb38e0df2007-03-06 18:08:43 +0100[diff] [blame]296
297 lwz r7, 8(r1)
298 stw r3, 0(r7)
299 lwz r7, 4(r1)
300 stw r4, 0(r7)
301 lwz r7, 0(r1)
302 stw r5, 0(r7)
303
304 lwz r0, 12(r1)
305 addi r1, r1, 16
306 mtlr r0
307 blr
308
309/* int cpu_post_complex_1_asm (int a1, int a2, int a3, int a4, int n); */
310 .global cpu_post_complex_1_asm
311cpu_post_complex_1_asm:
312 li r9,0
313 cmpw r9,r7
314 bge cpu_post_complex_1_done
315 mtctr r7
316cpu_post_complex_1_loop:
317 mullw r0,r3,r4
318 subf r0,r5,r0
319 divw r0,r0,r6
320 add r9,r9,r0
321 bdnz cpu_post_complex_1_loop
322cpu_post_complex_1_done:
323 mr r3,r9
324 blr
325
326/* int cpu_post_complex_2_asm (int x, int n); */
327 .global cpu_post_complex_2_asm
328cpu_post_complex_2_asm:
329 mr. r0,r4
330 mtctr r0
331 mr r0,r3
332 li r3,1
333 li r4,1
334 blelr
335cpu_post_complex_2_loop:
336 mullw r3,r3,r0
337 add r3,r3,r4
338 bdnz cpu_post_complex_2_loop
339blr
340
341#endif