| Ovidiu Panait | a850c32 | 2022-05-31 21:14:34 +0300 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 2 | /* |
| 3 | * Copyright (C) 2022, Ovidiu Panait <ovpanait@gmail.com> |
| 4 | */ |
| 5 | |
| 6 | #ifndef __ASM_MICROBLAZE_PVR_H |
| 7 | #define __ASM_MICROBLAZE_PVR_H |
| 8 | |
| 9 | #include <asm/asm.h> |
| 10 | |
| 11 | #define PVR_FULL_COUNT 13 /* PVR0 - PVR12 */ |
| 12 | |
| 13 | #define __get_pvr(val, reg) \ |
| 14 | __asm__ __volatile__ ("mfs %0," #reg : "=r" (val) :: "memory") |
| 15 | #define get_pvr(pvrid, val) \ |
| 16 | __get_pvr(val, rpvr ## pvrid) |
| 17 | |
| 18 | #define PVR_MSR_BIT 0x00000400 |
| 19 | |
| 20 | /* PVR0 masks */ |
| 21 | #define PVR0_PVR_FULL_MASK 0x80000000 |
| 22 | #define PVR0_VERSION_MASK 0x0000FF00 |
| 23 | |
| 24 | /* PVR4 masks - ICache configs */ |
| 25 | #define PVR4_ICACHE_LINE_LEN_MASK 0x00E00000 /* ICLL */ |
| 26 | #define PVR4_ICACHE_BYTE_SIZE_MASK 0x001F0000 /* ICBS */ |
| 27 | |
| 28 | /* PVR5 masks - DCache configs */ |
| 29 | #define PVR5_DCACHE_LINE_LEN_MASK 0x00E00000 /* DCLL */ |
| 30 | #define PVR5_DCACHE_BYTE_SIZE_MASK 0x001F0000 /* DCBS */ |
| 31 | |
| 32 | /* PVR10 masks - FPGA family */ |
| 33 | #define PVR10_TARGET_FAMILY_MASK 0xFF000000 |
| 34 | |
| 35 | /* PVR11 masks - MMU */ |
| 36 | #define PVR11_USE_MMU 0xC0000000 |
| 37 | |
| 38 | /* PVR access macros */ |
| 39 | #define PVR_VERSION(pvr) \ |
| 40 | ((pvr[0] & PVR0_VERSION_MASK) >> 8) |
| 41 | |
| 42 | #define PVR_ICACHE_LINE_LEN(pvr) \ |
| 43 | ((1 << ((pvr[4] & PVR4_ICACHE_LINE_LEN_MASK) >> 21)) << 2) |
| 44 | #define PVR_ICACHE_BYTE_SIZE(pvr) \ |
| 45 | (1 << ((pvr[4] & PVR4_ICACHE_BYTE_SIZE_MASK) >> 16)) |
| 46 | |
| 47 | #define PVR_DCACHE_LINE_LEN(pvr) \ |
| 48 | ((1 << ((pvr[5] & PVR5_DCACHE_LINE_LEN_MASK) >> 21)) << 2) |
| 49 | #define PVR_DCACHE_BYTE_SIZE(pvr) \ |
| 50 | (1 << ((pvr[5] & PVR5_DCACHE_BYTE_SIZE_MASK) >> 16)) |
| 51 | |
| 52 | #define PVR_USE_MMU(pvr) \ |
| 53 | ((pvr[11] & PVR11_USE_MMU) >> 30) |
| 54 | |
| 55 | #define PVR_TARGET_FAMILY(pvr) \ |
| 56 | ((pvr[10] & PVR10_TARGET_FAMILY_MASK) >> 24) |
| 57 | |
| 58 | /** |
| 59 | * microblaze_cpu_has_pvr_full() - Check for full PVR support |
| 60 | * |
| 61 | * Check MSR register for PVR support and, if applicable, check the PVR0 |
| 62 | * register for full PVR support. |
| 63 | * |
| 64 | * Return: 1 if there is full PVR support, 0 otherwise. |
| 65 | */ |
| 66 | int microblaze_cpu_has_pvr_full(void); |
| 67 | |
| 68 | /** |
| 69 | * microblaze_get_all_pvrs() - Copy PVR0-PVR12 to destination array |
| 70 | * |
| 71 | * @pvr: destination array of size PVR_FULL_COUNT |
| 72 | */ |
| 73 | void microblaze_get_all_pvrs(u32 pvr[PVR_FULL_COUNT]); |
| 74 | |
| 75 | #endif /* __ASM_MICROBLAZE_PVR_H */ |