Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / 3263e748a19043c290316fe7d2aefa15c2866dcb / . / drivers / pinctrl / renesas / pfc-r8a7795.c
blob: ba17a5577524c36afce31b2c48e3944e84d28688 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]2/*
3 * R8A7795 ES2.0+ processor support - PFC hardware block.
4 *
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5 * Copyright (C) 2015-2019 Renesas Electronics Corporation
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6 */
7
8#include <common.h>
9#include <dm.h>
10#include <errno.h>
11#include <dm/pinctrl.h>
12#include <linux/kernel.h>
13
14#include "sh_pfc.h"
15
16#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \
17 SH_PFC_PIN_CFG_PULL_UP | \
18 SH_PFC_PIN_CFG_PULL_DOWN)
19
20#define CPU_ALL_PORT(fn, sfx) \
21 PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]22 PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]23 PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
24 PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
25 PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
26 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
27 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
28 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
29 PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
30 PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
31 PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
32 PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
33/*
34 * F_() : just information
35 * FM() : macro for FN_xxx / xxx_MARK
36 */
37
38/* GPSR0 */
39#define GPSR0_15 F_(D15, IP7_11_8)
40#define GPSR0_14 F_(D14, IP7_7_4)
41#define GPSR0_13 F_(D13, IP7_3_0)
42#define GPSR0_12 F_(D12, IP6_31_28)
43#define GPSR0_11 F_(D11, IP6_27_24)
44#define GPSR0_10 F_(D10, IP6_23_20)
45#define GPSR0_9 F_(D9, IP6_19_16)
46#define GPSR0_8 F_(D8, IP6_15_12)
47#define GPSR0_7 F_(D7, IP6_11_8)
48#define GPSR0_6 F_(D6, IP6_7_4)
49#define GPSR0_5 F_(D5, IP6_3_0)
50#define GPSR0_4 F_(D4, IP5_31_28)
51#define GPSR0_3 F_(D3, IP5_27_24)
52#define GPSR0_2 F_(D2, IP5_23_20)
53#define GPSR0_1 F_(D1, IP5_19_16)
54#define GPSR0_0 F_(D0, IP5_15_12)
55
56/* GPSR1 */
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]57#define GPSR1_28 FM(CLKOUT)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]58#define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8)
59#define GPSR1_26 F_(WE1_N, IP5_7_4)
60#define GPSR1_25 F_(WE0_N, IP5_3_0)
61#define GPSR1_24 F_(RD_WR_N, IP4_31_28)
62#define GPSR1_23 F_(RD_N, IP4_27_24)
63#define GPSR1_22 F_(BS_N, IP4_23_20)
64#define GPSR1_21 F_(CS1_N, IP4_19_16)
65#define GPSR1_20 F_(CS0_N, IP4_15_12)
66#define GPSR1_19 F_(A19, IP4_11_8)
67#define GPSR1_18 F_(A18, IP4_7_4)
68#define GPSR1_17 F_(A17, IP4_3_0)
69#define GPSR1_16 F_(A16, IP3_31_28)
70#define GPSR1_15 F_(A15, IP3_27_24)
71#define GPSR1_14 F_(A14, IP3_23_20)
72#define GPSR1_13 F_(A13, IP3_19_16)
73#define GPSR1_12 F_(A12, IP3_15_12)
74#define GPSR1_11 F_(A11, IP3_11_8)
75#define GPSR1_10 F_(A10, IP3_7_4)
76#define GPSR1_9 F_(A9, IP3_3_0)
77#define GPSR1_8 F_(A8, IP2_31_28)
78#define GPSR1_7 F_(A7, IP2_27_24)
79#define GPSR1_6 F_(A6, IP2_23_20)
80#define GPSR1_5 F_(A5, IP2_19_16)
81#define GPSR1_4 F_(A4, IP2_15_12)
82#define GPSR1_3 F_(A3, IP2_11_8)
83#define GPSR1_2 F_(A2, IP2_7_4)
84#define GPSR1_1 F_(A1, IP2_3_0)
85#define GPSR1_0 F_(A0, IP1_31_28)
86
87/* GPSR2 */
88#define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20)
89#define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16)
90#define GPSR2_12 F_(AVB_LINK, IP0_15_12)
91#define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8)
92#define GPSR2_10 F_(AVB_MAGIC, IP0_7_4)
93#define GPSR2_9 F_(AVB_MDC, IP0_3_0)
94#define GPSR2_8 F_(PWM2_A, IP1_27_24)
95#define GPSR2_7 F_(PWM1_A, IP1_23_20)
96#define GPSR2_6 F_(PWM0, IP1_19_16)
97#define GPSR2_5 F_(IRQ5, IP1_15_12)
98#define GPSR2_4 F_(IRQ4, IP1_11_8)
99#define GPSR2_3 F_(IRQ3, IP1_7_4)
100#define GPSR2_2 F_(IRQ2, IP1_3_0)
101#define GPSR2_1 F_(IRQ1, IP0_31_28)
102#define GPSR2_0 F_(IRQ0, IP0_27_24)
103
104/* GPSR3 */
105#define GPSR3_15 F_(SD1_WP, IP11_23_20)
106#define GPSR3_14 F_(SD1_CD, IP11_19_16)
107#define GPSR3_13 F_(SD0_WP, IP11_15_12)
108#define GPSR3_12 F_(SD0_CD, IP11_11_8)
109#define GPSR3_11 F_(SD1_DAT3, IP8_31_28)
110#define GPSR3_10 F_(SD1_DAT2, IP8_27_24)
111#define GPSR3_9 F_(SD1_DAT1, IP8_23_20)
112#define GPSR3_8 F_(SD1_DAT0, IP8_19_16)
113#define GPSR3_7 F_(SD1_CMD, IP8_15_12)
114#define GPSR3_6 F_(SD1_CLK, IP8_11_8)
115#define GPSR3_5 F_(SD0_DAT3, IP8_7_4)
116#define GPSR3_4 F_(SD0_DAT2, IP8_3_0)
117#define GPSR3_3 F_(SD0_DAT1, IP7_31_28)
118#define GPSR3_2 F_(SD0_DAT0, IP7_27_24)
119#define GPSR3_1 F_(SD0_CMD, IP7_23_20)
120#define GPSR3_0 F_(SD0_CLK, IP7_19_16)
121
122/* GPSR4 */
123#define GPSR4_17 F_(SD3_DS, IP11_7_4)
124#define GPSR4_16 F_(SD3_DAT7, IP11_3_0)
125#define GPSR4_15 F_(SD3_DAT6, IP10_31_28)
126#define GPSR4_14 F_(SD3_DAT5, IP10_27_24)
127#define GPSR4_13 F_(SD3_DAT4, IP10_23_20)
128#define GPSR4_12 F_(SD3_DAT3, IP10_19_16)
129#define GPSR4_11 F_(SD3_DAT2, IP10_15_12)
130#define GPSR4_10 F_(SD3_DAT1, IP10_11_8)
131#define GPSR4_9 F_(SD3_DAT0, IP10_7_4)
132#define GPSR4_8 F_(SD3_CMD, IP10_3_0)
133#define GPSR4_7 F_(SD3_CLK, IP9_31_28)
134#define GPSR4_6 F_(SD2_DS, IP9_27_24)
135#define GPSR4_5 F_(SD2_DAT3, IP9_23_20)
136#define GPSR4_4 F_(SD2_DAT2, IP9_19_16)
137#define GPSR4_3 F_(SD2_DAT1, IP9_15_12)
138#define GPSR4_2 F_(SD2_DAT0, IP9_11_8)
139#define GPSR4_1 F_(SD2_CMD, IP9_7_4)
140#define GPSR4_0 F_(SD2_CLK, IP9_3_0)
141
142/* GPSR5 */
143#define GPSR5_25 F_(MLB_DAT, IP14_19_16)
144#define GPSR5_24 F_(MLB_SIG, IP14_15_12)
145#define GPSR5_23 F_(MLB_CLK, IP14_11_8)
146#define GPSR5_22 FM(MSIOF0_RXD)
147#define GPSR5_21 F_(MSIOF0_SS2, IP14_7_4)
148#define GPSR5_20 FM(MSIOF0_TXD)
149#define GPSR5_19 F_(MSIOF0_SS1, IP14_3_0)
150#define GPSR5_18 F_(MSIOF0_SYNC, IP13_31_28)
151#define GPSR5_17 FM(MSIOF0_SCK)
152#define GPSR5_16 F_(HRTS0_N, IP13_27_24)
153#define GPSR5_15 F_(HCTS0_N, IP13_23_20)
154#define GPSR5_14 F_(HTX0, IP13_19_16)
155#define GPSR5_13 F_(HRX0, IP13_15_12)
156#define GPSR5_12 F_(HSCK0, IP13_11_8)
157#define GPSR5_11 F_(RX2_A, IP13_7_4)
158#define GPSR5_10 F_(TX2_A, IP13_3_0)
159#define GPSR5_9 F_(SCK2, IP12_31_28)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]160#define GPSR5_8 F_(RTS1_N, IP12_27_24)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]161#define GPSR5_7 F_(CTS1_N, IP12_23_20)
162#define GPSR5_6 F_(TX1_A, IP12_19_16)
163#define GPSR5_5 F_(RX1_A, IP12_15_12)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]164#define GPSR5_4 F_(RTS0_N, IP12_11_8)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]165#define GPSR5_3 F_(CTS0_N, IP12_7_4)
166#define GPSR5_2 F_(TX0, IP12_3_0)
167#define GPSR5_1 F_(RX0, IP11_31_28)
168#define GPSR5_0 F_(SCK0, IP11_27_24)
169
170/* GPSR6 */
171#define GPSR6_31 F_(USB2_CH3_OVC, IP18_7_4)
172#define GPSR6_30 F_(USB2_CH3_PWEN, IP18_3_0)
173#define GPSR6_29 F_(USB30_OVC, IP17_31_28)
174#define GPSR6_28 F_(USB30_PWEN, IP17_27_24)
175#define GPSR6_27 F_(USB1_OVC, IP17_23_20)
176#define GPSR6_26 F_(USB1_PWEN, IP17_19_16)
177#define GPSR6_25 F_(USB0_OVC, IP17_15_12)
178#define GPSR6_24 F_(USB0_PWEN, IP17_11_8)
179#define GPSR6_23 F_(AUDIO_CLKB_B, IP17_7_4)
180#define GPSR6_22 F_(AUDIO_CLKA_A, IP17_3_0)
181#define GPSR6_21 F_(SSI_SDATA9_A, IP16_31_28)
182#define GPSR6_20 F_(SSI_SDATA8, IP16_27_24)
183#define GPSR6_19 F_(SSI_SDATA7, IP16_23_20)
184#define GPSR6_18 F_(SSI_WS78, IP16_19_16)
185#define GPSR6_17 F_(SSI_SCK78, IP16_15_12)
186#define GPSR6_16 F_(SSI_SDATA6, IP16_11_8)
187#define GPSR6_15 F_(SSI_WS6, IP16_7_4)
188#define GPSR6_14 F_(SSI_SCK6, IP16_3_0)
189#define GPSR6_13 FM(SSI_SDATA5)
190#define GPSR6_12 FM(SSI_WS5)
191#define GPSR6_11 FM(SSI_SCK5)
192#define GPSR6_10 F_(SSI_SDATA4, IP15_31_28)
193#define GPSR6_9 F_(SSI_WS4, IP15_27_24)
194#define GPSR6_8 F_(SSI_SCK4, IP15_23_20)
195#define GPSR6_7 F_(SSI_SDATA3, IP15_19_16)
196#define GPSR6_6 F_(SSI_WS349, IP15_15_12)
197#define GPSR6_5 F_(SSI_SCK349, IP15_11_8)
198#define GPSR6_4 F_(SSI_SDATA2_A, IP15_7_4)
199#define GPSR6_3 F_(SSI_SDATA1_A, IP15_3_0)
200#define GPSR6_2 F_(SSI_SDATA0, IP14_31_28)
201#define GPSR6_1 F_(SSI_WS01239, IP14_27_24)
202#define GPSR6_0 F_(SSI_SCK01239, IP14_23_20)
203
204/* GPSR7 */
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]205#define GPSR7_3 FM(GP7_03)
206#define GPSR7_2 FM(GP7_02)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]207#define GPSR7_1 FM(AVS2)
208#define GPSR7_0 FM(AVS1)
209
210
211/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
212#define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
213#define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
214#define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
215#define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
216#define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) FM(FSCLKST2_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]217#define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]218#define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
219#define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
220#define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]221#define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) F_(0, 0) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
222#define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) F_(0, 0) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
223#define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) F_(0, 0) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) FM(FSCLKST2_N_B) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
224#define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)F_(0, 0) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
225#define IP1_23_20 FM(PWM1_A) F_(0, 0) F_(0, 0) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
226#define IP1_27_24 FM(PWM2_A) F_(0, 0) F_(0, 0) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]227#define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
228#define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
229#define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
230#define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
231
232/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
233#define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
234#define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
235#define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
236#define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
237#define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
238#define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]239#define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]240#define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
241#define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
242#define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
243#define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
244#define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
245#define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
246#define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
247#define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
248#define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
249#define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
250#define IP4_19_16 FM(CS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
251#define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
252#define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
253#define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
254#define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]255#define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]256#define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
257#define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
258#define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
259#define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
260#define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
261#define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
262#define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263#define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264#define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
265#define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
266#define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
267#define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]268#define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_C) FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]269#define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270#define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271#define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
272#define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273#define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
274
275/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
276#define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
277#define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
278#define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279#define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280#define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281#define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
282#define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) FM(NFCE_N_B) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283#define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) FM(NFWP_N_B) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284#define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) FM(NFDATA14_B) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
285#define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) FM(NFDATA15_B) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
286#define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) FM(NFRB_N_B) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
287#define IP9_3_0 FM(SD2_CLK) F_(0, 0) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
288#define IP9_7_4 FM(SD2_CMD) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
289#define IP9_11_8 FM(SD2_DAT0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
290#define IP9_15_12 FM(SD2_DAT1) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291#define IP9_19_16 FM(SD2_DAT2) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292#define IP9_23_20 FM(SD2_DAT3) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293#define IP9_27_24 FM(SD2_DS) F_(0, 0) FM(NFALE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294#define IP9_31_28 FM(SD3_CLK) F_(0, 0) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295#define IP10_3_0 FM(SD3_CMD) F_(0, 0) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296#define IP10_7_4 FM(SD3_DAT0) F_(0, 0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
297#define IP10_11_8 FM(SD3_DAT1) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
298#define IP10_15_12 FM(SD3_DAT2) F_(0, 0) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299#define IP10_19_16 FM(SD3_DAT3) F_(0, 0) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300#define IP10_23_20 FM(SD3_DAT4) FM(SD2_CD_A) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301#define IP10_27_24 FM(SD3_DAT5) FM(SD2_WP_A) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
302#define IP10_31_28 FM(SD3_DAT6) FM(SD3_CD) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
303#define IP11_3_0 FM(SD3_DAT7) FM(SD3_WP) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304#define IP11_7_4 FM(SD3_DS) F_(0, 0) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305#define IP11_11_8 FM(SD0_CD) F_(0, 0) FM(NFDATA14_A) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306
307/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
308#define IP11_15_12 FM(SD0_WP) F_(0, 0) FM(NFDATA15_A) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
309#define IP11_19_16 FM(SD1_CD) F_(0, 0) FM(NFRB_N_A) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310#define IP11_23_20 FM(SD1_WP) F_(0, 0) FM(NFCE_N_A) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
311#define IP11_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
312#define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
313#define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
314#define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]315#define IP12_11_8 FM(RTS0_N) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]316#define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
317#define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
318#define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]319#define IP12_27_24 FM(RTS1_N) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]320#define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
321#define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
322#define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
323#define IP13_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
324#define IP13_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
325#define IP13_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
326#define IP13_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
327#define IP13_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
328#define IP13_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) FM(TX5_B) F_(0, 0) F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0)
329#define IP14_3_0 FM(MSIOF0_SS1) FM(RX5_A) FM(NFWP_N_A) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
330#define IP14_7_4 FM(MSIOF0_SS2) FM(TX5_A) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
331#define IP14_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
332#define IP14_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
333#define IP14_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
334#define IP14_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
335#define IP14_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
336
337/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
338#define IP14_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
339#define IP15_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
340#define IP15_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
341#define IP15_11_8 FM(SSI_SCK349) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
342#define IP15_15_12 FM(SSI_WS349) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
343#define IP15_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
344#define IP15_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
345#define IP15_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
346#define IP15_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
347#define IP16_3_0 FM(SSI_SCK6) FM(USB2_PWEN) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
348#define IP16_7_4 FM(SSI_WS6) FM(USB2_OVC) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
349#define IP16_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
350#define IP16_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
351#define IP16_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
352#define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
353#define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
354#define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]355#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]356#define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
357#define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
358#define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
359#define IP17_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0)
360#define IP17_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0)
361#define IP17_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0)
362#define IP17_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_N) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
363#define IP18_3_0 FM(USB2_CH3_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0)
364#define IP18_7_4 FM(USB2_CH3_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0)
365
366#define PINMUX_GPSR \
367\
368 GPSR6_31 \
369 GPSR6_30 \
370 GPSR6_29 \
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]371 GPSR1_28 GPSR6_28 \
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]372 GPSR1_27 GPSR6_27 \
373 GPSR1_26 GPSR6_26 \
374 GPSR1_25 GPSR5_25 GPSR6_25 \
375 GPSR1_24 GPSR5_24 GPSR6_24 \
376 GPSR1_23 GPSR5_23 GPSR6_23 \
377 GPSR1_22 GPSR5_22 GPSR6_22 \
378 GPSR1_21 GPSR5_21 GPSR6_21 \
379 GPSR1_20 GPSR5_20 GPSR6_20 \
380 GPSR1_19 GPSR5_19 GPSR6_19 \
381 GPSR1_18 GPSR5_18 GPSR6_18 \
382 GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \
383 GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \
384GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \
385GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \
386GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \
387GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \
388GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \
389GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \
390GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
391GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
392GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
393GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
394GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
395GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
396GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \
397GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \
398GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \
399GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0
400
401#define PINMUX_IPSR \
402\
403FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
404FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
405FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
406FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
407FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
408FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
409FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
410FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
411\
412FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
413FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
414FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
415FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 \
416FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
417FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
418FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
419FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
420\
421FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
422FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
423FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
424FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
425FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
426FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
427FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
428FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
429\
430FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \
431FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \
432FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \
433FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \
434FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \
435FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \
436FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \
437FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \
438\
439FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 FM(IP18_3_0) IP18_3_0 \
440FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 FM(IP18_7_4) IP18_7_4 \
441FM(IP16_11_8) IP16_11_8 FM(IP17_11_8) IP17_11_8 \
442FM(IP16_15_12) IP16_15_12 FM(IP17_15_12) IP17_15_12 \
443FM(IP16_19_16) IP16_19_16 FM(IP17_19_16) IP17_19_16 \
444FM(IP16_23_20) IP16_23_20 FM(IP17_23_20) IP17_23_20 \
445FM(IP16_27_24) IP16_27_24 FM(IP17_27_24) IP17_27_24 \
446FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
447
448/* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
449#define MOD_SEL0_31_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3) FM(SEL_MSIOF3_4) F_(0, 0) F_(0, 0) F_(0, 0)
450#define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3)
451#define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0)
452#define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1)
453#define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1)
454#define MOD_SEL0_21 FM(SEL_I2C2_0) FM(SEL_I2C2_1)
455#define MOD_SEL0_20 FM(SEL_I2C1_0) FM(SEL_I2C1_1)
456#define MOD_SEL0_19 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1)
457#define MOD_SEL0_18_17 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3)
458#define MOD_SEL0_16 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1)
459#define MOD_SEL0_14_13 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) FM(SEL_HSCIF2_2) F_(0, 0)
460#define MOD_SEL0_12 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1)
461#define MOD_SEL0_11 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1)
462#define MOD_SEL0_10 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
463#define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
464#define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
465#define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]466#define MOD_SEL0_4_3 FM(SEL_ADGA_0) FM(SEL_ADGA_1) FM(SEL_ADGA_2) FM(SEL_ADGA_3)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]467
468/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
469#define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
470#define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0)
471#define MOD_SEL1_26 FM(SEL_TIMER_TMU1_0) FM(SEL_TIMER_TMU1_1)
472#define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3)
473#define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]474#define MOD_SEL1_20 FM(SEL_SSI1_0) FM(SEL_SSI1_1)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]475#define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1)
476#define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3)
477#define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1)
478#define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0)
479#define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
480#define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
481#define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
482#define MOD_SEL1_10 FM(SEL_SCIF_0) FM(SEL_SCIF_1)
483#define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1)
484#define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1)
485#define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
486#define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1)
487#define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
488#define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
489#define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
490#define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
491
492/* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */
493#define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1)
494#define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1)
495#define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1)
496#define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3)
497#define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
498#define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
499#define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
500#define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
501#define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1)
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]502#define MOD_SEL2_18 FM(SEL_ADGB_0) FM(SEL_ADGB_1)
503#define MOD_SEL2_17 FM(SEL_ADGC_0) FM(SEL_ADGC_1)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]504#define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
505
506#define PINMUX_MOD_SELS \
507\
508MOD_SEL0_31_30_29 MOD_SEL1_31_30 MOD_SEL2_31 \
509 MOD_SEL2_30 \
510 MOD_SEL1_29_28_27 MOD_SEL2_29 \
511MOD_SEL0_28_27 MOD_SEL2_28_27 \
512MOD_SEL0_26_25_24 MOD_SEL1_26 MOD_SEL2_26 \
513 MOD_SEL1_25_24 MOD_SEL2_25_24_23 \
514MOD_SEL0_23 MOD_SEL1_23_22_21 \
515MOD_SEL0_22 \
516MOD_SEL0_21 MOD_SEL2_21 \
517MOD_SEL0_20 MOD_SEL1_20 MOD_SEL2_20 \
518MOD_SEL0_19 MOD_SEL1_19 MOD_SEL2_19 \
519MOD_SEL0_18_17 MOD_SEL1_18_17 MOD_SEL2_18 \
520 MOD_SEL2_17 \
521MOD_SEL0_16 MOD_SEL1_16 \
522 MOD_SEL1_15_14 \
523MOD_SEL0_14_13 \
524 MOD_SEL1_13 \
525MOD_SEL0_12 MOD_SEL1_12 \
526MOD_SEL0_11 MOD_SEL1_11 \
527MOD_SEL0_10 MOD_SEL1_10 \
528MOD_SEL0_9_8 MOD_SEL1_9 \
529MOD_SEL0_7_6 \
530 MOD_SEL1_6 \
531MOD_SEL0_5 MOD_SEL1_5 \
532MOD_SEL0_4_3 MOD_SEL1_4 \
533 MOD_SEL1_3 \
534 MOD_SEL1_2 \
535 MOD_SEL1_1 \
536 MOD_SEL1_0 MOD_SEL2_0
537
538/*
539 * These pins are not able to be muxed but have other properties
540 * that can be set, such as drive-strength or pull-up/pull-down enable.
541 */
542#define PINMUX_STATIC \
543 FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
544 FM(QSPI0_IO2) FM(QSPI0_IO3) \
545 FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
546 FM(QSPI1_IO2) FM(QSPI1_IO3) \
547 FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
548 FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
549 FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
550 FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]551 FM(PRESETOUT) \
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]552 FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) FM(DU_DOTCLKIN3) \
553 FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
554
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]555#define PINMUX_PHYS \
556 FM(SCL0) FM(SDA0) FM(SCL3) FM(SDA3) FM(SCL5) FM(SDA5)
557
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]558enum {
559 PINMUX_RESERVED = 0,
560
561 PINMUX_DATA_BEGIN,
562 GP_ALL(DATA),
563 PINMUX_DATA_END,
564
565#define F_(x, y)
566#define FM(x) FN_##x,
567 PINMUX_FUNCTION_BEGIN,
568 GP_ALL(FN),
569 PINMUX_GPSR
570 PINMUX_IPSR
571 PINMUX_MOD_SELS
572 PINMUX_FUNCTION_END,
573#undef F_
574#undef FM
575
576#define F_(x, y)
577#define FM(x) x##_MARK,
578 PINMUX_MARK_BEGIN,
579 PINMUX_GPSR
580 PINMUX_IPSR
581 PINMUX_MOD_SELS
582 PINMUX_STATIC
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]583 PINMUX_PHYS
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]584 PINMUX_MARK_END,
585#undef F_
586#undef FM
587};
588
589static const u16 pinmux_data[] = {
590 PINMUX_DATA_GP_ALL(),
591
592 PINMUX_SINGLE(AVS1),
593 PINMUX_SINGLE(AVS2),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]594 PINMUX_SINGLE(CLKOUT),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]595 PINMUX_SINGLE(GP7_02),
596 PINMUX_SINGLE(GP7_03),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]597 PINMUX_SINGLE(MSIOF0_RXD),
598 PINMUX_SINGLE(MSIOF0_SCK),
599 PINMUX_SINGLE(MSIOF0_TXD),
600 PINMUX_SINGLE(SSI_SCK5),
601 PINMUX_SINGLE(SSI_SDATA5),
602 PINMUX_SINGLE(SSI_WS5),
603
604 /* IPSR0 */
605 PINMUX_IPSR_GPSR(IP0_3_0, AVB_MDC),
606 PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2),
607
608 PINMUX_IPSR_GPSR(IP0_7_4, AVB_MAGIC),
609 PINMUX_IPSR_MSEL(IP0_7_4, MSIOF2_SS1_C, SEL_MSIOF2_2),
610 PINMUX_IPSR_MSEL(IP0_7_4, SCK4_A, SEL_SCIF4_0),
611
612 PINMUX_IPSR_GPSR(IP0_11_8, AVB_PHY_INT),
613 PINMUX_IPSR_MSEL(IP0_11_8, MSIOF2_SYNC_C, SEL_MSIOF2_2),
614 PINMUX_IPSR_MSEL(IP0_11_8, RX4_A, SEL_SCIF4_0),
615
616 PINMUX_IPSR_GPSR(IP0_15_12, AVB_LINK),
617 PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2),
618 PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0),
619
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]620 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
621 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, MSIOF2_RXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
622 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, CTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
623 PINMUX_IPSR_MSEL(IP0_19_16, FSCLKST2_N_A, I2C_SEL_5_0),
624 PINMUX_IPSR_PHYS(IP0_19_16, SCL5, I2C_SEL_5_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]625
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]626 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
627 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
628 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
629 PINMUX_IPSR_PHYS(IP0_23_20, SDA5, I2C_SEL_5_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]630
631 PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
632 PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
633 PINMUX_IPSR_GPSR(IP0_27_24, DU_CDE),
634 PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1),
635 PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1),
636 PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_B, SEL_CANFD0_1),
637 PINMUX_IPSR_MSEL(IP0_27_24, MSIOF3_SS2_E, SEL_MSIOF3_4),
638
639 PINMUX_IPSR_GPSR(IP0_31_28, IRQ1),
640 PINMUX_IPSR_GPSR(IP0_31_28, QPOLA),
641 PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP),
642 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1),
643 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1),
644 PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1),
645 PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_SS1_E, SEL_MSIOF3_4),
646
647 /* IPSR1 */
648 PINMUX_IPSR_GPSR(IP1_3_0, IRQ2),
649 PINMUX_IPSR_GPSR(IP1_3_0, QCPV_QDE),
650 PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE),
651 PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1),
652 PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1),
653 PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_SYNC_E, SEL_MSIOF3_4),
654
655 PINMUX_IPSR_GPSR(IP1_7_4, IRQ3),
656 PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]657 PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1),
658 PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1),
659 PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1),
660 PINMUX_IPSR_MSEL(IP1_7_4, MSIOF3_SCK_E, SEL_MSIOF3_4),
661
662 PINMUX_IPSR_GPSR(IP1_11_8, IRQ4),
663 PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]664 PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC),
665 PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1),
666 PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1),
667 PINMUX_IPSR_MSEL(IP1_11_8, MSIOF3_RXD_E, SEL_MSIOF3_4),
668
669 PINMUX_IPSR_GPSR(IP1_15_12, IRQ5),
670 PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]671 PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC),
672 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1),
673 PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1),
674 PINMUX_IPSR_GPSR(IP1_15_12, FSCLKST2_N_B),
675 PINMUX_IPSR_MSEL(IP1_15_12, MSIOF3_TXD_E, SEL_MSIOF3_4),
676
677 PINMUX_IPSR_GPSR(IP1_19_16, PWM0),
678 PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]679 PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1),
680 PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1),
681
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]682 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, PWM1_A, I2C_SEL_3_0, SEL_PWM1_0),
683 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
684 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1),
685 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1),
686 PINMUX_IPSR_PHYS(IP0_23_20, SCL3, I2C_SEL_3_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]687
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]688 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0),
689 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
690 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, IETX_B, I2C_SEL_3_0, SEL_IEBUS_1),
691 PINMUX_IPSR_PHYS(IP1_27_24, SDA3, I2C_SEL_3_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]692
693 PINMUX_IPSR_GPSR(IP1_31_28, A0),
694 PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16),
695 PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SYNC_B, SEL_MSIOF3_1),
696 PINMUX_IPSR_GPSR(IP1_31_28, VI4_DATA8),
697 PINMUX_IPSR_GPSR(IP1_31_28, DU_DB0),
698 PINMUX_IPSR_MSEL(IP1_31_28, PWM3_A, SEL_PWM3_0),
699
700 /* IPSR2 */
701 PINMUX_IPSR_GPSR(IP2_3_0, A1),
702 PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT17),
703 PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_TXD_B, SEL_MSIOF3_1),
704 PINMUX_IPSR_GPSR(IP2_3_0, VI4_DATA9),
705 PINMUX_IPSR_GPSR(IP2_3_0, DU_DB1),
706 PINMUX_IPSR_MSEL(IP2_3_0, PWM4_A, SEL_PWM4_0),
707
708 PINMUX_IPSR_GPSR(IP2_7_4, A2),
709 PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT18),
710 PINMUX_IPSR_MSEL(IP2_7_4, MSIOF3_SCK_B, SEL_MSIOF3_1),
711 PINMUX_IPSR_GPSR(IP2_7_4, VI4_DATA10),
712 PINMUX_IPSR_GPSR(IP2_7_4, DU_DB2),
713 PINMUX_IPSR_MSEL(IP2_7_4, PWM5_A, SEL_PWM5_0),
714
715 PINMUX_IPSR_GPSR(IP2_11_8, A3),
716 PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT19),
717 PINMUX_IPSR_MSEL(IP2_11_8, MSIOF3_RXD_B, SEL_MSIOF3_1),
718 PINMUX_IPSR_GPSR(IP2_11_8, VI4_DATA11),
719 PINMUX_IPSR_GPSR(IP2_11_8, DU_DB3),
720 PINMUX_IPSR_MSEL(IP2_11_8, PWM6_A, SEL_PWM6_0),
721
722 PINMUX_IPSR_GPSR(IP2_15_12, A4),
723 PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT20),
724 PINMUX_IPSR_MSEL(IP2_15_12, MSIOF3_SS1_B, SEL_MSIOF3_1),
725 PINMUX_IPSR_GPSR(IP2_15_12, VI4_DATA12),
726 PINMUX_IPSR_GPSR(IP2_15_12, VI5_DATA12),
727 PINMUX_IPSR_GPSR(IP2_15_12, DU_DB4),
728
729 PINMUX_IPSR_GPSR(IP2_19_16, A5),
730 PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT21),
731 PINMUX_IPSR_MSEL(IP2_19_16, MSIOF3_SS2_B, SEL_MSIOF3_1),
732 PINMUX_IPSR_MSEL(IP2_19_16, SCK4_B, SEL_SCIF4_1),
733 PINMUX_IPSR_GPSR(IP2_19_16, VI4_DATA13),
734 PINMUX_IPSR_GPSR(IP2_19_16, VI5_DATA13),
735 PINMUX_IPSR_GPSR(IP2_19_16, DU_DB5),
736
737 PINMUX_IPSR_GPSR(IP2_23_20, A6),
738 PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT22),
739 PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_SS1_A, SEL_MSIOF2_0),
740 PINMUX_IPSR_MSEL(IP2_23_20, RX4_B, SEL_SCIF4_1),
741 PINMUX_IPSR_GPSR(IP2_23_20, VI4_DATA14),
742 PINMUX_IPSR_GPSR(IP2_23_20, VI5_DATA14),
743 PINMUX_IPSR_GPSR(IP2_23_20, DU_DB6),
744
745 PINMUX_IPSR_GPSR(IP2_27_24, A7),
746 PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT23),
747 PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SS2_A, SEL_MSIOF2_0),
748 PINMUX_IPSR_MSEL(IP2_27_24, TX4_B, SEL_SCIF4_1),
749 PINMUX_IPSR_GPSR(IP2_27_24, VI4_DATA15),
750 PINMUX_IPSR_GPSR(IP2_27_24, VI5_DATA15),
751 PINMUX_IPSR_GPSR(IP2_27_24, DU_DB7),
752
753 PINMUX_IPSR_GPSR(IP2_31_28, A8),
754 PINMUX_IPSR_MSEL(IP2_31_28, RX3_B, SEL_SCIF3_1),
755 PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0),
756 PINMUX_IPSR_MSEL(IP2_31_28, HRX4_B, SEL_HSCIF4_1),
757 PINMUX_IPSR_MSEL(IP2_31_28, SDA6_A, SEL_I2C6_0),
758 PINMUX_IPSR_MSEL(IP2_31_28, AVB_AVTP_MATCH_B, SEL_ETHERAVB_1),
759 PINMUX_IPSR_MSEL(IP2_31_28, PWM1_B, SEL_PWM1_1),
760
761 /* IPSR3 */
762 PINMUX_IPSR_GPSR(IP3_3_0, A9),
763 PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0),
764 PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1),
765 PINMUX_IPSR_GPSR(IP3_3_0, VI5_VSYNC_N),
766
767 PINMUX_IPSR_GPSR(IP3_7_4, A10),
768 PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]769 PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_B, SEL_SCIF4_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]770 PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N),
771
772 PINMUX_IPSR_GPSR(IP3_11_8, A11),
773 PINMUX_IPSR_MSEL(IP3_11_8, TX3_B, SEL_SCIF3_1),
774 PINMUX_IPSR_MSEL(IP3_11_8, MSIOF2_TXD_A, SEL_MSIOF2_0),
775 PINMUX_IPSR_MSEL(IP3_11_8, HTX4_B, SEL_HSCIF4_1),
776 PINMUX_IPSR_GPSR(IP3_11_8, HSCK4),
777 PINMUX_IPSR_GPSR(IP3_11_8, VI5_FIELD),
778 PINMUX_IPSR_MSEL(IP3_11_8, SCL6_A, SEL_I2C6_0),
779 PINMUX_IPSR_MSEL(IP3_11_8, AVB_AVTP_CAPTURE_B, SEL_ETHERAVB_1),
780 PINMUX_IPSR_MSEL(IP3_11_8, PWM2_B, SEL_PWM2_1),
781
782 PINMUX_IPSR_GPSR(IP3_15_12, A12),
783 PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT12),
784 PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SCK_C, SEL_MSIOF3_2),
785 PINMUX_IPSR_MSEL(IP3_15_12, HRX4_A, SEL_HSCIF4_0),
786 PINMUX_IPSR_GPSR(IP3_15_12, VI5_DATA8),
787 PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4),
788
789 PINMUX_IPSR_GPSR(IP3_19_16, A13),
790 PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT13),
791 PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SYNC_C, SEL_MSIOF3_2),
792 PINMUX_IPSR_MSEL(IP3_19_16, HTX4_A, SEL_HSCIF4_0),
793 PINMUX_IPSR_GPSR(IP3_19_16, VI5_DATA9),
794 PINMUX_IPSR_GPSR(IP3_19_16, DU_DG5),
795
796 PINMUX_IPSR_GPSR(IP3_23_20, A14),
797 PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT14),
798 PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_C, SEL_MSIOF3_2),
799 PINMUX_IPSR_GPSR(IP3_23_20, HCTS4_N),
800 PINMUX_IPSR_GPSR(IP3_23_20, VI5_DATA10),
801 PINMUX_IPSR_GPSR(IP3_23_20, DU_DG6),
802
803 PINMUX_IPSR_GPSR(IP3_27_24, A15),
804 PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT15),
805 PINMUX_IPSR_MSEL(IP3_27_24, MSIOF3_TXD_C, SEL_MSIOF3_2),
806 PINMUX_IPSR_GPSR(IP3_27_24, HRTS4_N),
807 PINMUX_IPSR_GPSR(IP3_27_24, VI5_DATA11),
808 PINMUX_IPSR_GPSR(IP3_27_24, DU_DG7),
809
810 PINMUX_IPSR_GPSR(IP3_31_28, A16),
811 PINMUX_IPSR_GPSR(IP3_31_28, LCDOUT8),
812 PINMUX_IPSR_GPSR(IP3_31_28, VI4_FIELD),
813 PINMUX_IPSR_GPSR(IP3_31_28, DU_DG0),
814
815 /* IPSR4 */
816 PINMUX_IPSR_GPSR(IP4_3_0, A17),
817 PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT9),
818 PINMUX_IPSR_GPSR(IP4_3_0, VI4_VSYNC_N),
819 PINMUX_IPSR_GPSR(IP4_3_0, DU_DG1),
820
821 PINMUX_IPSR_GPSR(IP4_7_4, A18),
822 PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT10),
823 PINMUX_IPSR_GPSR(IP4_7_4, VI4_HSYNC_N),
824 PINMUX_IPSR_GPSR(IP4_7_4, DU_DG2),
825
826 PINMUX_IPSR_GPSR(IP4_11_8, A19),
827 PINMUX_IPSR_GPSR(IP4_11_8, LCDOUT11),
828 PINMUX_IPSR_GPSR(IP4_11_8, VI4_CLKENB),
829 PINMUX_IPSR_GPSR(IP4_11_8, DU_DG3),
830
831 PINMUX_IPSR_GPSR(IP4_15_12, CS0_N),
832 PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB),
833
834 PINMUX_IPSR_GPSR(IP4_19_16, CS1_N),
835 PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK),
836 PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1),
837
838 PINMUX_IPSR_GPSR(IP4_23_20, BS_N),
839 PINMUX_IPSR_GPSR(IP4_23_20, QSTVA_QVS),
840 PINMUX_IPSR_MSEL(IP4_23_20, MSIOF3_SCK_D, SEL_MSIOF3_3),
841 PINMUX_IPSR_GPSR(IP4_23_20, SCK3),
842 PINMUX_IPSR_GPSR(IP4_23_20, HSCK3),
843 PINMUX_IPSR_GPSR(IP4_23_20, CAN1_TX),
844 PINMUX_IPSR_GPSR(IP4_23_20, CANFD1_TX),
845 PINMUX_IPSR_MSEL(IP4_23_20, IETX_A, SEL_IEBUS_0),
846
847 PINMUX_IPSR_GPSR(IP4_27_24, RD_N),
848 PINMUX_IPSR_MSEL(IP4_27_24, MSIOF3_SYNC_D, SEL_MSIOF3_3),
849 PINMUX_IPSR_MSEL(IP4_27_24, RX3_A, SEL_SCIF3_0),
850 PINMUX_IPSR_MSEL(IP4_27_24, HRX3_A, SEL_HSCIF3_0),
851 PINMUX_IPSR_MSEL(IP4_27_24, CAN0_TX_A, SEL_RCAN0_0),
852 PINMUX_IPSR_MSEL(IP4_27_24, CANFD0_TX_A, SEL_CANFD0_0),
853
854 PINMUX_IPSR_GPSR(IP4_31_28, RD_WR_N),
855 PINMUX_IPSR_MSEL(IP4_31_28, MSIOF3_RXD_D, SEL_MSIOF3_3),
856 PINMUX_IPSR_MSEL(IP4_31_28, TX3_A, SEL_SCIF3_0),
857 PINMUX_IPSR_MSEL(IP4_31_28, HTX3_A, SEL_HSCIF3_0),
858 PINMUX_IPSR_MSEL(IP4_31_28, CAN0_RX_A, SEL_RCAN0_0),
859 PINMUX_IPSR_MSEL(IP4_31_28, CANFD0_RX_A, SEL_CANFD0_0),
860
861 /* IPSR5 */
862 PINMUX_IPSR_GPSR(IP5_3_0, WE0_N),
863 PINMUX_IPSR_MSEL(IP5_3_0, MSIOF3_TXD_D, SEL_MSIOF3_3),
864 PINMUX_IPSR_GPSR(IP5_3_0, CTS3_N),
865 PINMUX_IPSR_GPSR(IP5_3_0, HCTS3_N),
866 PINMUX_IPSR_MSEL(IP5_3_0, SCL6_B, SEL_I2C6_1),
867 PINMUX_IPSR_GPSR(IP5_3_0, CAN_CLK),
868 PINMUX_IPSR_MSEL(IP5_3_0, IECLK_A, SEL_IEBUS_0),
869
870 PINMUX_IPSR_GPSR(IP5_7_4, WE1_N),
871 PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]872 PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]873 PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N),
874 PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1),
875 PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX),
876 PINMUX_IPSR_GPSR(IP5_7_4, CANFD1_RX),
877 PINMUX_IPSR_MSEL(IP5_7_4, IERX_A, SEL_IEBUS_0),
878
879 PINMUX_IPSR_MSEL(IP5_11_8, EX_WAIT0_A, SEL_LBSC_0),
880 PINMUX_IPSR_GPSR(IP5_11_8, QCLK),
881 PINMUX_IPSR_GPSR(IP5_11_8, VI4_CLK),
882 PINMUX_IPSR_GPSR(IP5_11_8, DU_DOTCLKOUT0),
883
884 PINMUX_IPSR_GPSR(IP5_15_12, D0),
885 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF2_SS1_B, SEL_MSIOF2_1),
886 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF3_SCK_A, SEL_MSIOF3_0),
887 PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA16),
888 PINMUX_IPSR_GPSR(IP5_15_12, VI5_DATA0),
889
890 PINMUX_IPSR_GPSR(IP5_19_16, D1),
891 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF2_SS2_B, SEL_MSIOF2_1),
892 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF3_SYNC_A, SEL_MSIOF3_0),
893 PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA17),
894 PINMUX_IPSR_GPSR(IP5_19_16, VI5_DATA1),
895
896 PINMUX_IPSR_GPSR(IP5_23_20, D2),
897 PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_RXD_A, SEL_MSIOF3_0),
898 PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA18),
899 PINMUX_IPSR_GPSR(IP5_23_20, VI5_DATA2),
900
901 PINMUX_IPSR_GPSR(IP5_27_24, D3),
902 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0),
903 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19),
904 PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3),
905
906 PINMUX_IPSR_GPSR(IP5_31_28, D4),
907 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF2_SCK_B, SEL_MSIOF2_1),
908 PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA20),
909 PINMUX_IPSR_GPSR(IP5_31_28, VI5_DATA4),
910
911 /* IPSR6 */
912 PINMUX_IPSR_GPSR(IP6_3_0, D5),
913 PINMUX_IPSR_MSEL(IP6_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1),
914 PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA21),
915 PINMUX_IPSR_GPSR(IP6_3_0, VI5_DATA5),
916
917 PINMUX_IPSR_GPSR(IP6_7_4, D6),
918 PINMUX_IPSR_MSEL(IP6_7_4, MSIOF2_RXD_B, SEL_MSIOF2_1),
919 PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA22),
920 PINMUX_IPSR_GPSR(IP6_7_4, VI5_DATA6),
921
922 PINMUX_IPSR_GPSR(IP6_11_8, D7),
923 PINMUX_IPSR_MSEL(IP6_11_8, MSIOF2_TXD_B, SEL_MSIOF2_1),
924 PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA23),
925 PINMUX_IPSR_GPSR(IP6_11_8, VI5_DATA7),
926
927 PINMUX_IPSR_GPSR(IP6_15_12, D8),
928 PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT0),
929 PINMUX_IPSR_MSEL(IP6_15_12, MSIOF2_SCK_D, SEL_MSIOF2_3),
930 PINMUX_IPSR_MSEL(IP6_15_12, SCK4_C, SEL_SCIF4_2),
931 PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA0_A, SEL_VIN4_0),
932 PINMUX_IPSR_GPSR(IP6_15_12, DU_DR0),
933
934 PINMUX_IPSR_GPSR(IP6_19_16, D9),
935 PINMUX_IPSR_GPSR(IP6_19_16, LCDOUT1),
936 PINMUX_IPSR_MSEL(IP6_19_16, MSIOF2_SYNC_D, SEL_MSIOF2_3),
937 PINMUX_IPSR_MSEL(IP6_19_16, VI4_DATA1_A, SEL_VIN4_0),
938 PINMUX_IPSR_GPSR(IP6_19_16, DU_DR1),
939
940 PINMUX_IPSR_GPSR(IP6_23_20, D10),
941 PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT2),
942 PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_RXD_D, SEL_MSIOF2_3),
943 PINMUX_IPSR_MSEL(IP6_23_20, HRX3_B, SEL_HSCIF3_1),
944 PINMUX_IPSR_MSEL(IP6_23_20, VI4_DATA2_A, SEL_VIN4_0),
945 PINMUX_IPSR_MSEL(IP6_23_20, CTS4_N_C, SEL_SCIF4_2),
946 PINMUX_IPSR_GPSR(IP6_23_20, DU_DR2),
947
948 PINMUX_IPSR_GPSR(IP6_27_24, D11),
949 PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT3),
950 PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3),
951 PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1),
952 PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]953 PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_C, SEL_SCIF4_2),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]954 PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3),
955
956 PINMUX_IPSR_GPSR(IP6_31_28, D12),
957 PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT4),
958 PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3),
959 PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2),
960 PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0),
961 PINMUX_IPSR_GPSR(IP6_31_28, DU_DR4),
962
963 /* IPSR7 */
964 PINMUX_IPSR_GPSR(IP7_3_0, D13),
965 PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT5),
966 PINMUX_IPSR_MSEL(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3),
967 PINMUX_IPSR_MSEL(IP7_3_0, TX4_C, SEL_SCIF4_2),
968 PINMUX_IPSR_MSEL(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0),
969 PINMUX_IPSR_GPSR(IP7_3_0, DU_DR5),
970
971 PINMUX_IPSR_GPSR(IP7_7_4, D14),
972 PINMUX_IPSR_GPSR(IP7_7_4, LCDOUT6),
973 PINMUX_IPSR_MSEL(IP7_7_4, MSIOF3_SS1_A, SEL_MSIOF3_0),
974 PINMUX_IPSR_MSEL(IP7_7_4, HRX3_C, SEL_HSCIF3_2),
975 PINMUX_IPSR_MSEL(IP7_7_4, VI4_DATA6_A, SEL_VIN4_0),
976 PINMUX_IPSR_GPSR(IP7_7_4, DU_DR6),
977 PINMUX_IPSR_MSEL(IP7_7_4, SCL6_C, SEL_I2C6_2),
978
979 PINMUX_IPSR_GPSR(IP7_11_8, D15),
980 PINMUX_IPSR_GPSR(IP7_11_8, LCDOUT7),
981 PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SS2_A, SEL_MSIOF3_0),
982 PINMUX_IPSR_MSEL(IP7_11_8, HTX3_C, SEL_HSCIF3_2),
983 PINMUX_IPSR_MSEL(IP7_11_8, VI4_DATA7_A, SEL_VIN4_0),
984 PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7),
985 PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2),
986
987 PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK),
988 PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4),
989 PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1),
990
991 PINMUX_IPSR_GPSR(IP7_23_20, SD0_CMD),
992 PINMUX_IPSR_MSEL(IP7_23_20, MSIOF1_SYNC_E, SEL_MSIOF1_4),
993 PINMUX_IPSR_MSEL(IP7_23_20, STP_IVCXO27_0_B, SEL_SSP1_0_1),
994
995 PINMUX_IPSR_GPSR(IP7_27_24, SD0_DAT0),
996 PINMUX_IPSR_MSEL(IP7_27_24, MSIOF1_RXD_E, SEL_MSIOF1_4),
997 PINMUX_IPSR_MSEL(IP7_27_24, TS_SCK0_B, SEL_TSIF0_1),
998 PINMUX_IPSR_MSEL(IP7_27_24, STP_ISCLK_0_B, SEL_SSP1_0_1),
999
1000 PINMUX_IPSR_GPSR(IP7_31_28, SD0_DAT1),
1001 PINMUX_IPSR_MSEL(IP7_31_28, MSIOF1_TXD_E, SEL_MSIOF1_4),
1002 PINMUX_IPSR_MSEL(IP7_31_28, TS_SPSYNC0_B, SEL_TSIF0_1),
1003 PINMUX_IPSR_MSEL(IP7_31_28, STP_ISSYNC_0_B, SEL_SSP1_0_1),
1004
1005 /* IPSR8 */
1006 PINMUX_IPSR_GPSR(IP8_3_0, SD0_DAT2),
1007 PINMUX_IPSR_MSEL(IP8_3_0, MSIOF1_SS1_E, SEL_MSIOF1_4),
1008 PINMUX_IPSR_MSEL(IP8_3_0, TS_SDAT0_B, SEL_TSIF0_1),
1009 PINMUX_IPSR_MSEL(IP8_3_0, STP_ISD_0_B, SEL_SSP1_0_1),
1010
1011 PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT3),
1012 PINMUX_IPSR_MSEL(IP8_7_4, MSIOF1_SS2_E, SEL_MSIOF1_4),
1013 PINMUX_IPSR_MSEL(IP8_7_4, TS_SDEN0_B, SEL_TSIF0_1),
1014 PINMUX_IPSR_MSEL(IP8_7_4, STP_ISEN_0_B, SEL_SSP1_0_1),
1015
1016 PINMUX_IPSR_GPSR(IP8_11_8, SD1_CLK),
1017 PINMUX_IPSR_MSEL(IP8_11_8, MSIOF1_SCK_G, SEL_MSIOF1_6),
1018 PINMUX_IPSR_MSEL(IP8_11_8, SIM0_CLK_A, SEL_SIMCARD_0),
1019
1020 PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD),
1021 PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6),
1022 PINMUX_IPSR_GPSR(IP8_15_12, NFCE_N_B),
1023 PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0),
1024 PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1),
1025
1026 PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0),
1027 PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4),
1028 PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6),
1029 PINMUX_IPSR_GPSR(IP8_19_16, NFWP_N_B),
1030 PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1),
1031 PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1),
1032
1033 PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1),
1034 PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5),
1035 PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6),
1036 PINMUX_IPSR_GPSR(IP8_23_20, NFDATA14_B),
1037 PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1),
1038 PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1),
1039
1040 PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2),
1041 PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6),
1042 PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6),
1043 PINMUX_IPSR_GPSR(IP8_27_24, NFDATA15_B),
1044 PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1),
1045 PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1),
1046
1047 PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3),
1048 PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7),
1049 PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6),
1050 PINMUX_IPSR_GPSR(IP8_31_28, NFRB_N_B),
1051 PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1),
1052 PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1),
1053
1054 /* IPSR9 */
1055 PINMUX_IPSR_GPSR(IP9_3_0, SD2_CLK),
1056 PINMUX_IPSR_GPSR(IP9_3_0, NFDATA8),
1057
1058 PINMUX_IPSR_GPSR(IP9_7_4, SD2_CMD),
1059 PINMUX_IPSR_GPSR(IP9_7_4, NFDATA9),
1060
1061 PINMUX_IPSR_GPSR(IP9_11_8, SD2_DAT0),
1062 PINMUX_IPSR_GPSR(IP9_11_8, NFDATA10),
1063
1064 PINMUX_IPSR_GPSR(IP9_15_12, SD2_DAT1),
1065 PINMUX_IPSR_GPSR(IP9_15_12, NFDATA11),
1066
1067 PINMUX_IPSR_GPSR(IP9_19_16, SD2_DAT2),
1068 PINMUX_IPSR_GPSR(IP9_19_16, NFDATA12),
1069
1070 PINMUX_IPSR_GPSR(IP9_23_20, SD2_DAT3),
1071 PINMUX_IPSR_GPSR(IP9_23_20, NFDATA13),
1072
1073 PINMUX_IPSR_GPSR(IP9_27_24, SD2_DS),
1074 PINMUX_IPSR_GPSR(IP9_27_24, NFALE),
1075 PINMUX_IPSR_GPSR(IP9_27_24, SATA_DEVSLP_B),
1076
1077 PINMUX_IPSR_GPSR(IP9_31_28, SD3_CLK),
1078 PINMUX_IPSR_GPSR(IP9_31_28, NFWE_N),
1079
1080 /* IPSR10 */
1081 PINMUX_IPSR_GPSR(IP10_3_0, SD3_CMD),
1082 PINMUX_IPSR_GPSR(IP10_3_0, NFRE_N),
1083
1084 PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT0),
1085 PINMUX_IPSR_GPSR(IP10_7_4, NFDATA0),
1086
1087 PINMUX_IPSR_GPSR(IP10_11_8, SD3_DAT1),
1088 PINMUX_IPSR_GPSR(IP10_11_8, NFDATA1),
1089
1090 PINMUX_IPSR_GPSR(IP10_15_12, SD3_DAT2),
1091 PINMUX_IPSR_GPSR(IP10_15_12, NFDATA2),
1092
1093 PINMUX_IPSR_GPSR(IP10_19_16, SD3_DAT3),
1094 PINMUX_IPSR_GPSR(IP10_19_16, NFDATA3),
1095
1096 PINMUX_IPSR_GPSR(IP10_23_20, SD3_DAT4),
1097 PINMUX_IPSR_MSEL(IP10_23_20, SD2_CD_A, SEL_SDHI2_0),
1098 PINMUX_IPSR_GPSR(IP10_23_20, NFDATA4),
1099
1100 PINMUX_IPSR_GPSR(IP10_27_24, SD3_DAT5),
1101 PINMUX_IPSR_MSEL(IP10_27_24, SD2_WP_A, SEL_SDHI2_0),
1102 PINMUX_IPSR_GPSR(IP10_27_24, NFDATA5),
1103
1104 PINMUX_IPSR_GPSR(IP10_31_28, SD3_DAT6),
1105 PINMUX_IPSR_GPSR(IP10_31_28, SD3_CD),
1106 PINMUX_IPSR_GPSR(IP10_31_28, NFDATA6),
1107
1108 /* IPSR11 */
1109 PINMUX_IPSR_GPSR(IP11_3_0, SD3_DAT7),
1110 PINMUX_IPSR_GPSR(IP11_3_0, SD3_WP),
1111 PINMUX_IPSR_GPSR(IP11_3_0, NFDATA7),
1112
1113 PINMUX_IPSR_GPSR(IP11_7_4, SD3_DS),
1114 PINMUX_IPSR_GPSR(IP11_7_4, NFCLE),
1115
1116 PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD),
1117 PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1),
1118 PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0),
1119
1120 PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP),
1121 PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1),
1122
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]1123 PINMUX_IPSR_MSEL(IP11_19_16, SD1_CD, I2C_SEL_0_0),
1124 PINMUX_IPSR_PHYS_MSEL(IP11_19_16, SIM0_CLK_B, I2C_SEL_0_0, SEL_SIMCARD_1),
1125 PINMUX_IPSR_PHYS(IP11_19_16, SCL0, I2C_SEL_0_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1126
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]1127 PINMUX_IPSR_MSEL(IP11_23_20, SD1_WP, I2C_SEL_0_0),
1128 PINMUX_IPSR_PHYS_MSEL(IP11_23_20, SIM0_D_B, I2C_SEL_0_0, SEL_SIMCARD_1),
1129 PINMUX_IPSR_PHYS(IP11_23_20, SDA0, I2C_SEL_0_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1130
1131 PINMUX_IPSR_GPSR(IP11_27_24, SCK0),
1132 PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1),
1133 PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1134 PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADGC_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1135 PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0),
1136 PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1),
1137 PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2),
1138 PINMUX_IPSR_MSEL(IP11_27_24, RIF0_CLK_B, SEL_DRIF0_1),
1139 PINMUX_IPSR_GPSR(IP11_27_24, ADICHS2),
1140 PINMUX_IPSR_MSEL(IP11_27_24, SCK5_B, SEL_SCIF5_1),
1141
1142 PINMUX_IPSR_GPSR(IP11_31_28, RX0),
1143 PINMUX_IPSR_MSEL(IP11_31_28, HRX1_B, SEL_HSCIF1_1),
1144 PINMUX_IPSR_MSEL(IP11_31_28, TS_SCK0_C, SEL_TSIF0_2),
1145 PINMUX_IPSR_MSEL(IP11_31_28, STP_ISCLK_0_C, SEL_SSP1_0_2),
1146 PINMUX_IPSR_MSEL(IP11_31_28, RIF0_D0_B, SEL_DRIF0_1),
1147
1148 /* IPSR12 */
1149 PINMUX_IPSR_GPSR(IP12_3_0, TX0),
1150 PINMUX_IPSR_MSEL(IP12_3_0, HTX1_B, SEL_HSCIF1_1),
1151 PINMUX_IPSR_MSEL(IP12_3_0, TS_SPSYNC0_C, SEL_TSIF0_2),
1152 PINMUX_IPSR_MSEL(IP12_3_0, STP_ISSYNC_0_C, SEL_SSP1_0_2),
1153 PINMUX_IPSR_MSEL(IP12_3_0, RIF0_D1_B, SEL_DRIF0_1),
1154
1155 PINMUX_IPSR_GPSR(IP12_7_4, CTS0_N),
1156 PINMUX_IPSR_MSEL(IP12_7_4, HCTS1_N_B, SEL_HSCIF1_1),
1157 PINMUX_IPSR_MSEL(IP12_7_4, MSIOF1_SYNC_B, SEL_MSIOF1_1),
1158 PINMUX_IPSR_MSEL(IP12_7_4, TS_SPSYNC1_C, SEL_TSIF1_2),
1159 PINMUX_IPSR_MSEL(IP12_7_4, STP_ISSYNC_1_C, SEL_SSP1_1_2),
1160 PINMUX_IPSR_MSEL(IP12_7_4, RIF1_SYNC_B, SEL_DRIF1_1),
1161 PINMUX_IPSR_GPSR(IP12_7_4, AUDIO_CLKOUT_C),
1162 PINMUX_IPSR_GPSR(IP12_7_4, ADICS_SAMP),
1163
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1164 PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1165 PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1),
1166 PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1167 PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADGA_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1168 PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0),
1169 PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2),
1170 PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1),
1171 PINMUX_IPSR_GPSR(IP12_11_8, ADICHS1),
1172
1173 PINMUX_IPSR_MSEL(IP12_15_12, RX1_A, SEL_SCIF1_0),
1174 PINMUX_IPSR_MSEL(IP12_15_12, HRX1_A, SEL_HSCIF1_0),
1175 PINMUX_IPSR_MSEL(IP12_15_12, TS_SDAT0_C, SEL_TSIF0_2),
1176 PINMUX_IPSR_MSEL(IP12_15_12, STP_ISD_0_C, SEL_SSP1_0_2),
1177 PINMUX_IPSR_MSEL(IP12_15_12, RIF1_CLK_C, SEL_DRIF1_2),
1178
1179 PINMUX_IPSR_MSEL(IP12_19_16, TX1_A, SEL_SCIF1_0),
1180 PINMUX_IPSR_MSEL(IP12_19_16, HTX1_A, SEL_HSCIF1_0),
1181 PINMUX_IPSR_MSEL(IP12_19_16, TS_SDEN0_C, SEL_TSIF0_2),
1182 PINMUX_IPSR_MSEL(IP12_19_16, STP_ISEN_0_C, SEL_SSP1_0_2),
1183 PINMUX_IPSR_MSEL(IP12_19_16, RIF1_D0_C, SEL_DRIF1_2),
1184
1185 PINMUX_IPSR_GPSR(IP12_23_20, CTS1_N),
1186 PINMUX_IPSR_MSEL(IP12_23_20, HCTS1_N_A, SEL_HSCIF1_0),
1187 PINMUX_IPSR_MSEL(IP12_23_20, MSIOF1_RXD_B, SEL_MSIOF1_1),
1188 PINMUX_IPSR_MSEL(IP12_23_20, TS_SDEN1_C, SEL_TSIF1_2),
1189 PINMUX_IPSR_MSEL(IP12_23_20, STP_ISEN_1_C, SEL_SSP1_1_2),
1190 PINMUX_IPSR_MSEL(IP12_23_20, RIF1_D0_B, SEL_DRIF1_1),
1191 PINMUX_IPSR_GPSR(IP12_23_20, ADIDATA),
1192
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1193 PINMUX_IPSR_GPSR(IP12_27_24, RTS1_N),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1194 PINMUX_IPSR_MSEL(IP12_27_24, HRTS1_N_A, SEL_HSCIF1_0),
1195 PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1),
1196 PINMUX_IPSR_MSEL(IP12_27_24, TS_SDAT1_C, SEL_TSIF1_2),
1197 PINMUX_IPSR_MSEL(IP12_27_24, STP_ISD_1_C, SEL_SSP1_1_2),
1198 PINMUX_IPSR_MSEL(IP12_27_24, RIF1_D1_B, SEL_DRIF1_1),
1199 PINMUX_IPSR_GPSR(IP12_27_24, ADICHS0),
1200
1201 PINMUX_IPSR_GPSR(IP12_31_28, SCK2),
1202 PINMUX_IPSR_MSEL(IP12_31_28, SCIF_CLK_B, SEL_SCIF_1),
1203 PINMUX_IPSR_MSEL(IP12_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1),
1204 PINMUX_IPSR_MSEL(IP12_31_28, TS_SCK1_C, SEL_TSIF1_2),
1205 PINMUX_IPSR_MSEL(IP12_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2),
1206 PINMUX_IPSR_MSEL(IP12_31_28, RIF1_CLK_B, SEL_DRIF1_1),
1207 PINMUX_IPSR_GPSR(IP12_31_28, ADICLK),
1208
1209 /* IPSR13 */
1210 PINMUX_IPSR_MSEL(IP13_3_0, TX2_A, SEL_SCIF2_0),
1211 PINMUX_IPSR_MSEL(IP13_3_0, SD2_CD_B, SEL_SDHI2_1),
1212 PINMUX_IPSR_MSEL(IP13_3_0, SCL1_A, SEL_I2C1_0),
1213 PINMUX_IPSR_MSEL(IP13_3_0, FMCLK_A, SEL_FM_0),
1214 PINMUX_IPSR_MSEL(IP13_3_0, RIF1_D1_C, SEL_DRIF1_2),
1215 PINMUX_IPSR_GPSR(IP13_3_0, FSO_CFE_0_N),
1216
1217 PINMUX_IPSR_MSEL(IP13_7_4, RX2_A, SEL_SCIF2_0),
1218 PINMUX_IPSR_MSEL(IP13_7_4, SD2_WP_B, SEL_SDHI2_1),
1219 PINMUX_IPSR_MSEL(IP13_7_4, SDA1_A, SEL_I2C1_0),
1220 PINMUX_IPSR_MSEL(IP13_7_4, FMIN_A, SEL_FM_0),
1221 PINMUX_IPSR_MSEL(IP13_7_4, RIF1_SYNC_C, SEL_DRIF1_2),
1222 PINMUX_IPSR_GPSR(IP13_7_4, FSO_CFE_1_N),
1223
1224 PINMUX_IPSR_GPSR(IP13_11_8, HSCK0),
1225 PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1226 PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADGB_0),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1227 PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI1_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1228 PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3),
1229 PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
1230 PINMUX_IPSR_MSEL(IP13_11_8, RIF0_CLK_C, SEL_DRIF0_2),
1231 PINMUX_IPSR_MSEL(IP13_11_8, RX5_B, SEL_SCIF5_1),
1232
1233 PINMUX_IPSR_GPSR(IP13_15_12, HRX0),
1234 PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1235 PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA2_B, SEL_SSI2_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1236 PINMUX_IPSR_MSEL(IP13_15_12, TS_SDEN0_D, SEL_TSIF0_3),
1237 PINMUX_IPSR_MSEL(IP13_15_12, STP_ISEN_0_D, SEL_SSP1_0_3),
1238 PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_C, SEL_DRIF0_2),
1239
1240 PINMUX_IPSR_GPSR(IP13_19_16, HTX0),
1241 PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1242 PINMUX_IPSR_MSEL(IP13_19_16, SSI_SDATA9_B, SEL_SSI9_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1243 PINMUX_IPSR_MSEL(IP13_19_16, TS_SDAT0_D, SEL_TSIF0_3),
1244 PINMUX_IPSR_MSEL(IP13_19_16, STP_ISD_0_D, SEL_SSP1_0_3),
1245 PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_C, SEL_DRIF0_2),
1246
1247 PINMUX_IPSR_GPSR(IP13_23_20, HCTS0_N),
1248 PINMUX_IPSR_MSEL(IP13_23_20, RX2_B, SEL_SCIF2_1),
1249 PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1250 PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK9_A, SEL_SSI9_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1251 PINMUX_IPSR_MSEL(IP13_23_20, TS_SPSYNC0_D, SEL_TSIF0_3),
1252 PINMUX_IPSR_MSEL(IP13_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3),
1253 PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_C, SEL_DRIF0_2),
1254 PINMUX_IPSR_GPSR(IP13_23_20, AUDIO_CLKOUT1_A),
1255
1256 PINMUX_IPSR_GPSR(IP13_27_24, HRTS0_N),
1257 PINMUX_IPSR_MSEL(IP13_27_24, TX2_B, SEL_SCIF2_1),
1258 PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1259 PINMUX_IPSR_MSEL(IP13_27_24, SSI_WS9_A, SEL_SSI9_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1260 PINMUX_IPSR_MSEL(IP13_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3),
1261 PINMUX_IPSR_MSEL(IP13_27_24, BPFCLK_A, SEL_FM_0),
1262 PINMUX_IPSR_GPSR(IP13_27_24, AUDIO_CLKOUT2_A),
1263
1264 PINMUX_IPSR_GPSR(IP13_31_28, MSIOF0_SYNC),
1265 PINMUX_IPSR_GPSR(IP13_31_28, AUDIO_CLKOUT_A),
1266 PINMUX_IPSR_MSEL(IP13_31_28, TX5_B, SEL_SCIF5_1),
1267 PINMUX_IPSR_MSEL(IP13_31_28, BPFCLK_D, SEL_FM_3),
1268
1269 /* IPSR14 */
1270 PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1),
1271 PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0),
1272 PINMUX_IPSR_GPSR(IP14_3_0, NFWP_N_A),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1273 PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADGA_2),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1274 PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1275 PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
1276 PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A),
1277 PINMUX_IPSR_MSEL(IP14_3_0, TCLK1_B, SEL_TIMER_TMU1_1),
1278
1279 PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2),
1280 PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0),
1281 PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1282 PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADGC_0),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1283 PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI2_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1284 PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3),
1285 PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D),
1286 PINMUX_IPSR_MSEL(IP14_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1),
1287
1288 PINMUX_IPSR_GPSR(IP14_11_8, MLB_CLK),
1289 PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SCK_F, SEL_MSIOF1_5),
1290 PINMUX_IPSR_MSEL(IP14_11_8, SCL1_B, SEL_I2C1_1),
1291
1292 PINMUX_IPSR_GPSR(IP14_15_12, MLB_SIG),
1293 PINMUX_IPSR_MSEL(IP14_15_12, RX1_B, SEL_SCIF1_1),
1294 PINMUX_IPSR_MSEL(IP14_15_12, MSIOF1_SYNC_F, SEL_MSIOF1_5),
1295 PINMUX_IPSR_MSEL(IP14_15_12, SDA1_B, SEL_I2C1_1),
1296
1297 PINMUX_IPSR_GPSR(IP14_19_16, MLB_DAT),
1298 PINMUX_IPSR_MSEL(IP14_19_16, TX1_B, SEL_SCIF1_1),
1299 PINMUX_IPSR_MSEL(IP14_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5),
1300
1301 PINMUX_IPSR_GPSR(IP14_23_20, SSI_SCK01239),
1302 PINMUX_IPSR_MSEL(IP14_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5),
1303
1304 PINMUX_IPSR_GPSR(IP14_27_24, SSI_WS01239),
1305 PINMUX_IPSR_MSEL(IP14_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5),
1306
1307 PINMUX_IPSR_GPSR(IP14_31_28, SSI_SDATA0),
1308 PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5),
1309
1310 /* IPSR15 */
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1311 PINMUX_IPSR_MSEL(IP15_3_0, SSI_SDATA1_A, SEL_SSI1_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1312
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1313 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SDATA2_A, SEL_SSI2_0),
1314 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SCK1_B, SEL_SSI1_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1315
1316 PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK349),
1317 PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0),
1318 PINMUX_IPSR_MSEL(IP15_11_8, STP_OPWM_0_A, SEL_SSP1_0_0),
1319
1320 PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS349),
1321 PINMUX_IPSR_MSEL(IP15_15_12, HCTS2_N_A, SEL_HSCIF2_0),
1322 PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0),
1323 PINMUX_IPSR_MSEL(IP15_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0),
1324
1325 PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA3),
1326 PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0),
1327 PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_TXD_A, SEL_MSIOF1_0),
1328 PINMUX_IPSR_MSEL(IP15_19_16, TS_SCK0_A, SEL_TSIF0_0),
1329 PINMUX_IPSR_MSEL(IP15_19_16, STP_ISCLK_0_A, SEL_SSP1_0_0),
1330 PINMUX_IPSR_MSEL(IP15_19_16, RIF0_D1_A, SEL_DRIF0_0),
1331 PINMUX_IPSR_MSEL(IP15_19_16, RIF2_D0_A, SEL_DRIF2_0),
1332
1333 PINMUX_IPSR_GPSR(IP15_23_20, SSI_SCK4),
1334 PINMUX_IPSR_MSEL(IP15_23_20, HRX2_A, SEL_HSCIF2_0),
1335 PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_SCK_A, SEL_MSIOF1_0),
1336 PINMUX_IPSR_MSEL(IP15_23_20, TS_SDAT0_A, SEL_TSIF0_0),
1337 PINMUX_IPSR_MSEL(IP15_23_20, STP_ISD_0_A, SEL_SSP1_0_0),
1338 PINMUX_IPSR_MSEL(IP15_23_20, RIF0_CLK_A, SEL_DRIF0_0),
1339 PINMUX_IPSR_MSEL(IP15_23_20, RIF2_CLK_A, SEL_DRIF2_0),
1340
1341 PINMUX_IPSR_GPSR(IP15_27_24, SSI_WS4),
1342 PINMUX_IPSR_MSEL(IP15_27_24, HTX2_A, SEL_HSCIF2_0),
1343 PINMUX_IPSR_MSEL(IP15_27_24, MSIOF1_SYNC_A, SEL_MSIOF1_0),
1344 PINMUX_IPSR_MSEL(IP15_27_24, TS_SDEN0_A, SEL_TSIF0_0),
1345 PINMUX_IPSR_MSEL(IP15_27_24, STP_ISEN_0_A, SEL_SSP1_0_0),
1346 PINMUX_IPSR_MSEL(IP15_27_24, RIF0_SYNC_A, SEL_DRIF0_0),
1347 PINMUX_IPSR_MSEL(IP15_27_24, RIF2_SYNC_A, SEL_DRIF2_0),
1348
1349 PINMUX_IPSR_GPSR(IP15_31_28, SSI_SDATA4),
1350 PINMUX_IPSR_MSEL(IP15_31_28, HSCK2_A, SEL_HSCIF2_0),
1351 PINMUX_IPSR_MSEL(IP15_31_28, MSIOF1_RXD_A, SEL_MSIOF1_0),
1352 PINMUX_IPSR_MSEL(IP15_31_28, TS_SPSYNC0_A, SEL_TSIF0_0),
1353 PINMUX_IPSR_MSEL(IP15_31_28, STP_ISSYNC_0_A, SEL_SSP1_0_0),
1354 PINMUX_IPSR_MSEL(IP15_31_28, RIF0_D0_A, SEL_DRIF0_0),
1355 PINMUX_IPSR_MSEL(IP15_31_28, RIF2_D1_A, SEL_DRIF2_0),
1356
1357 /* IPSR16 */
1358 PINMUX_IPSR_GPSR(IP16_3_0, SSI_SCK6),
1359 PINMUX_IPSR_GPSR(IP16_3_0, USB2_PWEN),
1360 PINMUX_IPSR_MSEL(IP16_3_0, SIM0_RST_D, SEL_SIMCARD_3),
1361
1362 PINMUX_IPSR_GPSR(IP16_7_4, SSI_WS6),
1363 PINMUX_IPSR_GPSR(IP16_7_4, USB2_OVC),
1364 PINMUX_IPSR_MSEL(IP16_7_4, SIM0_D_D, SEL_SIMCARD_3),
1365
1366 PINMUX_IPSR_GPSR(IP16_11_8, SSI_SDATA6),
1367 PINMUX_IPSR_MSEL(IP16_11_8, SIM0_CLK_D, SEL_SIMCARD_3),
1368 PINMUX_IPSR_GPSR(IP16_11_8, SATA_DEVSLP_A),
1369
1370 PINMUX_IPSR_GPSR(IP16_15_12, SSI_SCK78),
1371 PINMUX_IPSR_MSEL(IP16_15_12, HRX2_B, SEL_HSCIF2_1),
1372 PINMUX_IPSR_MSEL(IP16_15_12, MSIOF1_SCK_C, SEL_MSIOF1_2),
1373 PINMUX_IPSR_MSEL(IP16_15_12, TS_SCK1_A, SEL_TSIF1_0),
1374 PINMUX_IPSR_MSEL(IP16_15_12, STP_ISCLK_1_A, SEL_SSP1_1_0),
1375 PINMUX_IPSR_MSEL(IP16_15_12, RIF1_CLK_A, SEL_DRIF1_0),
1376 PINMUX_IPSR_MSEL(IP16_15_12, RIF3_CLK_A, SEL_DRIF3_0),
1377
1378 PINMUX_IPSR_GPSR(IP16_19_16, SSI_WS78),
1379 PINMUX_IPSR_MSEL(IP16_19_16, HTX2_B, SEL_HSCIF2_1),
1380 PINMUX_IPSR_MSEL(IP16_19_16, MSIOF1_SYNC_C, SEL_MSIOF1_2),
1381 PINMUX_IPSR_MSEL(IP16_19_16, TS_SDAT1_A, SEL_TSIF1_0),
1382 PINMUX_IPSR_MSEL(IP16_19_16, STP_ISD_1_A, SEL_SSP1_1_0),
1383 PINMUX_IPSR_MSEL(IP16_19_16, RIF1_SYNC_A, SEL_DRIF1_0),
1384 PINMUX_IPSR_MSEL(IP16_19_16, RIF3_SYNC_A, SEL_DRIF3_0),
1385
1386 PINMUX_IPSR_GPSR(IP16_23_20, SSI_SDATA7),
1387 PINMUX_IPSR_MSEL(IP16_23_20, HCTS2_N_B, SEL_HSCIF2_1),
1388 PINMUX_IPSR_MSEL(IP16_23_20, MSIOF1_RXD_C, SEL_MSIOF1_2),
1389 PINMUX_IPSR_MSEL(IP16_23_20, TS_SDEN1_A, SEL_TSIF1_0),
1390 PINMUX_IPSR_MSEL(IP16_23_20, STP_ISEN_1_A, SEL_SSP1_1_0),
1391 PINMUX_IPSR_MSEL(IP16_23_20, RIF1_D0_A, SEL_DRIF1_0),
1392 PINMUX_IPSR_MSEL(IP16_23_20, RIF3_D0_A, SEL_DRIF3_0),
1393 PINMUX_IPSR_MSEL(IP16_23_20, TCLK2_A, SEL_TIMER_TMU2_0),
1394
1395 PINMUX_IPSR_GPSR(IP16_27_24, SSI_SDATA8),
1396 PINMUX_IPSR_MSEL(IP16_27_24, HRTS2_N_B, SEL_HSCIF2_1),
1397 PINMUX_IPSR_MSEL(IP16_27_24, MSIOF1_TXD_C, SEL_MSIOF1_2),
1398 PINMUX_IPSR_MSEL(IP16_27_24, TS_SPSYNC1_A, SEL_TSIF1_0),
1399 PINMUX_IPSR_MSEL(IP16_27_24, STP_ISSYNC_1_A, SEL_SSP1_1_0),
1400 PINMUX_IPSR_MSEL(IP16_27_24, RIF1_D1_A, SEL_DRIF1_0),
1401 PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D1_A, SEL_DRIF3_0),
1402
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1403 PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA9_A, SEL_SSI9_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1404 PINMUX_IPSR_MSEL(IP16_31_28, HSCK2_B, SEL_HSCIF2_1),
1405 PINMUX_IPSR_MSEL(IP16_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2),
1406 PINMUX_IPSR_MSEL(IP16_31_28, HSCK1_A, SEL_HSCIF1_0),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1407 PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI1_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1408 PINMUX_IPSR_GPSR(IP16_31_28, SCK1),
1409 PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0),
1410 PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0),
1411
1412 /* IPSR17 */
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1413 PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADGA_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1414
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1415 PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADGB_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1416 PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0),
1417 PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3),
1418 PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0),
1419 PINMUX_IPSR_MSEL(IP17_7_4, TCLK1_A, SEL_TIMER_TMU1_0),
1420
1421 PINMUX_IPSR_GPSR(IP17_11_8, USB0_PWEN),
1422 PINMUX_IPSR_MSEL(IP17_11_8, SIM0_RST_C, SEL_SIMCARD_2),
1423 PINMUX_IPSR_MSEL(IP17_11_8, TS_SCK1_D, SEL_TSIF1_3),
1424 PINMUX_IPSR_MSEL(IP17_11_8, STP_ISCLK_1_D, SEL_SSP1_1_3),
1425 PINMUX_IPSR_MSEL(IP17_11_8, BPFCLK_B, SEL_FM_1),
1426 PINMUX_IPSR_MSEL(IP17_11_8, RIF3_CLK_B, SEL_DRIF3_1),
1427 PINMUX_IPSR_MSEL(IP17_11_8, HSCK2_C, SEL_HSCIF2_2),
1428
1429 PINMUX_IPSR_GPSR(IP17_15_12, USB0_OVC),
1430 PINMUX_IPSR_MSEL(IP17_15_12, SIM0_D_C, SEL_SIMCARD_2),
1431 PINMUX_IPSR_MSEL(IP17_15_12, TS_SDAT1_D, SEL_TSIF1_3),
1432 PINMUX_IPSR_MSEL(IP17_15_12, STP_ISD_1_D, SEL_SSP1_1_3),
1433 PINMUX_IPSR_MSEL(IP17_15_12, RIF3_SYNC_B, SEL_DRIF3_1),
1434 PINMUX_IPSR_MSEL(IP17_15_12, HRX2_C, SEL_HSCIF2_2),
1435
1436 PINMUX_IPSR_GPSR(IP17_19_16, USB1_PWEN),
1437 PINMUX_IPSR_MSEL(IP17_19_16, SIM0_CLK_C, SEL_SIMCARD_2),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1438 PINMUX_IPSR_MSEL(IP17_19_16, SSI_SCK1_A, SEL_SSI1_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1439 PINMUX_IPSR_MSEL(IP17_19_16, TS_SCK0_E, SEL_TSIF0_4),
1440 PINMUX_IPSR_MSEL(IP17_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4),
1441 PINMUX_IPSR_MSEL(IP17_19_16, FMCLK_B, SEL_FM_1),
1442 PINMUX_IPSR_MSEL(IP17_19_16, RIF2_CLK_B, SEL_DRIF2_1),
1443 PINMUX_IPSR_MSEL(IP17_19_16, SPEEDIN_A, SEL_SPEED_PULSE_0),
1444 PINMUX_IPSR_MSEL(IP17_19_16, HTX2_C, SEL_HSCIF2_2),
1445
1446 PINMUX_IPSR_GPSR(IP17_23_20, USB1_OVC),
1447 PINMUX_IPSR_MSEL(IP17_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1448 PINMUX_IPSR_MSEL(IP17_23_20, SSI_WS1_A, SEL_SSI1_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1449 PINMUX_IPSR_MSEL(IP17_23_20, TS_SDAT0_E, SEL_TSIF0_4),
1450 PINMUX_IPSR_MSEL(IP17_23_20, STP_ISD_0_E, SEL_SSP1_0_4),
1451 PINMUX_IPSR_MSEL(IP17_23_20, FMIN_B, SEL_FM_1),
1452 PINMUX_IPSR_MSEL(IP17_23_20, RIF2_SYNC_B, SEL_DRIF2_1),
1453 PINMUX_IPSR_MSEL(IP17_23_20, REMOCON_B, SEL_REMOCON_1),
1454 PINMUX_IPSR_MSEL(IP17_23_20, HCTS2_N_C, SEL_HSCIF2_2),
1455
1456 PINMUX_IPSR_GPSR(IP17_27_24, USB30_PWEN),
1457 PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_B),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1458 PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI2_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1459 PINMUX_IPSR_MSEL(IP17_27_24, TS_SDEN1_D, SEL_TSIF1_3),
1460 PINMUX_IPSR_MSEL(IP17_27_24, STP_ISEN_1_D, SEL_SSP1_1_3),
1461 PINMUX_IPSR_MSEL(IP17_27_24, STP_OPWM_0_E, SEL_SSP1_0_4),
1462 PINMUX_IPSR_MSEL(IP17_27_24, RIF3_D0_B, SEL_DRIF3_1),
1463 PINMUX_IPSR_MSEL(IP17_27_24, TCLK2_B, SEL_TIMER_TMU2_1),
1464 PINMUX_IPSR_GPSR(IP17_27_24, TPU0TO0),
1465 PINMUX_IPSR_MSEL(IP17_27_24, BPFCLK_C, SEL_FM_2),
1466 PINMUX_IPSR_MSEL(IP17_27_24, HRTS2_N_C, SEL_HSCIF2_2),
1467
1468 PINMUX_IPSR_GPSR(IP17_31_28, USB30_OVC),
1469 PINMUX_IPSR_GPSR(IP17_31_28, AUDIO_CLKOUT1_B),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1470 PINMUX_IPSR_MSEL(IP17_31_28, SSI_WS2_B, SEL_SSI2_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1471 PINMUX_IPSR_MSEL(IP17_31_28, TS_SPSYNC1_D, SEL_TSIF1_3),
1472 PINMUX_IPSR_MSEL(IP17_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3),
1473 PINMUX_IPSR_MSEL(IP17_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4),
1474 PINMUX_IPSR_MSEL(IP17_31_28, RIF3_D1_B, SEL_DRIF3_1),
1475 PINMUX_IPSR_GPSR(IP17_31_28, FSO_TOE_N),
1476 PINMUX_IPSR_GPSR(IP17_31_28, TPU0TO1),
1477
1478 /* IPSR18 */
1479 PINMUX_IPSR_GPSR(IP18_3_0, USB2_CH3_PWEN),
1480 PINMUX_IPSR_GPSR(IP18_3_0, AUDIO_CLKOUT2_B),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1481 PINMUX_IPSR_MSEL(IP18_3_0, SSI_SCK9_B, SEL_SSI9_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1482 PINMUX_IPSR_MSEL(IP18_3_0, TS_SDEN0_E, SEL_TSIF0_4),
1483 PINMUX_IPSR_MSEL(IP18_3_0, STP_ISEN_0_E, SEL_SSP1_0_4),
1484 PINMUX_IPSR_MSEL(IP18_3_0, RIF2_D0_B, SEL_DRIF2_1),
1485 PINMUX_IPSR_GPSR(IP18_3_0, TPU0TO2),
1486 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_C, SEL_FM_2),
1487 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_D, SEL_FM_3),
1488
1489 PINMUX_IPSR_GPSR(IP18_7_4, USB2_CH3_OVC),
1490 PINMUX_IPSR_GPSR(IP18_7_4, AUDIO_CLKOUT3_B),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1491 PINMUX_IPSR_MSEL(IP18_7_4, SSI_WS9_B, SEL_SSI9_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1492 PINMUX_IPSR_MSEL(IP18_7_4, TS_SPSYNC0_E, SEL_TSIF0_4),
1493 PINMUX_IPSR_MSEL(IP18_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4),
1494 PINMUX_IPSR_MSEL(IP18_7_4, RIF2_D1_B, SEL_DRIF2_1),
1495 PINMUX_IPSR_GPSR(IP18_7_4, TPU0TO3),
1496 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_C, SEL_FM_2),
1497 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_D, SEL_FM_3),
1498
1499/*
1500 * Static pins can not be muxed between different functions but
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]1501 * still need mark entries in the pinmux list. Add each static
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1502 * pin to the list without an associated function. The sh-pfc
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]1503 * core will do the right thing and skip trying to mux the pin
1504 * while still applying configuration to it.
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1505 */
1506#define FM(x) PINMUX_DATA(x##_MARK, 0),
1507 PINMUX_STATIC
1508#undef FM
1509};
1510
1511/*
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1512 * R8A7795 has 8 banks with 32 GPIOs in each => 256 GPIOs.
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1513 * Physical layout rows: A - AW, cols: 1 - 39.
1514 */
1515#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
1516#define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300)
1517#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1518#define PIN_NONE U16_MAX
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1519
1520static const struct sh_pfc_pin pinmux_pins[] = {
1521 PINMUX_GPIO_GP_ALL(),
1522
1523 /*
1524 * Pins not associated with a GPIO port.
1525 *
1526 * The pin positions are different between different r8a7795
1527 * packages, all that is needed for the pfc driver is a unique
1528 * number for each pin. To this end use the pin layout from
1529 * R-Car H3SiP to calculate a unique number for each pin.
1530 */
1531 SH_PFC_PIN_NAMED_CFG('A', 8, AVB_TX_CTL, CFG_FLAGS),
1532 SH_PFC_PIN_NAMED_CFG('A', 9, AVB_MDIO, CFG_FLAGS),
1533 SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, CFG_FLAGS),
1534 SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, CFG_FLAGS),
1535 SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, CFG_FLAGS),
1536 SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, CFG_FLAGS),
1537 SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, CFG_FLAGS),
1538 SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, CFG_FLAGS),
1539 SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, CFG_FLAGS),
1540 SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, CFG_FLAGS),
1541 SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, CFG_FLAGS),
1542 SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, CFG_FLAGS),
1543 SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, CFG_FLAGS),
1544 SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, CFG_FLAGS),
1545 SH_PFC_PIN_NAMED_CFG('C', 1, PRESETOUT#, CFG_FLAGS),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1546 SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, CFG_FLAGS),
1547 SH_PFC_PIN_NAMED_CFG('V', 3, QSPI1_SPCLK, CFG_FLAGS),
1548 SH_PFC_PIN_NAMED_CFG('V', 5, QSPI1_SSL, CFG_FLAGS),
1549 SH_PFC_PIN_NAMED_CFG('V', 6, RPC_WP#, CFG_FLAGS),
1550 SH_PFC_PIN_NAMED_CFG('V', 7, RPC_RESET#, CFG_FLAGS),
1551 SH_PFC_PIN_NAMED_CFG('W', 3, QSPI0_SPCLK, CFG_FLAGS),
1552 SH_PFC_PIN_NAMED_CFG('Y', 3, QSPI0_SSL, CFG_FLAGS),
1553 SH_PFC_PIN_NAMED_CFG('Y', 6, QSPI0_IO2, CFG_FLAGS),
1554 SH_PFC_PIN_NAMED_CFG('Y', 7, RPC_INT#, CFG_FLAGS),
1555 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 4, QSPI0_MISO_IO1, CFG_FLAGS),
1556 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 6, QSPI0_IO3, CFG_FLAGS),
1557 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 3, QSPI1_IO3, CFG_FLAGS),
1558 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 5, QSPI0_MOSI_IO0, CFG_FLAGS),
1559 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 7, QSPI1_MOSI_IO0, CFG_FLAGS),
1560 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST#, CFG_FLAGS),
1561 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1562 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 4, QSPI1_IO2, CFG_FLAGS),
1563 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 5, QSPI1_MISO_IO1, CFG_FLAGS),
1564 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 7, DU_DOTCLKIN0, CFG_FLAGS),
1565 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 8, DU_DOTCLKIN1, CFG_FLAGS),
1566 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 7, DU_DOTCLKIN2, CFG_FLAGS),
1567 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 8, DU_DOTCLKIN3, CFG_FLAGS),
1568 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1569 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1570 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS),
1571 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1572 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
1573 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS),
1574};
1575
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1576/* - AUDIO CLOCK ------------------------------------------------------------ */
1577static const unsigned int audio_clk_a_a_pins[] = {
1578 /* CLK A */
1579 RCAR_GP_PIN(6, 22),
1580};
1581static const unsigned int audio_clk_a_a_mux[] = {
1582 AUDIO_CLKA_A_MARK,
1583};
1584static const unsigned int audio_clk_a_b_pins[] = {
1585 /* CLK A */
1586 RCAR_GP_PIN(5, 4),
1587};
1588static const unsigned int audio_clk_a_b_mux[] = {
1589 AUDIO_CLKA_B_MARK,
1590};
1591static const unsigned int audio_clk_a_c_pins[] = {
1592 /* CLK A */
1593 RCAR_GP_PIN(5, 19),
1594};
1595static const unsigned int audio_clk_a_c_mux[] = {
1596 AUDIO_CLKA_C_MARK,
1597};
1598static const unsigned int audio_clk_b_a_pins[] = {
1599 /* CLK B */
1600 RCAR_GP_PIN(5, 12),
1601};
1602static const unsigned int audio_clk_b_a_mux[] = {
1603 AUDIO_CLKB_A_MARK,
1604};
1605static const unsigned int audio_clk_b_b_pins[] = {
1606 /* CLK B */
1607 RCAR_GP_PIN(6, 23),
1608};
1609static const unsigned int audio_clk_b_b_mux[] = {
1610 AUDIO_CLKB_B_MARK,
1611};
1612static const unsigned int audio_clk_c_a_pins[] = {
1613 /* CLK C */
1614 RCAR_GP_PIN(5, 21),
1615};
1616static const unsigned int audio_clk_c_a_mux[] = {
1617 AUDIO_CLKC_A_MARK,
1618};
1619static const unsigned int audio_clk_c_b_pins[] = {
1620 /* CLK C */
1621 RCAR_GP_PIN(5, 0),
1622};
1623static const unsigned int audio_clk_c_b_mux[] = {
1624 AUDIO_CLKC_B_MARK,
1625};
1626static const unsigned int audio_clkout_a_pins[] = {
1627 /* CLKOUT */
1628 RCAR_GP_PIN(5, 18),
1629};
1630static const unsigned int audio_clkout_a_mux[] = {
1631 AUDIO_CLKOUT_A_MARK,
1632};
1633static const unsigned int audio_clkout_b_pins[] = {
1634 /* CLKOUT */
1635 RCAR_GP_PIN(6, 28),
1636};
1637static const unsigned int audio_clkout_b_mux[] = {
1638 AUDIO_CLKOUT_B_MARK,
1639};
1640static const unsigned int audio_clkout_c_pins[] = {
1641 /* CLKOUT */
1642 RCAR_GP_PIN(5, 3),
1643};
1644static const unsigned int audio_clkout_c_mux[] = {
1645 AUDIO_CLKOUT_C_MARK,
1646};
1647static const unsigned int audio_clkout_d_pins[] = {
1648 /* CLKOUT */
1649 RCAR_GP_PIN(5, 21),
1650};
1651static const unsigned int audio_clkout_d_mux[] = {
1652 AUDIO_CLKOUT_D_MARK,
1653};
1654static const unsigned int audio_clkout1_a_pins[] = {
1655 /* CLKOUT1 */
1656 RCAR_GP_PIN(5, 15),
1657};
1658static const unsigned int audio_clkout1_a_mux[] = {
1659 AUDIO_CLKOUT1_A_MARK,
1660};
1661static const unsigned int audio_clkout1_b_pins[] = {
1662 /* CLKOUT1 */
1663 RCAR_GP_PIN(6, 29),
1664};
1665static const unsigned int audio_clkout1_b_mux[] = {
1666 AUDIO_CLKOUT1_B_MARK,
1667};
1668static const unsigned int audio_clkout2_a_pins[] = {
1669 /* CLKOUT2 */
1670 RCAR_GP_PIN(5, 16),
1671};
1672static const unsigned int audio_clkout2_a_mux[] = {
1673 AUDIO_CLKOUT2_A_MARK,
1674};
1675static const unsigned int audio_clkout2_b_pins[] = {
1676 /* CLKOUT2 */
1677 RCAR_GP_PIN(6, 30),
1678};
1679static const unsigned int audio_clkout2_b_mux[] = {
1680 AUDIO_CLKOUT2_B_MARK,
1681};
1682static const unsigned int audio_clkout3_a_pins[] = {
1683 /* CLKOUT3 */
1684 RCAR_GP_PIN(5, 19),
1685};
1686static const unsigned int audio_clkout3_a_mux[] = {
1687 AUDIO_CLKOUT3_A_MARK,
1688};
1689static const unsigned int audio_clkout3_b_pins[] = {
1690 /* CLKOUT3 */
1691 RCAR_GP_PIN(6, 31),
1692};
1693static const unsigned int audio_clkout3_b_mux[] = {
1694 AUDIO_CLKOUT3_B_MARK,
1695};
1696
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1697/* - EtherAVB --------------------------------------------------------------- */
1698static const unsigned int avb_link_pins[] = {
1699 /* AVB_LINK */
1700 RCAR_GP_PIN(2, 12),
1701};
1702static const unsigned int avb_link_mux[] = {
1703 AVB_LINK_MARK,
1704};
1705static const unsigned int avb_magic_pins[] = {
1706 /* AVB_MAGIC_ */
1707 RCAR_GP_PIN(2, 10),
1708};
1709static const unsigned int avb_magic_mux[] = {
1710 AVB_MAGIC_MARK,
1711};
1712static const unsigned int avb_phy_int_pins[] = {
1713 /* AVB_PHY_INT */
1714 RCAR_GP_PIN(2, 11),
1715};
1716static const unsigned int avb_phy_int_mux[] = {
1717 AVB_PHY_INT_MARK,
1718};
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1719static const unsigned int avb_mdio_pins[] = {
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1720 /* AVB_MDC, AVB_MDIO */
1721 RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9),
1722};
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1723static const unsigned int avb_mdio_mux[] = {
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1724 AVB_MDC_MARK, AVB_MDIO_MARK,
1725};
1726static const unsigned int avb_mii_pins[] = {
1727 /*
1728 * AVB_TX_CTL, AVB_TXC, AVB_TD0,
1729 * AVB_TD1, AVB_TD2, AVB_TD3,
1730 * AVB_RX_CTL, AVB_RXC, AVB_RD0,
1731 * AVB_RD1, AVB_RD2, AVB_RD3,
1732 * AVB_TXCREFCLK
1733 */
1734 PIN_NUMBER('A', 8), PIN_NUMBER('A', 19), PIN_NUMBER('A', 18),
1735 PIN_NUMBER('B', 18), PIN_NUMBER('A', 17), PIN_NUMBER('B', 17),
1736 PIN_NUMBER('A', 16), PIN_NUMBER('B', 19), PIN_NUMBER('A', 13),
1737 PIN_NUMBER('B', 13), PIN_NUMBER('A', 14), PIN_NUMBER('B', 14),
1738 PIN_NUMBER('A', 12),
1739
1740};
1741static const unsigned int avb_mii_mux[] = {
1742 AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
1743 AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
1744 AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
1745 AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
1746 AVB_TXCREFCLK_MARK,
1747};
1748static const unsigned int avb_avtp_pps_pins[] = {
1749 /* AVB_AVTP_PPS */
1750 RCAR_GP_PIN(2, 6),
1751};
1752static const unsigned int avb_avtp_pps_mux[] = {
1753 AVB_AVTP_PPS_MARK,
1754};
1755static const unsigned int avb_avtp_match_a_pins[] = {
1756 /* AVB_AVTP_MATCH_A */
1757 RCAR_GP_PIN(2, 13),
1758};
1759static const unsigned int avb_avtp_match_a_mux[] = {
1760 AVB_AVTP_MATCH_A_MARK,
1761};
1762static const unsigned int avb_avtp_capture_a_pins[] = {
1763 /* AVB_AVTP_CAPTURE_A */
1764 RCAR_GP_PIN(2, 14),
1765};
1766static const unsigned int avb_avtp_capture_a_mux[] = {
1767 AVB_AVTP_CAPTURE_A_MARK,
1768};
1769static const unsigned int avb_avtp_match_b_pins[] = {
1770 /* AVB_AVTP_MATCH_B */
1771 RCAR_GP_PIN(1, 8),
1772};
1773static const unsigned int avb_avtp_match_b_mux[] = {
1774 AVB_AVTP_MATCH_B_MARK,
1775};
1776static const unsigned int avb_avtp_capture_b_pins[] = {
1777 /* AVB_AVTP_CAPTURE_B */
1778 RCAR_GP_PIN(1, 11),
1779};
1780static const unsigned int avb_avtp_capture_b_mux[] = {
1781 AVB_AVTP_CAPTURE_B_MARK,
1782};
1783
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1784/* - CAN ------------------------------------------------------------------ */
1785static const unsigned int can0_data_a_pins[] = {
1786 /* TX, RX */
1787 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1788};
1789static const unsigned int can0_data_a_mux[] = {
1790 CAN0_TX_A_MARK, CAN0_RX_A_MARK,
1791};
1792static const unsigned int can0_data_b_pins[] = {
1793 /* TX, RX */
1794 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1795};
1796static const unsigned int can0_data_b_mux[] = {
1797 CAN0_TX_B_MARK, CAN0_RX_B_MARK,
1798};
1799static const unsigned int can1_data_pins[] = {
1800 /* TX, RX */
1801 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1802};
1803static const unsigned int can1_data_mux[] = {
1804 CAN1_TX_MARK, CAN1_RX_MARK,
1805};
1806
1807/* - CAN Clock -------------------------------------------------------------- */
1808static const unsigned int can_clk_pins[] = {
1809 /* CLK */
1810 RCAR_GP_PIN(1, 25),
1811};
1812static const unsigned int can_clk_mux[] = {
1813 CAN_CLK_MARK,
1814};
1815
1816/* - CAN FD --------------------------------------------------------------- */
1817static const unsigned int canfd0_data_a_pins[] = {
1818 /* TX, RX */
1819 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1820};
1821static const unsigned int canfd0_data_a_mux[] = {
1822 CANFD0_TX_A_MARK, CANFD0_RX_A_MARK,
1823};
1824static const unsigned int canfd0_data_b_pins[] = {
1825 /* TX, RX */
1826 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1827};
1828static const unsigned int canfd0_data_b_mux[] = {
1829 CANFD0_TX_B_MARK, CANFD0_RX_B_MARK,
1830};
1831static const unsigned int canfd1_data_pins[] = {
1832 /* TX, RX */
1833 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1834};
1835static const unsigned int canfd1_data_mux[] = {
1836 CANFD1_TX_MARK, CANFD1_RX_MARK,
1837};
1838
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1839/* - DRIF0 --------------------------------------------------------------- */
1840static const unsigned int drif0_ctrl_a_pins[] = {
1841 /* CLK, SYNC */
1842 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1843};
1844static const unsigned int drif0_ctrl_a_mux[] = {
1845 RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
1846};
1847static const unsigned int drif0_data0_a_pins[] = {
1848 /* D0 */
1849 RCAR_GP_PIN(6, 10),
1850};
1851static const unsigned int drif0_data0_a_mux[] = {
1852 RIF0_D0_A_MARK,
1853};
1854static const unsigned int drif0_data1_a_pins[] = {
1855 /* D1 */
1856 RCAR_GP_PIN(6, 7),
1857};
1858static const unsigned int drif0_data1_a_mux[] = {
1859 RIF0_D1_A_MARK,
1860};
1861static const unsigned int drif0_ctrl_b_pins[] = {
1862 /* CLK, SYNC */
1863 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
1864};
1865static const unsigned int drif0_ctrl_b_mux[] = {
1866 RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
1867};
1868static const unsigned int drif0_data0_b_pins[] = {
1869 /* D0 */
1870 RCAR_GP_PIN(5, 1),
1871};
1872static const unsigned int drif0_data0_b_mux[] = {
1873 RIF0_D0_B_MARK,
1874};
1875static const unsigned int drif0_data1_b_pins[] = {
1876 /* D1 */
1877 RCAR_GP_PIN(5, 2),
1878};
1879static const unsigned int drif0_data1_b_mux[] = {
1880 RIF0_D1_B_MARK,
1881};
1882static const unsigned int drif0_ctrl_c_pins[] = {
1883 /* CLK, SYNC */
1884 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15),
1885};
1886static const unsigned int drif0_ctrl_c_mux[] = {
1887 RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK,
1888};
1889static const unsigned int drif0_data0_c_pins[] = {
1890 /* D0 */
1891 RCAR_GP_PIN(5, 13),
1892};
1893static const unsigned int drif0_data0_c_mux[] = {
1894 RIF0_D0_C_MARK,
1895};
1896static const unsigned int drif0_data1_c_pins[] = {
1897 /* D1 */
1898 RCAR_GP_PIN(5, 14),
1899};
1900static const unsigned int drif0_data1_c_mux[] = {
1901 RIF0_D1_C_MARK,
1902};
1903/* - DRIF1 --------------------------------------------------------------- */
1904static const unsigned int drif1_ctrl_a_pins[] = {
1905 /* CLK, SYNC */
1906 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
1907};
1908static const unsigned int drif1_ctrl_a_mux[] = {
1909 RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK,
1910};
1911static const unsigned int drif1_data0_a_pins[] = {
1912 /* D0 */
1913 RCAR_GP_PIN(6, 19),
1914};
1915static const unsigned int drif1_data0_a_mux[] = {
1916 RIF1_D0_A_MARK,
1917};
1918static const unsigned int drif1_data1_a_pins[] = {
1919 /* D1 */
1920 RCAR_GP_PIN(6, 20),
1921};
1922static const unsigned int drif1_data1_a_mux[] = {
1923 RIF1_D1_A_MARK,
1924};
1925static const unsigned int drif1_ctrl_b_pins[] = {
1926 /* CLK, SYNC */
1927 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3),
1928};
1929static const unsigned int drif1_ctrl_b_mux[] = {
1930 RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK,
1931};
1932static const unsigned int drif1_data0_b_pins[] = {
1933 /* D0 */
1934 RCAR_GP_PIN(5, 7),
1935};
1936static const unsigned int drif1_data0_b_mux[] = {
1937 RIF1_D0_B_MARK,
1938};
1939static const unsigned int drif1_data1_b_pins[] = {
1940 /* D1 */
1941 RCAR_GP_PIN(5, 8),
1942};
1943static const unsigned int drif1_data1_b_mux[] = {
1944 RIF1_D1_B_MARK,
1945};
1946static const unsigned int drif1_ctrl_c_pins[] = {
1947 /* CLK, SYNC */
1948 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
1949};
1950static const unsigned int drif1_ctrl_c_mux[] = {
1951 RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK,
1952};
1953static const unsigned int drif1_data0_c_pins[] = {
1954 /* D0 */
1955 RCAR_GP_PIN(5, 6),
1956};
1957static const unsigned int drif1_data0_c_mux[] = {
1958 RIF1_D0_C_MARK,
1959};
1960static const unsigned int drif1_data1_c_pins[] = {
1961 /* D1 */
1962 RCAR_GP_PIN(5, 10),
1963};
1964static const unsigned int drif1_data1_c_mux[] = {
1965 RIF1_D1_C_MARK,
1966};
1967/* - DRIF2 --------------------------------------------------------------- */
1968static const unsigned int drif2_ctrl_a_pins[] = {
1969 /* CLK, SYNC */
1970 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1971};
1972static const unsigned int drif2_ctrl_a_mux[] = {
1973 RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
1974};
1975static const unsigned int drif2_data0_a_pins[] = {
1976 /* D0 */
1977 RCAR_GP_PIN(6, 7),
1978};
1979static const unsigned int drif2_data0_a_mux[] = {
1980 RIF2_D0_A_MARK,
1981};
1982static const unsigned int drif2_data1_a_pins[] = {
1983 /* D1 */
1984 RCAR_GP_PIN(6, 10),
1985};
1986static const unsigned int drif2_data1_a_mux[] = {
1987 RIF2_D1_A_MARK,
1988};
1989static const unsigned int drif2_ctrl_b_pins[] = {
1990 /* CLK, SYNC */
1991 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
1992};
1993static const unsigned int drif2_ctrl_b_mux[] = {
1994 RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
1995};
1996static const unsigned int drif2_data0_b_pins[] = {
1997 /* D0 */
1998 RCAR_GP_PIN(6, 30),
1999};
2000static const unsigned int drif2_data0_b_mux[] = {
2001 RIF2_D0_B_MARK,
2002};
2003static const unsigned int drif2_data1_b_pins[] = {
2004 /* D1 */
2005 RCAR_GP_PIN(6, 31),
2006};
2007static const unsigned int drif2_data1_b_mux[] = {
2008 RIF2_D1_B_MARK,
2009};
2010/* - DRIF3 --------------------------------------------------------------- */
2011static const unsigned int drif3_ctrl_a_pins[] = {
2012 /* CLK, SYNC */
2013 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2014};
2015static const unsigned int drif3_ctrl_a_mux[] = {
2016 RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
2017};
2018static const unsigned int drif3_data0_a_pins[] = {
2019 /* D0 */
2020 RCAR_GP_PIN(6, 19),
2021};
2022static const unsigned int drif3_data0_a_mux[] = {
2023 RIF3_D0_A_MARK,
2024};
2025static const unsigned int drif3_data1_a_pins[] = {
2026 /* D1 */
2027 RCAR_GP_PIN(6, 20),
2028};
2029static const unsigned int drif3_data1_a_mux[] = {
2030 RIF3_D1_A_MARK,
2031};
2032static const unsigned int drif3_ctrl_b_pins[] = {
2033 /* CLK, SYNC */
2034 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
2035};
2036static const unsigned int drif3_ctrl_b_mux[] = {
2037 RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
2038};
2039static const unsigned int drif3_data0_b_pins[] = {
2040 /* D0 */
2041 RCAR_GP_PIN(6, 28),
2042};
2043static const unsigned int drif3_data0_b_mux[] = {
2044 RIF3_D0_B_MARK,
2045};
2046static const unsigned int drif3_data1_b_pins[] = {
2047 /* D1 */
2048 RCAR_GP_PIN(6, 29),
2049};
2050static const unsigned int drif3_data1_b_mux[] = {
2051 RIF3_D1_B_MARK,
2052};
2053
2054/* - DU --------------------------------------------------------------------- */
2055static const unsigned int du_rgb666_pins[] = {
2056 /* R[7:2], G[7:2], B[7:2] */
2057 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2058 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2059 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2060 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2061 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
2062 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
2063};
2064static const unsigned int du_rgb666_mux[] = {
2065 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2066 DU_DR3_MARK, DU_DR2_MARK,
2067 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2068 DU_DG3_MARK, DU_DG2_MARK,
2069 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2070 DU_DB3_MARK, DU_DB2_MARK,
2071};
2072static const unsigned int du_rgb888_pins[] = {
2073 /* R[7:0], G[7:0], B[7:0] */
2074 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2075 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2076 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
2077 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2078 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2079 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
2080 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
2081 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
2082 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
2083};
2084static const unsigned int du_rgb888_mux[] = {
2085 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2086 DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
2087 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2088 DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
2089 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2090 DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
2091};
2092static const unsigned int du_clk_out_0_pins[] = {
2093 /* CLKOUT */
2094 RCAR_GP_PIN(1, 27),
2095};
2096static const unsigned int du_clk_out_0_mux[] = {
2097 DU_DOTCLKOUT0_MARK
2098};
2099static const unsigned int du_clk_out_1_pins[] = {
2100 /* CLKOUT */
2101 RCAR_GP_PIN(2, 3),
2102};
2103static const unsigned int du_clk_out_1_mux[] = {
2104 DU_DOTCLKOUT1_MARK
2105};
2106static const unsigned int du_sync_pins[] = {
2107 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
2108 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
2109};
2110static const unsigned int du_sync_mux[] = {
2111 DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
2112};
2113static const unsigned int du_oddf_pins[] = {
2114 /* EXDISP/EXODDF/EXCDE */
2115 RCAR_GP_PIN(2, 2),
2116};
2117static const unsigned int du_oddf_mux[] = {
2118 DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
2119};
2120static const unsigned int du_cde_pins[] = {
2121 /* CDE */
2122 RCAR_GP_PIN(2, 0),
2123};
2124static const unsigned int du_cde_mux[] = {
2125 DU_CDE_MARK,
2126};
2127static const unsigned int du_disp_pins[] = {
2128 /* DISP */
2129 RCAR_GP_PIN(2, 1),
2130};
2131static const unsigned int du_disp_mux[] = {
2132 DU_DISP_MARK,
2133};
2134
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]2135/* - HSCIF0 ----------------------------------------------------------------- */
2136static const unsigned int hscif0_data_pins[] = {
2137 /* RX, TX */
2138 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
2139};
2140static const unsigned int hscif0_data_mux[] = {
2141 HRX0_MARK, HTX0_MARK,
2142};
2143static const unsigned int hscif0_clk_pins[] = {
2144 /* SCK */
2145 RCAR_GP_PIN(5, 12),
2146};
2147static const unsigned int hscif0_clk_mux[] = {
2148 HSCK0_MARK,
2149};
2150static const unsigned int hscif0_ctrl_pins[] = {
2151 /* RTS, CTS */
2152 RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
2153};
2154static const unsigned int hscif0_ctrl_mux[] = {
2155 HRTS0_N_MARK, HCTS0_N_MARK,
2156};
2157/* - HSCIF1 ----------------------------------------------------------------- */
2158static const unsigned int hscif1_data_a_pins[] = {
2159 /* RX, TX */
2160 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2161};
2162static const unsigned int hscif1_data_a_mux[] = {
2163 HRX1_A_MARK, HTX1_A_MARK,
2164};
2165static const unsigned int hscif1_clk_a_pins[] = {
2166 /* SCK */
2167 RCAR_GP_PIN(6, 21),
2168};
2169static const unsigned int hscif1_clk_a_mux[] = {
2170 HSCK1_A_MARK,
2171};
2172static const unsigned int hscif1_ctrl_a_pins[] = {
2173 /* RTS, CTS */
2174 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
2175};
2176static const unsigned int hscif1_ctrl_a_mux[] = {
2177 HRTS1_N_A_MARK, HCTS1_N_A_MARK,
2178};
2179
2180static const unsigned int hscif1_data_b_pins[] = {
2181 /* RX, TX */
2182 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2183};
2184static const unsigned int hscif1_data_b_mux[] = {
2185 HRX1_B_MARK, HTX1_B_MARK,
2186};
2187static const unsigned int hscif1_clk_b_pins[] = {
2188 /* SCK */
2189 RCAR_GP_PIN(5, 0),
2190};
2191static const unsigned int hscif1_clk_b_mux[] = {
2192 HSCK1_B_MARK,
2193};
2194static const unsigned int hscif1_ctrl_b_pins[] = {
2195 /* RTS, CTS */
2196 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
2197};
2198static const unsigned int hscif1_ctrl_b_mux[] = {
2199 HRTS1_N_B_MARK, HCTS1_N_B_MARK,
2200};
2201/* - HSCIF2 ----------------------------------------------------------------- */
2202static const unsigned int hscif2_data_a_pins[] = {
2203 /* RX, TX */
2204 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
2205};
2206static const unsigned int hscif2_data_a_mux[] = {
2207 HRX2_A_MARK, HTX2_A_MARK,
2208};
2209static const unsigned int hscif2_clk_a_pins[] = {
2210 /* SCK */
2211 RCAR_GP_PIN(6, 10),
2212};
2213static const unsigned int hscif2_clk_a_mux[] = {
2214 HSCK2_A_MARK,
2215};
2216static const unsigned int hscif2_ctrl_a_pins[] = {
2217 /* RTS, CTS */
2218 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
2219};
2220static const unsigned int hscif2_ctrl_a_mux[] = {
2221 HRTS2_N_A_MARK, HCTS2_N_A_MARK,
2222};
2223
2224static const unsigned int hscif2_data_b_pins[] = {
2225 /* RX, TX */
2226 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2227};
2228static const unsigned int hscif2_data_b_mux[] = {
2229 HRX2_B_MARK, HTX2_B_MARK,
2230};
2231static const unsigned int hscif2_clk_b_pins[] = {
2232 /* SCK */
2233 RCAR_GP_PIN(6, 21),
2234};
2235static const unsigned int hscif2_clk_b_mux[] = {
2236 HSCK2_B_MARK,
2237};
2238static const unsigned int hscif2_ctrl_b_pins[] = {
2239 /* RTS, CTS */
2240 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19),
2241};
2242static const unsigned int hscif2_ctrl_b_mux[] = {
2243 HRTS2_N_B_MARK, HCTS2_N_B_MARK,
2244};
2245
2246static const unsigned int hscif2_data_c_pins[] = {
2247 /* RX, TX */
2248 RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26),
2249};
2250static const unsigned int hscif2_data_c_mux[] = {
2251 HRX2_C_MARK, HTX2_C_MARK,
2252};
2253static const unsigned int hscif2_clk_c_pins[] = {
2254 /* SCK */
2255 RCAR_GP_PIN(6, 24),
2256};
2257static const unsigned int hscif2_clk_c_mux[] = {
2258 HSCK2_C_MARK,
2259};
2260static const unsigned int hscif2_ctrl_c_pins[] = {
2261 /* RTS, CTS */
2262 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 27),
2263};
2264static const unsigned int hscif2_ctrl_c_mux[] = {
2265 HRTS2_N_C_MARK, HCTS2_N_C_MARK,
2266};
2267/* - HSCIF3 ----------------------------------------------------------------- */
2268static const unsigned int hscif3_data_a_pins[] = {
2269 /* RX, TX */
2270 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
2271};
2272static const unsigned int hscif3_data_a_mux[] = {
2273 HRX3_A_MARK, HTX3_A_MARK,
2274};
2275static const unsigned int hscif3_clk_pins[] = {
2276 /* SCK */
2277 RCAR_GP_PIN(1, 22),
2278};
2279static const unsigned int hscif3_clk_mux[] = {
2280 HSCK3_MARK,
2281};
2282static const unsigned int hscif3_ctrl_pins[] = {
2283 /* RTS, CTS */
2284 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2285};
2286static const unsigned int hscif3_ctrl_mux[] = {
2287 HRTS3_N_MARK, HCTS3_N_MARK,
2288};
2289
2290static const unsigned int hscif3_data_b_pins[] = {
2291 /* RX, TX */
2292 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
2293};
2294static const unsigned int hscif3_data_b_mux[] = {
2295 HRX3_B_MARK, HTX3_B_MARK,
2296};
2297static const unsigned int hscif3_data_c_pins[] = {
2298 /* RX, TX */
2299 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2300};
2301static const unsigned int hscif3_data_c_mux[] = {
2302 HRX3_C_MARK, HTX3_C_MARK,
2303};
2304static const unsigned int hscif3_data_d_pins[] = {
2305 /* RX, TX */
2306 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2307};
2308static const unsigned int hscif3_data_d_mux[] = {
2309 HRX3_D_MARK, HTX3_D_MARK,
2310};
2311/* - HSCIF4 ----------------------------------------------------------------- */
2312static const unsigned int hscif4_data_a_pins[] = {
2313 /* RX, TX */
2314 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
2315};
2316static const unsigned int hscif4_data_a_mux[] = {
2317 HRX4_A_MARK, HTX4_A_MARK,
2318};
2319static const unsigned int hscif4_clk_pins[] = {
2320 /* SCK */
2321 RCAR_GP_PIN(1, 11),
2322};
2323static const unsigned int hscif4_clk_mux[] = {
2324 HSCK4_MARK,
2325};
2326static const unsigned int hscif4_ctrl_pins[] = {
2327 /* RTS, CTS */
2328 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
2329};
2330static const unsigned int hscif4_ctrl_mux[] = {
2331 HRTS4_N_MARK, HCTS4_N_MARK,
2332};
2333
2334static const unsigned int hscif4_data_b_pins[] = {
2335 /* RX, TX */
2336 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2337};
2338static const unsigned int hscif4_data_b_mux[] = {
2339 HRX4_B_MARK, HTX4_B_MARK,
2340};
2341
2342/* - I2C -------------------------------------------------------------------- */
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]2343static const unsigned int i2c0_pins[] = {
2344 /* SCL, SDA */
2345 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
2346};
2347
2348static const unsigned int i2c0_mux[] = {
2349 SCL0_MARK, SDA0_MARK,
2350};
2351
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]2352static const unsigned int i2c1_a_pins[] = {
2353 /* SDA, SCL */
2354 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
2355};
2356static const unsigned int i2c1_a_mux[] = {
2357 SDA1_A_MARK, SCL1_A_MARK,
2358};
2359static const unsigned int i2c1_b_pins[] = {
2360 /* SDA, SCL */
2361 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
2362};
2363static const unsigned int i2c1_b_mux[] = {
2364 SDA1_B_MARK, SCL1_B_MARK,
2365};
2366static const unsigned int i2c2_a_pins[] = {
2367 /* SDA, SCL */
2368 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
2369};
2370static const unsigned int i2c2_a_mux[] = {
2371 SDA2_A_MARK, SCL2_A_MARK,
2372};
2373static const unsigned int i2c2_b_pins[] = {
2374 /* SDA, SCL */
2375 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
2376};
2377static const unsigned int i2c2_b_mux[] = {
2378 SDA2_B_MARK, SCL2_B_MARK,
2379};
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]2380
2381static const unsigned int i2c3_pins[] = {
2382 /* SCL, SDA */
2383 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2384};
2385
2386static const unsigned int i2c3_mux[] = {
2387 SCL3_MARK, SDA3_MARK,
2388};
2389
2390static const unsigned int i2c5_pins[] = {
2391 /* SCL, SDA */
2392 RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
2393};
2394
2395static const unsigned int i2c5_mux[] = {
2396 SCL5_MARK, SDA5_MARK,
2397};
2398
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]2399static const unsigned int i2c6_a_pins[] = {
2400 /* SDA, SCL */
2401 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2402};
2403static const unsigned int i2c6_a_mux[] = {
2404 SDA6_A_MARK, SCL6_A_MARK,
2405};
2406static const unsigned int i2c6_b_pins[] = {
2407 /* SDA, SCL */
2408 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2409};
2410static const unsigned int i2c6_b_mux[] = {
2411 SDA6_B_MARK, SCL6_B_MARK,
2412};
2413static const unsigned int i2c6_c_pins[] = {
2414 /* SDA, SCL */
2415 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
2416};
2417static const unsigned int i2c6_c_mux[] = {
2418 SDA6_C_MARK, SCL6_C_MARK,
2419};
2420
2421/* - INTC-EX ---------------------------------------------------------------- */
2422static const unsigned int intc_ex_irq0_pins[] = {
2423 /* IRQ0 */
2424 RCAR_GP_PIN(2, 0),
2425};
2426static const unsigned int intc_ex_irq0_mux[] = {
2427 IRQ0_MARK,
2428};
2429static const unsigned int intc_ex_irq1_pins[] = {
2430 /* IRQ1 */
2431 RCAR_GP_PIN(2, 1),
2432};
2433static const unsigned int intc_ex_irq1_mux[] = {
2434 IRQ1_MARK,
2435};
2436static const unsigned int intc_ex_irq2_pins[] = {
2437 /* IRQ2 */
2438 RCAR_GP_PIN(2, 2),
2439};
2440static const unsigned int intc_ex_irq2_mux[] = {
2441 IRQ2_MARK,
2442};
2443static const unsigned int intc_ex_irq3_pins[] = {
2444 /* IRQ3 */
2445 RCAR_GP_PIN(2, 3),
2446};
2447static const unsigned int intc_ex_irq3_mux[] = {
2448 IRQ3_MARK,
2449};
2450static const unsigned int intc_ex_irq4_pins[] = {
2451 /* IRQ4 */
2452 RCAR_GP_PIN(2, 4),
2453};
2454static const unsigned int intc_ex_irq4_mux[] = {
2455 IRQ4_MARK,
2456};
2457static const unsigned int intc_ex_irq5_pins[] = {
2458 /* IRQ5 */
2459 RCAR_GP_PIN(2, 5),
2460};
2461static const unsigned int intc_ex_irq5_mux[] = {
2462 IRQ5_MARK,
2463};
2464
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]2465/* - MSIOF0 ----------------------------------------------------------------- */
2466static const unsigned int msiof0_clk_pins[] = {
2467 /* SCK */
2468 RCAR_GP_PIN(5, 17),
2469};
2470static const unsigned int msiof0_clk_mux[] = {
2471 MSIOF0_SCK_MARK,
2472};
2473static const unsigned int msiof0_sync_pins[] = {
2474 /* SYNC */
2475 RCAR_GP_PIN(5, 18),
2476};
2477static const unsigned int msiof0_sync_mux[] = {
2478 MSIOF0_SYNC_MARK,
2479};
2480static const unsigned int msiof0_ss1_pins[] = {
2481 /* SS1 */
2482 RCAR_GP_PIN(5, 19),
2483};
2484static const unsigned int msiof0_ss1_mux[] = {
2485 MSIOF0_SS1_MARK,
2486};
2487static const unsigned int msiof0_ss2_pins[] = {
2488 /* SS2 */
2489 RCAR_GP_PIN(5, 21),
2490};
2491static const unsigned int msiof0_ss2_mux[] = {
2492 MSIOF0_SS2_MARK,
2493};
2494static const unsigned int msiof0_txd_pins[] = {
2495 /* TXD */
2496 RCAR_GP_PIN(5, 20),
2497};
2498static const unsigned int msiof0_txd_mux[] = {
2499 MSIOF0_TXD_MARK,
2500};
2501static const unsigned int msiof0_rxd_pins[] = {
2502 /* RXD */
2503 RCAR_GP_PIN(5, 22),
2504};
2505static const unsigned int msiof0_rxd_mux[] = {
2506 MSIOF0_RXD_MARK,
2507};
2508/* - MSIOF1 ----------------------------------------------------------------- */
2509static const unsigned int msiof1_clk_a_pins[] = {
2510 /* SCK */
2511 RCAR_GP_PIN(6, 8),
2512};
2513static const unsigned int msiof1_clk_a_mux[] = {
2514 MSIOF1_SCK_A_MARK,
2515};
2516static const unsigned int msiof1_sync_a_pins[] = {
2517 /* SYNC */
2518 RCAR_GP_PIN(6, 9),
2519};
2520static const unsigned int msiof1_sync_a_mux[] = {
2521 MSIOF1_SYNC_A_MARK,
2522};
2523static const unsigned int msiof1_ss1_a_pins[] = {
2524 /* SS1 */
2525 RCAR_GP_PIN(6, 5),
2526};
2527static const unsigned int msiof1_ss1_a_mux[] = {
2528 MSIOF1_SS1_A_MARK,
2529};
2530static const unsigned int msiof1_ss2_a_pins[] = {
2531 /* SS2 */
2532 RCAR_GP_PIN(6, 6),
2533};
2534static const unsigned int msiof1_ss2_a_mux[] = {
2535 MSIOF1_SS2_A_MARK,
2536};
2537static const unsigned int msiof1_txd_a_pins[] = {
2538 /* TXD */
2539 RCAR_GP_PIN(6, 7),
2540};
2541static const unsigned int msiof1_txd_a_mux[] = {
2542 MSIOF1_TXD_A_MARK,
2543};
2544static const unsigned int msiof1_rxd_a_pins[] = {
2545 /* RXD */
2546 RCAR_GP_PIN(6, 10),
2547};
2548static const unsigned int msiof1_rxd_a_mux[] = {
2549 MSIOF1_RXD_A_MARK,
2550};
2551static const unsigned int msiof1_clk_b_pins[] = {
2552 /* SCK */
2553 RCAR_GP_PIN(5, 9),
2554};
2555static const unsigned int msiof1_clk_b_mux[] = {
2556 MSIOF1_SCK_B_MARK,
2557};
2558static const unsigned int msiof1_sync_b_pins[] = {
2559 /* SYNC */
2560 RCAR_GP_PIN(5, 3),
2561};
2562static const unsigned int msiof1_sync_b_mux[] = {
2563 MSIOF1_SYNC_B_MARK,
2564};
2565static const unsigned int msiof1_ss1_b_pins[] = {
2566 /* SS1 */
2567 RCAR_GP_PIN(5, 4),
2568};
2569static const unsigned int msiof1_ss1_b_mux[] = {
2570 MSIOF1_SS1_B_MARK,
2571};
2572static const unsigned int msiof1_ss2_b_pins[] = {
2573 /* SS2 */
2574 RCAR_GP_PIN(5, 0),
2575};
2576static const unsigned int msiof1_ss2_b_mux[] = {
2577 MSIOF1_SS2_B_MARK,
2578};
2579static const unsigned int msiof1_txd_b_pins[] = {
2580 /* TXD */
2581 RCAR_GP_PIN(5, 8),
2582};
2583static const unsigned int msiof1_txd_b_mux[] = {
2584 MSIOF1_TXD_B_MARK,
2585};
2586static const unsigned int msiof1_rxd_b_pins[] = {
2587 /* RXD */
2588 RCAR_GP_PIN(5, 7),
2589};
2590static const unsigned int msiof1_rxd_b_mux[] = {
2591 MSIOF1_RXD_B_MARK,
2592};
2593static const unsigned int msiof1_clk_c_pins[] = {
2594 /* SCK */
2595 RCAR_GP_PIN(6, 17),
2596};
2597static const unsigned int msiof1_clk_c_mux[] = {
2598 MSIOF1_SCK_C_MARK,
2599};
2600static const unsigned int msiof1_sync_c_pins[] = {
2601 /* SYNC */
2602 RCAR_GP_PIN(6, 18),
2603};
2604static const unsigned int msiof1_sync_c_mux[] = {
2605 MSIOF1_SYNC_C_MARK,
2606};
2607static const unsigned int msiof1_ss1_c_pins[] = {
2608 /* SS1 */
2609 RCAR_GP_PIN(6, 21),
2610};
2611static const unsigned int msiof1_ss1_c_mux[] = {
2612 MSIOF1_SS1_C_MARK,
2613};
2614static const unsigned int msiof1_ss2_c_pins[] = {
2615 /* SS2 */
2616 RCAR_GP_PIN(6, 27),
2617};
2618static const unsigned int msiof1_ss2_c_mux[] = {
2619 MSIOF1_SS2_C_MARK,
2620};
2621static const unsigned int msiof1_txd_c_pins[] = {
2622 /* TXD */
2623 RCAR_GP_PIN(6, 20),
2624};
2625static const unsigned int msiof1_txd_c_mux[] = {
2626 MSIOF1_TXD_C_MARK,
2627};
2628static const unsigned int msiof1_rxd_c_pins[] = {
2629 /* RXD */
2630 RCAR_GP_PIN(6, 19),
2631};
2632static const unsigned int msiof1_rxd_c_mux[] = {
2633 MSIOF1_RXD_C_MARK,
2634};
2635static const unsigned int msiof1_clk_d_pins[] = {
2636 /* SCK */
2637 RCAR_GP_PIN(5, 12),
2638};
2639static const unsigned int msiof1_clk_d_mux[] = {
2640 MSIOF1_SCK_D_MARK,
2641};
2642static const unsigned int msiof1_sync_d_pins[] = {
2643 /* SYNC */
2644 RCAR_GP_PIN(5, 15),
2645};
2646static const unsigned int msiof1_sync_d_mux[] = {
2647 MSIOF1_SYNC_D_MARK,
2648};
2649static const unsigned int msiof1_ss1_d_pins[] = {
2650 /* SS1 */
2651 RCAR_GP_PIN(5, 16),
2652};
2653static const unsigned int msiof1_ss1_d_mux[] = {
2654 MSIOF1_SS1_D_MARK,
2655};
2656static const unsigned int msiof1_ss2_d_pins[] = {
2657 /* SS2 */
2658 RCAR_GP_PIN(5, 21),
2659};
2660static const unsigned int msiof1_ss2_d_mux[] = {
2661 MSIOF1_SS2_D_MARK,
2662};
2663static const unsigned int msiof1_txd_d_pins[] = {
2664 /* TXD */
2665 RCAR_GP_PIN(5, 14),
2666};
2667static const unsigned int msiof1_txd_d_mux[] = {
2668 MSIOF1_TXD_D_MARK,
2669};
2670static const unsigned int msiof1_rxd_d_pins[] = {
2671 /* RXD */
2672 RCAR_GP_PIN(5, 13),
2673};
2674static const unsigned int msiof1_rxd_d_mux[] = {
2675 MSIOF1_RXD_D_MARK,
2676};
2677static const unsigned int msiof1_clk_e_pins[] = {
2678 /* SCK */
2679 RCAR_GP_PIN(3, 0),
2680};
2681static const unsigned int msiof1_clk_e_mux[] = {
2682 MSIOF1_SCK_E_MARK,
2683};
2684static const unsigned int msiof1_sync_e_pins[] = {
2685 /* SYNC */
2686 RCAR_GP_PIN(3, 1),
2687};
2688static const unsigned int msiof1_sync_e_mux[] = {
2689 MSIOF1_SYNC_E_MARK,
2690};
2691static const unsigned int msiof1_ss1_e_pins[] = {
2692 /* SS1 */
2693 RCAR_GP_PIN(3, 4),
2694};
2695static const unsigned int msiof1_ss1_e_mux[] = {
2696 MSIOF1_SS1_E_MARK,
2697};
2698static const unsigned int msiof1_ss2_e_pins[] = {
2699 /* SS2 */
2700 RCAR_GP_PIN(3, 5),
2701};
2702static const unsigned int msiof1_ss2_e_mux[] = {
2703 MSIOF1_SS2_E_MARK,
2704};
2705static const unsigned int msiof1_txd_e_pins[] = {
2706 /* TXD */
2707 RCAR_GP_PIN(3, 3),
2708};
2709static const unsigned int msiof1_txd_e_mux[] = {
2710 MSIOF1_TXD_E_MARK,
2711};
2712static const unsigned int msiof1_rxd_e_pins[] = {
2713 /* RXD */
2714 RCAR_GP_PIN(3, 2),
2715};
2716static const unsigned int msiof1_rxd_e_mux[] = {
2717 MSIOF1_RXD_E_MARK,
2718};
2719static const unsigned int msiof1_clk_f_pins[] = {
2720 /* SCK */
2721 RCAR_GP_PIN(5, 23),
2722};
2723static const unsigned int msiof1_clk_f_mux[] = {
2724 MSIOF1_SCK_F_MARK,
2725};
2726static const unsigned int msiof1_sync_f_pins[] = {
2727 /* SYNC */
2728 RCAR_GP_PIN(5, 24),
2729};
2730static const unsigned int msiof1_sync_f_mux[] = {
2731 MSIOF1_SYNC_F_MARK,
2732};
2733static const unsigned int msiof1_ss1_f_pins[] = {
2734 /* SS1 */
2735 RCAR_GP_PIN(6, 1),
2736};
2737static const unsigned int msiof1_ss1_f_mux[] = {
2738 MSIOF1_SS1_F_MARK,
2739};
2740static const unsigned int msiof1_ss2_f_pins[] = {
2741 /* SS2 */
2742 RCAR_GP_PIN(6, 2),
2743};
2744static const unsigned int msiof1_ss2_f_mux[] = {
2745 MSIOF1_SS2_F_MARK,
2746};
2747static const unsigned int msiof1_txd_f_pins[] = {
2748 /* TXD */
2749 RCAR_GP_PIN(6, 0),
2750};
2751static const unsigned int msiof1_txd_f_mux[] = {
2752 MSIOF1_TXD_F_MARK,
2753};
2754static const unsigned int msiof1_rxd_f_pins[] = {
2755 /* RXD */
2756 RCAR_GP_PIN(5, 25),
2757};
2758static const unsigned int msiof1_rxd_f_mux[] = {
2759 MSIOF1_RXD_F_MARK,
2760};
2761static const unsigned int msiof1_clk_g_pins[] = {
2762 /* SCK */
2763 RCAR_GP_PIN(3, 6),
2764};
2765static const unsigned int msiof1_clk_g_mux[] = {
2766 MSIOF1_SCK_G_MARK,
2767};
2768static const unsigned int msiof1_sync_g_pins[] = {
2769 /* SYNC */
2770 RCAR_GP_PIN(3, 7),
2771};
2772static const unsigned int msiof1_sync_g_mux[] = {
2773 MSIOF1_SYNC_G_MARK,
2774};
2775static const unsigned int msiof1_ss1_g_pins[] = {
2776 /* SS1 */
2777 RCAR_GP_PIN(3, 10),
2778};
2779static const unsigned int msiof1_ss1_g_mux[] = {
2780 MSIOF1_SS1_G_MARK,
2781};
2782static const unsigned int msiof1_ss2_g_pins[] = {
2783 /* SS2 */
2784 RCAR_GP_PIN(3, 11),
2785};
2786static const unsigned int msiof1_ss2_g_mux[] = {
2787 MSIOF1_SS2_G_MARK,
2788};
2789static const unsigned int msiof1_txd_g_pins[] = {
2790 /* TXD */
2791 RCAR_GP_PIN(3, 9),
2792};
2793static const unsigned int msiof1_txd_g_mux[] = {
2794 MSIOF1_TXD_G_MARK,
2795};
2796static const unsigned int msiof1_rxd_g_pins[] = {
2797 /* RXD */
2798 RCAR_GP_PIN(3, 8),
2799};
2800static const unsigned int msiof1_rxd_g_mux[] = {
2801 MSIOF1_RXD_G_MARK,
2802};
2803/* - MSIOF2 ----------------------------------------------------------------- */
2804static const unsigned int msiof2_clk_a_pins[] = {
2805 /* SCK */
2806 RCAR_GP_PIN(1, 9),
2807};
2808static const unsigned int msiof2_clk_a_mux[] = {
2809 MSIOF2_SCK_A_MARK,
2810};
2811static const unsigned int msiof2_sync_a_pins[] = {
2812 /* SYNC */
2813 RCAR_GP_PIN(1, 8),
2814};
2815static const unsigned int msiof2_sync_a_mux[] = {
2816 MSIOF2_SYNC_A_MARK,
2817};
2818static const unsigned int msiof2_ss1_a_pins[] = {
2819 /* SS1 */
2820 RCAR_GP_PIN(1, 6),
2821};
2822static const unsigned int msiof2_ss1_a_mux[] = {
2823 MSIOF2_SS1_A_MARK,
2824};
2825static const unsigned int msiof2_ss2_a_pins[] = {
2826 /* SS2 */
2827 RCAR_GP_PIN(1, 7),
2828};
2829static const unsigned int msiof2_ss2_a_mux[] = {
2830 MSIOF2_SS2_A_MARK,
2831};
2832static const unsigned int msiof2_txd_a_pins[] = {
2833 /* TXD */
2834 RCAR_GP_PIN(1, 11),
2835};
2836static const unsigned int msiof2_txd_a_mux[] = {
2837 MSIOF2_TXD_A_MARK,
2838};
2839static const unsigned int msiof2_rxd_a_pins[] = {
2840 /* RXD */
2841 RCAR_GP_PIN(1, 10),
2842};
2843static const unsigned int msiof2_rxd_a_mux[] = {
2844 MSIOF2_RXD_A_MARK,
2845};
2846static const unsigned int msiof2_clk_b_pins[] = {
2847 /* SCK */
2848 RCAR_GP_PIN(0, 4),
2849};
2850static const unsigned int msiof2_clk_b_mux[] = {
2851 MSIOF2_SCK_B_MARK,
2852};
2853static const unsigned int msiof2_sync_b_pins[] = {
2854 /* SYNC */
2855 RCAR_GP_PIN(0, 5),
2856};
2857static const unsigned int msiof2_sync_b_mux[] = {
2858 MSIOF2_SYNC_B_MARK,
2859};
2860static const unsigned int msiof2_ss1_b_pins[] = {
2861 /* SS1 */
2862 RCAR_GP_PIN(0, 0),
2863};
2864static const unsigned int msiof2_ss1_b_mux[] = {
2865 MSIOF2_SS1_B_MARK,
2866};
2867static const unsigned int msiof2_ss2_b_pins[] = {
2868 /* SS2 */
2869 RCAR_GP_PIN(0, 1),
2870};
2871static const unsigned int msiof2_ss2_b_mux[] = {
2872 MSIOF2_SS2_B_MARK,
2873};
2874static const unsigned int msiof2_txd_b_pins[] = {
2875 /* TXD */
2876 RCAR_GP_PIN(0, 7),
2877};
2878static const unsigned int msiof2_txd_b_mux[] = {
2879 MSIOF2_TXD_B_MARK,
2880};
2881static const unsigned int msiof2_rxd_b_pins[] = {
2882 /* RXD */
2883 RCAR_GP_PIN(0, 6),
2884};
2885static const unsigned int msiof2_rxd_b_mux[] = {
2886 MSIOF2_RXD_B_MARK,
2887};
2888static const unsigned int msiof2_clk_c_pins[] = {
2889 /* SCK */
2890 RCAR_GP_PIN(2, 12),
2891};
2892static const unsigned int msiof2_clk_c_mux[] = {
2893 MSIOF2_SCK_C_MARK,
2894};
2895static const unsigned int msiof2_sync_c_pins[] = {
2896 /* SYNC */
2897 RCAR_GP_PIN(2, 11),
2898};
2899static const unsigned int msiof2_sync_c_mux[] = {
2900 MSIOF2_SYNC_C_MARK,
2901};
2902static const unsigned int msiof2_ss1_c_pins[] = {
2903 /* SS1 */
2904 RCAR_GP_PIN(2, 10),
2905};
2906static const unsigned int msiof2_ss1_c_mux[] = {
2907 MSIOF2_SS1_C_MARK,
2908};
2909static const unsigned int msiof2_ss2_c_pins[] = {
2910 /* SS2 */
2911 RCAR_GP_PIN(2, 9),
2912};
2913static const unsigned int msiof2_ss2_c_mux[] = {
2914 MSIOF2_SS2_C_MARK,
2915};
2916static const unsigned int msiof2_txd_c_pins[] = {
2917 /* TXD */
2918 RCAR_GP_PIN(2, 14),
2919};
2920static const unsigned int msiof2_txd_c_mux[] = {
2921 MSIOF2_TXD_C_MARK,
2922};
2923static const unsigned int msiof2_rxd_c_pins[] = {
2924 /* RXD */
2925 RCAR_GP_PIN(2, 13),
2926};
2927static const unsigned int msiof2_rxd_c_mux[] = {
2928 MSIOF2_RXD_C_MARK,
2929};
2930static const unsigned int msiof2_clk_d_pins[] = {
2931 /* SCK */
2932 RCAR_GP_PIN(0, 8),
2933};
2934static const unsigned int msiof2_clk_d_mux[] = {
2935 MSIOF2_SCK_D_MARK,
2936};
2937static const unsigned int msiof2_sync_d_pins[] = {
2938 /* SYNC */
2939 RCAR_GP_PIN(0, 9),
2940};
2941static const unsigned int msiof2_sync_d_mux[] = {
2942 MSIOF2_SYNC_D_MARK,
2943};
2944static const unsigned int msiof2_ss1_d_pins[] = {
2945 /* SS1 */
2946 RCAR_GP_PIN(0, 12),
2947};
2948static const unsigned int msiof2_ss1_d_mux[] = {
2949 MSIOF2_SS1_D_MARK,
2950};
2951static const unsigned int msiof2_ss2_d_pins[] = {
2952 /* SS2 */
2953 RCAR_GP_PIN(0, 13),
2954};
2955static const unsigned int msiof2_ss2_d_mux[] = {
2956 MSIOF2_SS2_D_MARK,
2957};
2958static const unsigned int msiof2_txd_d_pins[] = {
2959 /* TXD */
2960 RCAR_GP_PIN(0, 11),
2961};
2962static const unsigned int msiof2_txd_d_mux[] = {
2963 MSIOF2_TXD_D_MARK,
2964};
2965static const unsigned int msiof2_rxd_d_pins[] = {
2966 /* RXD */
2967 RCAR_GP_PIN(0, 10),
2968};
2969static const unsigned int msiof2_rxd_d_mux[] = {
2970 MSIOF2_RXD_D_MARK,
2971};
2972/* - MSIOF3 ----------------------------------------------------------------- */
2973static const unsigned int msiof3_clk_a_pins[] = {
2974 /* SCK */
2975 RCAR_GP_PIN(0, 0),
2976};
2977static const unsigned int msiof3_clk_a_mux[] = {
2978 MSIOF3_SCK_A_MARK,
2979};
2980static const unsigned int msiof3_sync_a_pins[] = {
2981 /* SYNC */
2982 RCAR_GP_PIN(0, 1),
2983};
2984static const unsigned int msiof3_sync_a_mux[] = {
2985 MSIOF3_SYNC_A_MARK,
2986};
2987static const unsigned int msiof3_ss1_a_pins[] = {
2988 /* SS1 */
2989 RCAR_GP_PIN(0, 14),
2990};
2991static const unsigned int msiof3_ss1_a_mux[] = {
2992 MSIOF3_SS1_A_MARK,
2993};
2994static const unsigned int msiof3_ss2_a_pins[] = {
2995 /* SS2 */
2996 RCAR_GP_PIN(0, 15),
2997};
2998static const unsigned int msiof3_ss2_a_mux[] = {
2999 MSIOF3_SS2_A_MARK,
3000};
3001static const unsigned int msiof3_txd_a_pins[] = {
3002 /* TXD */
3003 RCAR_GP_PIN(0, 3),
3004};
3005static const unsigned int msiof3_txd_a_mux[] = {
3006 MSIOF3_TXD_A_MARK,
3007};
3008static const unsigned int msiof3_rxd_a_pins[] = {
3009 /* RXD */
3010 RCAR_GP_PIN(0, 2),
3011};
3012static const unsigned int msiof3_rxd_a_mux[] = {
3013 MSIOF3_RXD_A_MARK,
3014};
3015static const unsigned int msiof3_clk_b_pins[] = {
3016 /* SCK */
3017 RCAR_GP_PIN(1, 2),
3018};
3019static const unsigned int msiof3_clk_b_mux[] = {
3020 MSIOF3_SCK_B_MARK,
3021};
3022static const unsigned int msiof3_sync_b_pins[] = {
3023 /* SYNC */
3024 RCAR_GP_PIN(1, 0),
3025};
3026static const unsigned int msiof3_sync_b_mux[] = {
3027 MSIOF3_SYNC_B_MARK,
3028};
3029static const unsigned int msiof3_ss1_b_pins[] = {
3030 /* SS1 */
3031 RCAR_GP_PIN(1, 4),
3032};
3033static const unsigned int msiof3_ss1_b_mux[] = {
3034 MSIOF3_SS1_B_MARK,
3035};
3036static const unsigned int msiof3_ss2_b_pins[] = {
3037 /* SS2 */
3038 RCAR_GP_PIN(1, 5),
3039};
3040static const unsigned int msiof3_ss2_b_mux[] = {
3041 MSIOF3_SS2_B_MARK,
3042};
3043static const unsigned int msiof3_txd_b_pins[] = {
3044 /* TXD */
3045 RCAR_GP_PIN(1, 1),
3046};
3047static const unsigned int msiof3_txd_b_mux[] = {
3048 MSIOF3_TXD_B_MARK,
3049};
3050static const unsigned int msiof3_rxd_b_pins[] = {
3051 /* RXD */
3052 RCAR_GP_PIN(1, 3),
3053};
3054static const unsigned int msiof3_rxd_b_mux[] = {
3055 MSIOF3_RXD_B_MARK,
3056};
3057static const unsigned int msiof3_clk_c_pins[] = {
3058 /* SCK */
3059 RCAR_GP_PIN(1, 12),
3060};
3061static const unsigned int msiof3_clk_c_mux[] = {
3062 MSIOF3_SCK_C_MARK,
3063};
3064static const unsigned int msiof3_sync_c_pins[] = {
3065 /* SYNC */
3066 RCAR_GP_PIN(1, 13),
3067};
3068static const unsigned int msiof3_sync_c_mux[] = {
3069 MSIOF3_SYNC_C_MARK,
3070};
3071static const unsigned int msiof3_txd_c_pins[] = {
3072 /* TXD */
3073 RCAR_GP_PIN(1, 15),
3074};
3075static const unsigned int msiof3_txd_c_mux[] = {
3076 MSIOF3_TXD_C_MARK,
3077};
3078static const unsigned int msiof3_rxd_c_pins[] = {
3079 /* RXD */
3080 RCAR_GP_PIN(1, 14),
3081};
3082static const unsigned int msiof3_rxd_c_mux[] = {
3083 MSIOF3_RXD_C_MARK,
3084};
3085static const unsigned int msiof3_clk_d_pins[] = {
3086 /* SCK */
3087 RCAR_GP_PIN(1, 22),
3088};
3089static const unsigned int msiof3_clk_d_mux[] = {
3090 MSIOF3_SCK_D_MARK,
3091};
3092static const unsigned int msiof3_sync_d_pins[] = {
3093 /* SYNC */
3094 RCAR_GP_PIN(1, 23),
3095};
3096static const unsigned int msiof3_sync_d_mux[] = {
3097 MSIOF3_SYNC_D_MARK,
3098};
3099static const unsigned int msiof3_ss1_d_pins[] = {
3100 /* SS1 */
3101 RCAR_GP_PIN(1, 26),
3102};
3103static const unsigned int msiof3_ss1_d_mux[] = {
3104 MSIOF3_SS1_D_MARK,
3105};
3106static const unsigned int msiof3_txd_d_pins[] = {
3107 /* TXD */
3108 RCAR_GP_PIN(1, 25),
3109};
3110static const unsigned int msiof3_txd_d_mux[] = {
3111 MSIOF3_TXD_D_MARK,
3112};
3113static const unsigned int msiof3_rxd_d_pins[] = {
3114 /* RXD */
3115 RCAR_GP_PIN(1, 24),
3116};
3117static const unsigned int msiof3_rxd_d_mux[] = {
3118 MSIOF3_RXD_D_MARK,
3119};
3120static const unsigned int msiof3_clk_e_pins[] = {
3121 /* SCK */
3122 RCAR_GP_PIN(2, 3),
3123};
3124static const unsigned int msiof3_clk_e_mux[] = {
3125 MSIOF3_SCK_E_MARK,
3126};
3127static const unsigned int msiof3_sync_e_pins[] = {
3128 /* SYNC */
3129 RCAR_GP_PIN(2, 2),
3130};
3131static const unsigned int msiof3_sync_e_mux[] = {
3132 MSIOF3_SYNC_E_MARK,
3133};
3134static const unsigned int msiof3_ss1_e_pins[] = {
3135 /* SS1 */
3136 RCAR_GP_PIN(2, 1),
3137};
3138static const unsigned int msiof3_ss1_e_mux[] = {
3139 MSIOF3_SS1_E_MARK,
3140};
3141static const unsigned int msiof3_ss2_e_pins[] = {
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]3142 /* SS2 */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3143 RCAR_GP_PIN(2, 0),
3144};
3145static const unsigned int msiof3_ss2_e_mux[] = {
3146 MSIOF3_SS2_E_MARK,
3147};
3148static const unsigned int msiof3_txd_e_pins[] = {
3149 /* TXD */
3150 RCAR_GP_PIN(2, 5),
3151};
3152static const unsigned int msiof3_txd_e_mux[] = {
3153 MSIOF3_TXD_E_MARK,
3154};
3155static const unsigned int msiof3_rxd_e_pins[] = {
3156 /* RXD */
3157 RCAR_GP_PIN(2, 4),
3158};
3159static const unsigned int msiof3_rxd_e_mux[] = {
3160 MSIOF3_RXD_E_MARK,
3161};
3162
3163/* - PWM0 --------------------------------------------------------------------*/
3164static const unsigned int pwm0_pins[] = {
3165 /* PWM */
3166 RCAR_GP_PIN(2, 6),
3167};
3168static const unsigned int pwm0_mux[] = {
3169 PWM0_MARK,
3170};
3171/* - PWM1 --------------------------------------------------------------------*/
3172static const unsigned int pwm1_a_pins[] = {
3173 /* PWM */
3174 RCAR_GP_PIN(2, 7),
3175};
3176static const unsigned int pwm1_a_mux[] = {
3177 PWM1_A_MARK,
3178};
3179static const unsigned int pwm1_b_pins[] = {
3180 /* PWM */
3181 RCAR_GP_PIN(1, 8),
3182};
3183static const unsigned int pwm1_b_mux[] = {
3184 PWM1_B_MARK,
3185};
3186/* - PWM2 --------------------------------------------------------------------*/
3187static const unsigned int pwm2_a_pins[] = {
3188 /* PWM */
3189 RCAR_GP_PIN(2, 8),
3190};
3191static const unsigned int pwm2_a_mux[] = {
3192 PWM2_A_MARK,
3193};
3194static const unsigned int pwm2_b_pins[] = {
3195 /* PWM */
3196 RCAR_GP_PIN(1, 11),
3197};
3198static const unsigned int pwm2_b_mux[] = {
3199 PWM2_B_MARK,
3200};
3201/* - PWM3 --------------------------------------------------------------------*/
3202static const unsigned int pwm3_a_pins[] = {
3203 /* PWM */
3204 RCAR_GP_PIN(1, 0),
3205};
3206static const unsigned int pwm3_a_mux[] = {
3207 PWM3_A_MARK,
3208};
3209static const unsigned int pwm3_b_pins[] = {
3210 /* PWM */
3211 RCAR_GP_PIN(2, 2),
3212};
3213static const unsigned int pwm3_b_mux[] = {
3214 PWM3_B_MARK,
3215};
3216/* - PWM4 --------------------------------------------------------------------*/
3217static const unsigned int pwm4_a_pins[] = {
3218 /* PWM */
3219 RCAR_GP_PIN(1, 1),
3220};
3221static const unsigned int pwm4_a_mux[] = {
3222 PWM4_A_MARK,
3223};
3224static const unsigned int pwm4_b_pins[] = {
3225 /* PWM */
3226 RCAR_GP_PIN(2, 3),
3227};
3228static const unsigned int pwm4_b_mux[] = {
3229 PWM4_B_MARK,
3230};
3231/* - PWM5 --------------------------------------------------------------------*/
3232static const unsigned int pwm5_a_pins[] = {
3233 /* PWM */
3234 RCAR_GP_PIN(1, 2),
3235};
3236static const unsigned int pwm5_a_mux[] = {
3237 PWM5_A_MARK,
3238};
3239static const unsigned int pwm5_b_pins[] = {
3240 /* PWM */
3241 RCAR_GP_PIN(2, 4),
3242};
3243static const unsigned int pwm5_b_mux[] = {
3244 PWM5_B_MARK,
3245};
3246/* - PWM6 --------------------------------------------------------------------*/
3247static const unsigned int pwm6_a_pins[] = {
3248 /* PWM */
3249 RCAR_GP_PIN(1, 3),
3250};
3251static const unsigned int pwm6_a_mux[] = {
3252 PWM6_A_MARK,
3253};
3254static const unsigned int pwm6_b_pins[] = {
3255 /* PWM */
3256 RCAR_GP_PIN(2, 5),
3257};
3258static const unsigned int pwm6_b_mux[] = {
3259 PWM6_B_MARK,
3260};
3261
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3262/* - SATA --------------------------------------------------------------------*/
3263static const unsigned int sata0_devslp_a_pins[] = {
3264 /* DEVSLP */
3265 RCAR_GP_PIN(6, 16),
3266};
3267static const unsigned int sata0_devslp_a_mux[] = {
3268 SATA_DEVSLP_A_MARK,
3269};
3270static const unsigned int sata0_devslp_b_pins[] = {
3271 /* DEVSLP */
3272 RCAR_GP_PIN(4, 6),
3273};
3274static const unsigned int sata0_devslp_b_mux[] = {
3275 SATA_DEVSLP_B_MARK,
3276};
3277
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3278/* - SCIF0 ------------------------------------------------------------------ */
3279static const unsigned int scif0_data_pins[] = {
3280 /* RX, TX */
3281 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
3282};
3283static const unsigned int scif0_data_mux[] = {
3284 RX0_MARK, TX0_MARK,
3285};
3286static const unsigned int scif0_clk_pins[] = {
3287 /* SCK */
3288 RCAR_GP_PIN(5, 0),
3289};
3290static const unsigned int scif0_clk_mux[] = {
3291 SCK0_MARK,
3292};
3293static const unsigned int scif0_ctrl_pins[] = {
3294 /* RTS, CTS */
3295 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
3296};
3297static const unsigned int scif0_ctrl_mux[] = {
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3298 RTS0_N_MARK, CTS0_N_MARK,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3299};
3300/* - SCIF1 ------------------------------------------------------------------ */
3301static const unsigned int scif1_data_a_pins[] = {
3302 /* RX, TX */
3303 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
3304};
3305static const unsigned int scif1_data_a_mux[] = {
3306 RX1_A_MARK, TX1_A_MARK,
3307};
3308static const unsigned int scif1_clk_pins[] = {
3309 /* SCK */
3310 RCAR_GP_PIN(6, 21),
3311};
3312static const unsigned int scif1_clk_mux[] = {
3313 SCK1_MARK,
3314};
3315static const unsigned int scif1_ctrl_pins[] = {
3316 /* RTS, CTS */
3317 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
3318};
3319static const unsigned int scif1_ctrl_mux[] = {
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3320 RTS1_N_MARK, CTS1_N_MARK,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3321};
3322
3323static const unsigned int scif1_data_b_pins[] = {
3324 /* RX, TX */
3325 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
3326};
3327static const unsigned int scif1_data_b_mux[] = {
3328 RX1_B_MARK, TX1_B_MARK,
3329};
3330/* - SCIF2 ------------------------------------------------------------------ */
3331static const unsigned int scif2_data_a_pins[] = {
3332 /* RX, TX */
3333 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
3334};
3335static const unsigned int scif2_data_a_mux[] = {
3336 RX2_A_MARK, TX2_A_MARK,
3337};
3338static const unsigned int scif2_clk_pins[] = {
3339 /* SCK */
3340 RCAR_GP_PIN(5, 9),
3341};
3342static const unsigned int scif2_clk_mux[] = {
3343 SCK2_MARK,
3344};
3345static const unsigned int scif2_data_b_pins[] = {
3346 /* RX, TX */
3347 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3348};
3349static const unsigned int scif2_data_b_mux[] = {
3350 RX2_B_MARK, TX2_B_MARK,
3351};
3352/* - SCIF3 ------------------------------------------------------------------ */
3353static const unsigned int scif3_data_a_pins[] = {
3354 /* RX, TX */
3355 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
3356};
3357static const unsigned int scif3_data_a_mux[] = {
3358 RX3_A_MARK, TX3_A_MARK,
3359};
3360static const unsigned int scif3_clk_pins[] = {
3361 /* SCK */
3362 RCAR_GP_PIN(1, 22),
3363};
3364static const unsigned int scif3_clk_mux[] = {
3365 SCK3_MARK,
3366};
3367static const unsigned int scif3_ctrl_pins[] = {
3368 /* RTS, CTS */
3369 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
3370};
3371static const unsigned int scif3_ctrl_mux[] = {
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3372 RTS3_N_MARK, CTS3_N_MARK,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3373};
3374static const unsigned int scif3_data_b_pins[] = {
3375 /* RX, TX */
3376 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
3377};
3378static const unsigned int scif3_data_b_mux[] = {
3379 RX3_B_MARK, TX3_B_MARK,
3380};
3381/* - SCIF4 ------------------------------------------------------------------ */
3382static const unsigned int scif4_data_a_pins[] = {
3383 /* RX, TX */
3384 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
3385};
3386static const unsigned int scif4_data_a_mux[] = {
3387 RX4_A_MARK, TX4_A_MARK,
3388};
3389static const unsigned int scif4_clk_a_pins[] = {
3390 /* SCK */
3391 RCAR_GP_PIN(2, 10),
3392};
3393static const unsigned int scif4_clk_a_mux[] = {
3394 SCK4_A_MARK,
3395};
3396static const unsigned int scif4_ctrl_a_pins[] = {
3397 /* RTS, CTS */
3398 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
3399};
3400static const unsigned int scif4_ctrl_a_mux[] = {
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3401 RTS4_N_A_MARK, CTS4_N_A_MARK,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3402};
3403static const unsigned int scif4_data_b_pins[] = {
3404 /* RX, TX */
3405 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3406};
3407static const unsigned int scif4_data_b_mux[] = {
3408 RX4_B_MARK, TX4_B_MARK,
3409};
3410static const unsigned int scif4_clk_b_pins[] = {
3411 /* SCK */
3412 RCAR_GP_PIN(1, 5),
3413};
3414static const unsigned int scif4_clk_b_mux[] = {
3415 SCK4_B_MARK,
3416};
3417static const unsigned int scif4_ctrl_b_pins[] = {
3418 /* RTS, CTS */
3419 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
3420};
3421static const unsigned int scif4_ctrl_b_mux[] = {
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3422 RTS4_N_B_MARK, CTS4_N_B_MARK,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3423};
3424static const unsigned int scif4_data_c_pins[] = {
3425 /* RX, TX */
3426 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3427};
3428static const unsigned int scif4_data_c_mux[] = {
3429 RX4_C_MARK, TX4_C_MARK,
3430};
3431static const unsigned int scif4_clk_c_pins[] = {
3432 /* SCK */
3433 RCAR_GP_PIN(0, 8),
3434};
3435static const unsigned int scif4_clk_c_mux[] = {
3436 SCK4_C_MARK,
3437};
3438static const unsigned int scif4_ctrl_c_pins[] = {
3439 /* RTS, CTS */
3440 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
3441};
3442static const unsigned int scif4_ctrl_c_mux[] = {
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3443 RTS4_N_C_MARK, CTS4_N_C_MARK,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3444};
3445/* - SCIF5 ------------------------------------------------------------------ */
3446static const unsigned int scif5_data_a_pins[] = {
3447 /* RX, TX */
3448 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3449};
3450static const unsigned int scif5_data_a_mux[] = {
3451 RX5_A_MARK, TX5_A_MARK,
3452};
3453static const unsigned int scif5_clk_a_pins[] = {
3454 /* SCK */
3455 RCAR_GP_PIN(6, 21),
3456};
3457static const unsigned int scif5_clk_a_mux[] = {
3458 SCK5_A_MARK,
3459};
3460static const unsigned int scif5_data_b_pins[] = {
3461 /* RX, TX */
3462 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18),
3463};
3464static const unsigned int scif5_data_b_mux[] = {
3465 RX5_B_MARK, TX5_B_MARK,
3466};
3467static const unsigned int scif5_clk_b_pins[] = {
3468 /* SCK */
3469 RCAR_GP_PIN(5, 0),
3470};
3471static const unsigned int scif5_clk_b_mux[] = {
3472 SCK5_B_MARK,
3473};
3474
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3475/* - SCIF Clock ------------------------------------------------------------- */
3476static const unsigned int scif_clk_a_pins[] = {
3477 /* SCIF_CLK */
3478 RCAR_GP_PIN(6, 23),
3479};
3480static const unsigned int scif_clk_a_mux[] = {
3481 SCIF_CLK_A_MARK,
3482};
3483static const unsigned int scif_clk_b_pins[] = {
3484 /* SCIF_CLK */
3485 RCAR_GP_PIN(5, 9),
3486};
3487static const unsigned int scif_clk_b_mux[] = {
3488 SCIF_CLK_B_MARK,
3489};
3490
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3491/* - SDHI0 ------------------------------------------------------------------ */
3492static const unsigned int sdhi0_data1_pins[] = {
3493 /* D0 */
3494 RCAR_GP_PIN(3, 2),
3495};
3496static const unsigned int sdhi0_data1_mux[] = {
3497 SD0_DAT0_MARK,
3498};
3499static const unsigned int sdhi0_data4_pins[] = {
3500 /* D[0:3] */
3501 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3502 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3503};
3504static const unsigned int sdhi0_data4_mux[] = {
3505 SD0_DAT0_MARK, SD0_DAT1_MARK,
3506 SD0_DAT2_MARK, SD0_DAT3_MARK,
3507};
3508static const unsigned int sdhi0_ctrl_pins[] = {
3509 /* CLK, CMD */
3510 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3511};
3512static const unsigned int sdhi0_ctrl_mux[] = {
3513 SD0_CLK_MARK, SD0_CMD_MARK,
3514};
3515static const unsigned int sdhi0_cd_pins[] = {
3516 /* CD */
3517 RCAR_GP_PIN(3, 12),
3518};
3519static const unsigned int sdhi0_cd_mux[] = {
3520 SD0_CD_MARK,
3521};
3522static const unsigned int sdhi0_wp_pins[] = {
3523 /* WP */
3524 RCAR_GP_PIN(3, 13),
3525};
3526static const unsigned int sdhi0_wp_mux[] = {
3527 SD0_WP_MARK,
3528};
3529/* - SDHI1 ------------------------------------------------------------------ */
3530static const unsigned int sdhi1_data1_pins[] = {
3531 /* D0 */
3532 RCAR_GP_PIN(3, 8),
3533};
3534static const unsigned int sdhi1_data1_mux[] = {
3535 SD1_DAT0_MARK,
3536};
3537static const unsigned int sdhi1_data4_pins[] = {
3538 /* D[0:3] */
3539 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3540 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3541};
3542static const unsigned int sdhi1_data4_mux[] = {
3543 SD1_DAT0_MARK, SD1_DAT1_MARK,
3544 SD1_DAT2_MARK, SD1_DAT3_MARK,
3545};
3546static const unsigned int sdhi1_ctrl_pins[] = {
3547 /* CLK, CMD */
3548 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
3549};
3550static const unsigned int sdhi1_ctrl_mux[] = {
3551 SD1_CLK_MARK, SD1_CMD_MARK,
3552};
3553static const unsigned int sdhi1_cd_pins[] = {
3554 /* CD */
3555 RCAR_GP_PIN(3, 14),
3556};
3557static const unsigned int sdhi1_cd_mux[] = {
3558 SD1_CD_MARK,
3559};
3560static const unsigned int sdhi1_wp_pins[] = {
3561 /* WP */
3562 RCAR_GP_PIN(3, 15),
3563};
3564static const unsigned int sdhi1_wp_mux[] = {
3565 SD1_WP_MARK,
3566};
3567/* - SDHI2 ------------------------------------------------------------------ */
3568static const unsigned int sdhi2_data1_pins[] = {
3569 /* D0 */
3570 RCAR_GP_PIN(4, 2),
3571};
3572static const unsigned int sdhi2_data1_mux[] = {
3573 SD2_DAT0_MARK,
3574};
3575static const unsigned int sdhi2_data4_pins[] = {
3576 /* D[0:3] */
3577 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3578 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3579};
3580static const unsigned int sdhi2_data4_mux[] = {
3581 SD2_DAT0_MARK, SD2_DAT1_MARK,
3582 SD2_DAT2_MARK, SD2_DAT3_MARK,
3583};
3584static const unsigned int sdhi2_data8_pins[] = {
3585 /* D[0:7] */
3586 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3587 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3588 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3589 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3590};
3591static const unsigned int sdhi2_data8_mux[] = {
3592 SD2_DAT0_MARK, SD2_DAT1_MARK,
3593 SD2_DAT2_MARK, SD2_DAT3_MARK,
3594 SD2_DAT4_MARK, SD2_DAT5_MARK,
3595 SD2_DAT6_MARK, SD2_DAT7_MARK,
3596};
3597static const unsigned int sdhi2_ctrl_pins[] = {
3598 /* CLK, CMD */
3599 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
3600};
3601static const unsigned int sdhi2_ctrl_mux[] = {
3602 SD2_CLK_MARK, SD2_CMD_MARK,
3603};
3604static const unsigned int sdhi2_cd_a_pins[] = {
3605 /* CD */
3606 RCAR_GP_PIN(4, 13),
3607};
3608static const unsigned int sdhi2_cd_a_mux[] = {
3609 SD2_CD_A_MARK,
3610};
3611static const unsigned int sdhi2_cd_b_pins[] = {
3612 /* CD */
3613 RCAR_GP_PIN(5, 10),
3614};
3615static const unsigned int sdhi2_cd_b_mux[] = {
3616 SD2_CD_B_MARK,
3617};
3618static const unsigned int sdhi2_wp_a_pins[] = {
3619 /* WP */
3620 RCAR_GP_PIN(4, 14),
3621};
3622static const unsigned int sdhi2_wp_a_mux[] = {
3623 SD2_WP_A_MARK,
3624};
3625static const unsigned int sdhi2_wp_b_pins[] = {
3626 /* WP */
3627 RCAR_GP_PIN(5, 11),
3628};
3629static const unsigned int sdhi2_wp_b_mux[] = {
3630 SD2_WP_B_MARK,
3631};
3632static const unsigned int sdhi2_ds_pins[] = {
3633 /* DS */
3634 RCAR_GP_PIN(4, 6),
3635};
3636static const unsigned int sdhi2_ds_mux[] = {
3637 SD2_DS_MARK,
3638};
3639/* - SDHI3 ------------------------------------------------------------------ */
3640static const unsigned int sdhi3_data1_pins[] = {
3641 /* D0 */
3642 RCAR_GP_PIN(4, 9),
3643};
3644static const unsigned int sdhi3_data1_mux[] = {
3645 SD3_DAT0_MARK,
3646};
3647static const unsigned int sdhi3_data4_pins[] = {
3648 /* D[0:3] */
3649 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3650 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3651};
3652static const unsigned int sdhi3_data4_mux[] = {
3653 SD3_DAT0_MARK, SD3_DAT1_MARK,
3654 SD3_DAT2_MARK, SD3_DAT3_MARK,
3655};
3656static const unsigned int sdhi3_data8_pins[] = {
3657 /* D[0:7] */
3658 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3659 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3660 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
3661 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
3662};
3663static const unsigned int sdhi3_data8_mux[] = {
3664 SD3_DAT0_MARK, SD3_DAT1_MARK,
3665 SD3_DAT2_MARK, SD3_DAT3_MARK,
3666 SD3_DAT4_MARK, SD3_DAT5_MARK,
3667 SD3_DAT6_MARK, SD3_DAT7_MARK,
3668};
3669static const unsigned int sdhi3_ctrl_pins[] = {
3670 /* CLK, CMD */
3671 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
3672};
3673static const unsigned int sdhi3_ctrl_mux[] = {
3674 SD3_CLK_MARK, SD3_CMD_MARK,
3675};
3676static const unsigned int sdhi3_cd_pins[] = {
3677 /* CD */
3678 RCAR_GP_PIN(4, 15),
3679};
3680static const unsigned int sdhi3_cd_mux[] = {
3681 SD3_CD_MARK,
3682};
3683static const unsigned int sdhi3_wp_pins[] = {
3684 /* WP */
3685 RCAR_GP_PIN(4, 16),
3686};
3687static const unsigned int sdhi3_wp_mux[] = {
3688 SD3_WP_MARK,
3689};
3690static const unsigned int sdhi3_ds_pins[] = {
3691 /* DS */
3692 RCAR_GP_PIN(4, 17),
3693};
3694static const unsigned int sdhi3_ds_mux[] = {
3695 SD3_DS_MARK,
3696};
3697
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3698/* - SSI -------------------------------------------------------------------- */
3699static const unsigned int ssi0_data_pins[] = {
3700 /* SDATA */
3701 RCAR_GP_PIN(6, 2),
3702};
3703static const unsigned int ssi0_data_mux[] = {
3704 SSI_SDATA0_MARK,
3705};
3706static const unsigned int ssi01239_ctrl_pins[] = {
3707 /* SCK, WS */
3708 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3709};
3710static const unsigned int ssi01239_ctrl_mux[] = {
3711 SSI_SCK01239_MARK, SSI_WS01239_MARK,
3712};
3713static const unsigned int ssi1_data_a_pins[] = {
3714 /* SDATA */
3715 RCAR_GP_PIN(6, 3),
3716};
3717static const unsigned int ssi1_data_a_mux[] = {
3718 SSI_SDATA1_A_MARK,
3719};
3720static const unsigned int ssi1_data_b_pins[] = {
3721 /* SDATA */
3722 RCAR_GP_PIN(5, 12),
3723};
3724static const unsigned int ssi1_data_b_mux[] = {
3725 SSI_SDATA1_B_MARK,
3726};
3727static const unsigned int ssi1_ctrl_a_pins[] = {
3728 /* SCK, WS */
3729 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3730};
3731static const unsigned int ssi1_ctrl_a_mux[] = {
3732 SSI_SCK1_A_MARK, SSI_WS1_A_MARK,
3733};
3734static const unsigned int ssi1_ctrl_b_pins[] = {
3735 /* SCK, WS */
3736 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21),
3737};
3738static const unsigned int ssi1_ctrl_b_mux[] = {
3739 SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
3740};
3741static const unsigned int ssi2_data_a_pins[] = {
3742 /* SDATA */
3743 RCAR_GP_PIN(6, 4),
3744};
3745static const unsigned int ssi2_data_a_mux[] = {
3746 SSI_SDATA2_A_MARK,
3747};
3748static const unsigned int ssi2_data_b_pins[] = {
3749 /* SDATA */
3750 RCAR_GP_PIN(5, 13),
3751};
3752static const unsigned int ssi2_data_b_mux[] = {
3753 SSI_SDATA2_B_MARK,
3754};
3755static const unsigned int ssi2_ctrl_a_pins[] = {
3756 /* SCK, WS */
3757 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3758};
3759static const unsigned int ssi2_ctrl_a_mux[] = {
3760 SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
3761};
3762static const unsigned int ssi2_ctrl_b_pins[] = {
3763 /* SCK, WS */
3764 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3765};
3766static const unsigned int ssi2_ctrl_b_mux[] = {
3767 SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
3768};
3769static const unsigned int ssi3_data_pins[] = {
3770 /* SDATA */
3771 RCAR_GP_PIN(6, 7),
3772};
3773static const unsigned int ssi3_data_mux[] = {
3774 SSI_SDATA3_MARK,
3775};
3776static const unsigned int ssi349_ctrl_pins[] = {
3777 /* SCK, WS */
3778 RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
3779};
3780static const unsigned int ssi349_ctrl_mux[] = {
3781 SSI_SCK349_MARK, SSI_WS349_MARK,
3782};
3783static const unsigned int ssi4_data_pins[] = {
3784 /* SDATA */
3785 RCAR_GP_PIN(6, 10),
3786};
3787static const unsigned int ssi4_data_mux[] = {
3788 SSI_SDATA4_MARK,
3789};
3790static const unsigned int ssi4_ctrl_pins[] = {
3791 /* SCK, WS */
3792 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
3793};
3794static const unsigned int ssi4_ctrl_mux[] = {
3795 SSI_SCK4_MARK, SSI_WS4_MARK,
3796};
3797static const unsigned int ssi5_data_pins[] = {
3798 /* SDATA */
3799 RCAR_GP_PIN(6, 13),
3800};
3801static const unsigned int ssi5_data_mux[] = {
3802 SSI_SDATA5_MARK,
3803};
3804static const unsigned int ssi5_ctrl_pins[] = {
3805 /* SCK, WS */
3806 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
3807};
3808static const unsigned int ssi5_ctrl_mux[] = {
3809 SSI_SCK5_MARK, SSI_WS5_MARK,
3810};
3811static const unsigned int ssi6_data_pins[] = {
3812 /* SDATA */
3813 RCAR_GP_PIN(6, 16),
3814};
3815static const unsigned int ssi6_data_mux[] = {
3816 SSI_SDATA6_MARK,
3817};
3818static const unsigned int ssi6_ctrl_pins[] = {
3819 /* SCK, WS */
3820 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3821};
3822static const unsigned int ssi6_ctrl_mux[] = {
3823 SSI_SCK6_MARK, SSI_WS6_MARK,
3824};
3825static const unsigned int ssi7_data_pins[] = {
3826 /* SDATA */
3827 RCAR_GP_PIN(6, 19),
3828};
3829static const unsigned int ssi7_data_mux[] = {
3830 SSI_SDATA7_MARK,
3831};
3832static const unsigned int ssi78_ctrl_pins[] = {
3833 /* SCK, WS */
3834 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
3835};
3836static const unsigned int ssi78_ctrl_mux[] = {
3837 SSI_SCK78_MARK, SSI_WS78_MARK,
3838};
3839static const unsigned int ssi8_data_pins[] = {
3840 /* SDATA */
3841 RCAR_GP_PIN(6, 20),
3842};
3843static const unsigned int ssi8_data_mux[] = {
3844 SSI_SDATA8_MARK,
3845};
3846static const unsigned int ssi9_data_a_pins[] = {
3847 /* SDATA */
3848 RCAR_GP_PIN(6, 21),
3849};
3850static const unsigned int ssi9_data_a_mux[] = {
3851 SSI_SDATA9_A_MARK,
3852};
3853static const unsigned int ssi9_data_b_pins[] = {
3854 /* SDATA */
3855 RCAR_GP_PIN(5, 14),
3856};
3857static const unsigned int ssi9_data_b_mux[] = {
3858 SSI_SDATA9_B_MARK,
3859};
3860static const unsigned int ssi9_ctrl_a_pins[] = {
3861 /* SCK, WS */
3862 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3863};
3864static const unsigned int ssi9_ctrl_a_mux[] = {
3865 SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
3866};
3867static const unsigned int ssi9_ctrl_b_pins[] = {
3868 /* SCK, WS */
3869 RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
3870};
3871static const unsigned int ssi9_ctrl_b_mux[] = {
3872 SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
3873};
3874
3875/* - TMU -------------------------------------------------------------------- */
3876static const unsigned int tmu_tclk1_a_pins[] = {
3877 /* TCLK */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3878 RCAR_GP_PIN(6, 23),
3879};
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3880static const unsigned int tmu_tclk1_a_mux[] = {
3881 TCLK1_A_MARK,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3882};
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3883static const unsigned int tmu_tclk1_b_pins[] = {
3884 /* TCLK */
3885 RCAR_GP_PIN(5, 19),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3886};
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3887static const unsigned int tmu_tclk1_b_mux[] = {
3888 TCLK1_B_MARK,
3889};
3890static const unsigned int tmu_tclk2_a_pins[] = {
3891 /* TCLK */
3892 RCAR_GP_PIN(6, 19),
3893};
3894static const unsigned int tmu_tclk2_a_mux[] = {
3895 TCLK2_A_MARK,
3896};
3897static const unsigned int tmu_tclk2_b_pins[] = {
3898 /* TCLK */
3899 RCAR_GP_PIN(6, 28),
3900};
3901static const unsigned int tmu_tclk2_b_mux[] = {
3902 TCLK2_B_MARK,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3903};
3904
3905/* - USB0 ------------------------------------------------------------------- */
3906static const unsigned int usb0_pins[] = {
3907 /* PWEN, OVC */
3908 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
3909};
3910static const unsigned int usb0_mux[] = {
3911 USB0_PWEN_MARK, USB0_OVC_MARK,
3912};
3913/* - USB1 ------------------------------------------------------------------- */
3914static const unsigned int usb1_pins[] = {
3915 /* PWEN, OVC */
3916 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3917};
3918static const unsigned int usb1_mux[] = {
3919 USB1_PWEN_MARK, USB1_OVC_MARK,
3920};
3921/* - USB2 ------------------------------------------------------------------- */
3922static const unsigned int usb2_pins[] = {
3923 /* PWEN, OVC */
3924 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3925};
3926static const unsigned int usb2_mux[] = {
3927 USB2_PWEN_MARK, USB2_OVC_MARK,
3928};
3929/* - USB2_CH3 --------------------------------------------------------------- */
3930static const unsigned int usb2_ch3_pins[] = {
3931 /* PWEN, OVC */
3932 RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
3933};
3934static const unsigned int usb2_ch3_mux[] = {
3935 USB2_CH3_PWEN_MARK, USB2_CH3_OVC_MARK,
3936};
3937
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3938/* - USB30 ------------------------------------------------------------------ */
3939static const unsigned int usb30_pins[] = {
3940 /* PWEN, OVC */
3941 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3942};
3943static const unsigned int usb30_mux[] = {
3944 USB30_PWEN_MARK, USB30_OVC_MARK,
3945};
3946
3947/* - VIN4 ------------------------------------------------------------------- */
3948static const unsigned int vin4_data18_a_pins[] = {
3949 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3950 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3951 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3952 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3953 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3954 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3955 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3956 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3957 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3958};
3959static const unsigned int vin4_data18_a_mux[] = {
3960 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
3961 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
3962 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
3963 VI4_DATA10_MARK, VI4_DATA11_MARK,
3964 VI4_DATA12_MARK, VI4_DATA13_MARK,
3965 VI4_DATA14_MARK, VI4_DATA15_MARK,
3966 VI4_DATA18_MARK, VI4_DATA19_MARK,
3967 VI4_DATA20_MARK, VI4_DATA21_MARK,
3968 VI4_DATA22_MARK, VI4_DATA23_MARK,
3969};
3970static const unsigned int vin4_data18_b_pins[] = {
3971 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
3972 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
3973 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
3974 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3975 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3976 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3977 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3978 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3979 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3980};
3981static const unsigned int vin4_data18_b_mux[] = {
3982 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
3983 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
3984 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
3985 VI4_DATA10_MARK, VI4_DATA11_MARK,
3986 VI4_DATA12_MARK, VI4_DATA13_MARK,
3987 VI4_DATA14_MARK, VI4_DATA15_MARK,
3988 VI4_DATA18_MARK, VI4_DATA19_MARK,
3989 VI4_DATA20_MARK, VI4_DATA21_MARK,
3990 VI4_DATA22_MARK, VI4_DATA23_MARK,
3991};
3992static const union vin_data vin4_data_a_pins = {
3993 .data24 = {
3994 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
3995 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3996 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3997 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3998 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
3999 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4000 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4001 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4002 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4003 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4004 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4005 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4006 },
4007};
4008static const union vin_data vin4_data_a_mux = {
4009 .data24 = {
4010 VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
4011 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
4012 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
4013 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
4014 VI4_DATA8_MARK, VI4_DATA9_MARK,
4015 VI4_DATA10_MARK, VI4_DATA11_MARK,
4016 VI4_DATA12_MARK, VI4_DATA13_MARK,
4017 VI4_DATA14_MARK, VI4_DATA15_MARK,
4018 VI4_DATA16_MARK, VI4_DATA17_MARK,
4019 VI4_DATA18_MARK, VI4_DATA19_MARK,
4020 VI4_DATA20_MARK, VI4_DATA21_MARK,
4021 VI4_DATA22_MARK, VI4_DATA23_MARK,
4022 },
4023};
4024static const union vin_data vin4_data_b_pins = {
4025 .data24 = {
4026 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
4027 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
4028 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
4029 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
4030 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
4031 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4032 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4033 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4034 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4035 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4036 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4037 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4038 },
4039};
4040static const union vin_data vin4_data_b_mux = {
4041 .data24 = {
4042 VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
4043 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
4044 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
4045 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
4046 VI4_DATA8_MARK, VI4_DATA9_MARK,
4047 VI4_DATA10_MARK, VI4_DATA11_MARK,
4048 VI4_DATA12_MARK, VI4_DATA13_MARK,
4049 VI4_DATA14_MARK, VI4_DATA15_MARK,
4050 VI4_DATA16_MARK, VI4_DATA17_MARK,
4051 VI4_DATA18_MARK, VI4_DATA19_MARK,
4052 VI4_DATA20_MARK, VI4_DATA21_MARK,
4053 VI4_DATA22_MARK, VI4_DATA23_MARK,
4054 },
4055};
4056static const unsigned int vin4_sync_pins[] = {
4057 /* HSYNC#, VSYNC# */
4058 RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 17),
4059};
4060static const unsigned int vin4_sync_mux[] = {
4061 VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
4062};
4063static const unsigned int vin4_field_pins[] = {
4064 /* FIELD */
4065 RCAR_GP_PIN(1, 16),
4066};
4067static const unsigned int vin4_field_mux[] = {
4068 VI4_FIELD_MARK,
4069};
4070static const unsigned int vin4_clkenb_pins[] = {
4071 /* CLKENB */
4072 RCAR_GP_PIN(1, 19),
4073};
4074static const unsigned int vin4_clkenb_mux[] = {
4075 VI4_CLKENB_MARK,
4076};
4077static const unsigned int vin4_clk_pins[] = {
4078 /* CLK */
4079 RCAR_GP_PIN(1, 27),
4080};
4081static const unsigned int vin4_clk_mux[] = {
4082 VI4_CLK_MARK,
4083};
4084
4085/* - VIN5 ------------------------------------------------------------------- */
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]4086static const union vin_data16 vin5_data_pins = {
4087 .data16 = {
4088 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4089 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4090 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4091 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4092 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
4093 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
4094 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4095 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4096 },
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4097};
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]4098static const union vin_data16 vin5_data_mux = {
4099 .data16 = {
4100 VI5_DATA0_MARK, VI5_DATA1_MARK,
4101 VI5_DATA2_MARK, VI5_DATA3_MARK,
4102 VI5_DATA4_MARK, VI5_DATA5_MARK,
4103 VI5_DATA6_MARK, VI5_DATA7_MARK,
4104 VI5_DATA8_MARK, VI5_DATA9_MARK,
4105 VI5_DATA10_MARK, VI5_DATA11_MARK,
4106 VI5_DATA12_MARK, VI5_DATA13_MARK,
4107 VI5_DATA14_MARK, VI5_DATA15_MARK,
4108 },
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4109};
4110static const unsigned int vin5_sync_pins[] = {
4111 /* HSYNC#, VSYNC# */
4112 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
4113};
4114static const unsigned int vin5_sync_mux[] = {
4115 VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK,
4116};
4117static const unsigned int vin5_field_pins[] = {
4118 RCAR_GP_PIN(1, 11),
4119};
4120static const unsigned int vin5_field_mux[] = {
4121 /* FIELD */
4122 VI5_FIELD_MARK,
4123};
4124static const unsigned int vin5_clkenb_pins[] = {
4125 RCAR_GP_PIN(1, 20),
4126};
4127static const unsigned int vin5_clkenb_mux[] = {
4128 /* CLKENB */
4129 VI5_CLKENB_MARK,
4130};
4131static const unsigned int vin5_clk_pins[] = {
4132 RCAR_GP_PIN(1, 21),
4133};
4134static const unsigned int vin5_clk_mux[] = {
4135 /* CLK */
4136 VI5_CLK_MARK,
4137};
4138
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4139static const struct sh_pfc_pin_group pinmux_groups[] = {
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4140 SH_PFC_PIN_GROUP(audio_clk_a_a),
4141 SH_PFC_PIN_GROUP(audio_clk_a_b),
4142 SH_PFC_PIN_GROUP(audio_clk_a_c),
4143 SH_PFC_PIN_GROUP(audio_clk_b_a),
4144 SH_PFC_PIN_GROUP(audio_clk_b_b),
4145 SH_PFC_PIN_GROUP(audio_clk_c_a),
4146 SH_PFC_PIN_GROUP(audio_clk_c_b),
4147 SH_PFC_PIN_GROUP(audio_clkout_a),
4148 SH_PFC_PIN_GROUP(audio_clkout_b),
4149 SH_PFC_PIN_GROUP(audio_clkout_c),
4150 SH_PFC_PIN_GROUP(audio_clkout_d),
4151 SH_PFC_PIN_GROUP(audio_clkout1_a),
4152 SH_PFC_PIN_GROUP(audio_clkout1_b),
4153 SH_PFC_PIN_GROUP(audio_clkout2_a),
4154 SH_PFC_PIN_GROUP(audio_clkout2_b),
4155 SH_PFC_PIN_GROUP(audio_clkout3_a),
4156 SH_PFC_PIN_GROUP(audio_clkout3_b),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4157 SH_PFC_PIN_GROUP(avb_link),
4158 SH_PFC_PIN_GROUP(avb_magic),
4159 SH_PFC_PIN_GROUP(avb_phy_int),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4160 SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio), /* Deprecated */
4161 SH_PFC_PIN_GROUP(avb_mdio),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4162 SH_PFC_PIN_GROUP(avb_mii),
4163 SH_PFC_PIN_GROUP(avb_avtp_pps),
4164 SH_PFC_PIN_GROUP(avb_avtp_match_a),
4165 SH_PFC_PIN_GROUP(avb_avtp_capture_a),
4166 SH_PFC_PIN_GROUP(avb_avtp_match_b),
4167 SH_PFC_PIN_GROUP(avb_avtp_capture_b),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4168 SH_PFC_PIN_GROUP(can0_data_a),
4169 SH_PFC_PIN_GROUP(can0_data_b),
4170 SH_PFC_PIN_GROUP(can1_data),
4171 SH_PFC_PIN_GROUP(can_clk),
4172 SH_PFC_PIN_GROUP(canfd0_data_a),
4173 SH_PFC_PIN_GROUP(canfd0_data_b),
4174 SH_PFC_PIN_GROUP(canfd1_data),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4175 SH_PFC_PIN_GROUP(drif0_ctrl_a),
4176 SH_PFC_PIN_GROUP(drif0_data0_a),
4177 SH_PFC_PIN_GROUP(drif0_data1_a),
4178 SH_PFC_PIN_GROUP(drif0_ctrl_b),
4179 SH_PFC_PIN_GROUP(drif0_data0_b),
4180 SH_PFC_PIN_GROUP(drif0_data1_b),
4181 SH_PFC_PIN_GROUP(drif0_ctrl_c),
4182 SH_PFC_PIN_GROUP(drif0_data0_c),
4183 SH_PFC_PIN_GROUP(drif0_data1_c),
4184 SH_PFC_PIN_GROUP(drif1_ctrl_a),
4185 SH_PFC_PIN_GROUP(drif1_data0_a),
4186 SH_PFC_PIN_GROUP(drif1_data1_a),
4187 SH_PFC_PIN_GROUP(drif1_ctrl_b),
4188 SH_PFC_PIN_GROUP(drif1_data0_b),
4189 SH_PFC_PIN_GROUP(drif1_data1_b),
4190 SH_PFC_PIN_GROUP(drif1_ctrl_c),
4191 SH_PFC_PIN_GROUP(drif1_data0_c),
4192 SH_PFC_PIN_GROUP(drif1_data1_c),
4193 SH_PFC_PIN_GROUP(drif2_ctrl_a),
4194 SH_PFC_PIN_GROUP(drif2_data0_a),
4195 SH_PFC_PIN_GROUP(drif2_data1_a),
4196 SH_PFC_PIN_GROUP(drif2_ctrl_b),
4197 SH_PFC_PIN_GROUP(drif2_data0_b),
4198 SH_PFC_PIN_GROUP(drif2_data1_b),
4199 SH_PFC_PIN_GROUP(drif3_ctrl_a),
4200 SH_PFC_PIN_GROUP(drif3_data0_a),
4201 SH_PFC_PIN_GROUP(drif3_data1_a),
4202 SH_PFC_PIN_GROUP(drif3_ctrl_b),
4203 SH_PFC_PIN_GROUP(drif3_data0_b),
4204 SH_PFC_PIN_GROUP(drif3_data1_b),
4205 SH_PFC_PIN_GROUP(du_rgb666),
4206 SH_PFC_PIN_GROUP(du_rgb888),
4207 SH_PFC_PIN_GROUP(du_clk_out_0),
4208 SH_PFC_PIN_GROUP(du_clk_out_1),
4209 SH_PFC_PIN_GROUP(du_sync),
4210 SH_PFC_PIN_GROUP(du_oddf),
4211 SH_PFC_PIN_GROUP(du_cde),
4212 SH_PFC_PIN_GROUP(du_disp),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4213 SH_PFC_PIN_GROUP(hscif0_data),
4214 SH_PFC_PIN_GROUP(hscif0_clk),
4215 SH_PFC_PIN_GROUP(hscif0_ctrl),
4216 SH_PFC_PIN_GROUP(hscif1_data_a),
4217 SH_PFC_PIN_GROUP(hscif1_clk_a),
4218 SH_PFC_PIN_GROUP(hscif1_ctrl_a),
4219 SH_PFC_PIN_GROUP(hscif1_data_b),
4220 SH_PFC_PIN_GROUP(hscif1_clk_b),
4221 SH_PFC_PIN_GROUP(hscif1_ctrl_b),
4222 SH_PFC_PIN_GROUP(hscif2_data_a),
4223 SH_PFC_PIN_GROUP(hscif2_clk_a),
4224 SH_PFC_PIN_GROUP(hscif2_ctrl_a),
4225 SH_PFC_PIN_GROUP(hscif2_data_b),
4226 SH_PFC_PIN_GROUP(hscif2_clk_b),
4227 SH_PFC_PIN_GROUP(hscif2_ctrl_b),
4228 SH_PFC_PIN_GROUP(hscif2_data_c),
4229 SH_PFC_PIN_GROUP(hscif2_clk_c),
4230 SH_PFC_PIN_GROUP(hscif2_ctrl_c),
4231 SH_PFC_PIN_GROUP(hscif3_data_a),
4232 SH_PFC_PIN_GROUP(hscif3_clk),
4233 SH_PFC_PIN_GROUP(hscif3_ctrl),
4234 SH_PFC_PIN_GROUP(hscif3_data_b),
4235 SH_PFC_PIN_GROUP(hscif3_data_c),
4236 SH_PFC_PIN_GROUP(hscif3_data_d),
4237 SH_PFC_PIN_GROUP(hscif4_data_a),
4238 SH_PFC_PIN_GROUP(hscif4_clk),
4239 SH_PFC_PIN_GROUP(hscif4_ctrl),
4240 SH_PFC_PIN_GROUP(hscif4_data_b),
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]4241 SH_PFC_PIN_GROUP(i2c0),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4242 SH_PFC_PIN_GROUP(i2c1_a),
4243 SH_PFC_PIN_GROUP(i2c1_b),
4244 SH_PFC_PIN_GROUP(i2c2_a),
4245 SH_PFC_PIN_GROUP(i2c2_b),
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]4246 SH_PFC_PIN_GROUP(i2c3),
4247 SH_PFC_PIN_GROUP(i2c5),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4248 SH_PFC_PIN_GROUP(i2c6_a),
4249 SH_PFC_PIN_GROUP(i2c6_b),
4250 SH_PFC_PIN_GROUP(i2c6_c),
4251 SH_PFC_PIN_GROUP(intc_ex_irq0),
4252 SH_PFC_PIN_GROUP(intc_ex_irq1),
4253 SH_PFC_PIN_GROUP(intc_ex_irq2),
4254 SH_PFC_PIN_GROUP(intc_ex_irq3),
4255 SH_PFC_PIN_GROUP(intc_ex_irq4),
4256 SH_PFC_PIN_GROUP(intc_ex_irq5),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4257 SH_PFC_PIN_GROUP(msiof0_clk),
4258 SH_PFC_PIN_GROUP(msiof0_sync),
4259 SH_PFC_PIN_GROUP(msiof0_ss1),
4260 SH_PFC_PIN_GROUP(msiof0_ss2),
4261 SH_PFC_PIN_GROUP(msiof0_txd),
4262 SH_PFC_PIN_GROUP(msiof0_rxd),
4263 SH_PFC_PIN_GROUP(msiof1_clk_a),
4264 SH_PFC_PIN_GROUP(msiof1_sync_a),
4265 SH_PFC_PIN_GROUP(msiof1_ss1_a),
4266 SH_PFC_PIN_GROUP(msiof1_ss2_a),
4267 SH_PFC_PIN_GROUP(msiof1_txd_a),
4268 SH_PFC_PIN_GROUP(msiof1_rxd_a),
4269 SH_PFC_PIN_GROUP(msiof1_clk_b),
4270 SH_PFC_PIN_GROUP(msiof1_sync_b),
4271 SH_PFC_PIN_GROUP(msiof1_ss1_b),
4272 SH_PFC_PIN_GROUP(msiof1_ss2_b),
4273 SH_PFC_PIN_GROUP(msiof1_txd_b),
4274 SH_PFC_PIN_GROUP(msiof1_rxd_b),
4275 SH_PFC_PIN_GROUP(msiof1_clk_c),
4276 SH_PFC_PIN_GROUP(msiof1_sync_c),
4277 SH_PFC_PIN_GROUP(msiof1_ss1_c),
4278 SH_PFC_PIN_GROUP(msiof1_ss2_c),
4279 SH_PFC_PIN_GROUP(msiof1_txd_c),
4280 SH_PFC_PIN_GROUP(msiof1_rxd_c),
4281 SH_PFC_PIN_GROUP(msiof1_clk_d),
4282 SH_PFC_PIN_GROUP(msiof1_sync_d),
4283 SH_PFC_PIN_GROUP(msiof1_ss1_d),
4284 SH_PFC_PIN_GROUP(msiof1_ss2_d),
4285 SH_PFC_PIN_GROUP(msiof1_txd_d),
4286 SH_PFC_PIN_GROUP(msiof1_rxd_d),
4287 SH_PFC_PIN_GROUP(msiof1_clk_e),
4288 SH_PFC_PIN_GROUP(msiof1_sync_e),
4289 SH_PFC_PIN_GROUP(msiof1_ss1_e),
4290 SH_PFC_PIN_GROUP(msiof1_ss2_e),
4291 SH_PFC_PIN_GROUP(msiof1_txd_e),
4292 SH_PFC_PIN_GROUP(msiof1_rxd_e),
4293 SH_PFC_PIN_GROUP(msiof1_clk_f),
4294 SH_PFC_PIN_GROUP(msiof1_sync_f),
4295 SH_PFC_PIN_GROUP(msiof1_ss1_f),
4296 SH_PFC_PIN_GROUP(msiof1_ss2_f),
4297 SH_PFC_PIN_GROUP(msiof1_txd_f),
4298 SH_PFC_PIN_GROUP(msiof1_rxd_f),
4299 SH_PFC_PIN_GROUP(msiof1_clk_g),
4300 SH_PFC_PIN_GROUP(msiof1_sync_g),
4301 SH_PFC_PIN_GROUP(msiof1_ss1_g),
4302 SH_PFC_PIN_GROUP(msiof1_ss2_g),
4303 SH_PFC_PIN_GROUP(msiof1_txd_g),
4304 SH_PFC_PIN_GROUP(msiof1_rxd_g),
4305 SH_PFC_PIN_GROUP(msiof2_clk_a),
4306 SH_PFC_PIN_GROUP(msiof2_sync_a),
4307 SH_PFC_PIN_GROUP(msiof2_ss1_a),
4308 SH_PFC_PIN_GROUP(msiof2_ss2_a),
4309 SH_PFC_PIN_GROUP(msiof2_txd_a),
4310 SH_PFC_PIN_GROUP(msiof2_rxd_a),
4311 SH_PFC_PIN_GROUP(msiof2_clk_b),
4312 SH_PFC_PIN_GROUP(msiof2_sync_b),
4313 SH_PFC_PIN_GROUP(msiof2_ss1_b),
4314 SH_PFC_PIN_GROUP(msiof2_ss2_b),
4315 SH_PFC_PIN_GROUP(msiof2_txd_b),
4316 SH_PFC_PIN_GROUP(msiof2_rxd_b),
4317 SH_PFC_PIN_GROUP(msiof2_clk_c),
4318 SH_PFC_PIN_GROUP(msiof2_sync_c),
4319 SH_PFC_PIN_GROUP(msiof2_ss1_c),
4320 SH_PFC_PIN_GROUP(msiof2_ss2_c),
4321 SH_PFC_PIN_GROUP(msiof2_txd_c),
4322 SH_PFC_PIN_GROUP(msiof2_rxd_c),
4323 SH_PFC_PIN_GROUP(msiof2_clk_d),
4324 SH_PFC_PIN_GROUP(msiof2_sync_d),
4325 SH_PFC_PIN_GROUP(msiof2_ss1_d),
4326 SH_PFC_PIN_GROUP(msiof2_ss2_d),
4327 SH_PFC_PIN_GROUP(msiof2_txd_d),
4328 SH_PFC_PIN_GROUP(msiof2_rxd_d),
4329 SH_PFC_PIN_GROUP(msiof3_clk_a),
4330 SH_PFC_PIN_GROUP(msiof3_sync_a),
4331 SH_PFC_PIN_GROUP(msiof3_ss1_a),
4332 SH_PFC_PIN_GROUP(msiof3_ss2_a),
4333 SH_PFC_PIN_GROUP(msiof3_txd_a),
4334 SH_PFC_PIN_GROUP(msiof3_rxd_a),
4335 SH_PFC_PIN_GROUP(msiof3_clk_b),
4336 SH_PFC_PIN_GROUP(msiof3_sync_b),
4337 SH_PFC_PIN_GROUP(msiof3_ss1_b),
4338 SH_PFC_PIN_GROUP(msiof3_ss2_b),
4339 SH_PFC_PIN_GROUP(msiof3_txd_b),
4340 SH_PFC_PIN_GROUP(msiof3_rxd_b),
4341 SH_PFC_PIN_GROUP(msiof3_clk_c),
4342 SH_PFC_PIN_GROUP(msiof3_sync_c),
4343 SH_PFC_PIN_GROUP(msiof3_txd_c),
4344 SH_PFC_PIN_GROUP(msiof3_rxd_c),
4345 SH_PFC_PIN_GROUP(msiof3_clk_d),
4346 SH_PFC_PIN_GROUP(msiof3_sync_d),
4347 SH_PFC_PIN_GROUP(msiof3_ss1_d),
4348 SH_PFC_PIN_GROUP(msiof3_txd_d),
4349 SH_PFC_PIN_GROUP(msiof3_rxd_d),
4350 SH_PFC_PIN_GROUP(msiof3_clk_e),
4351 SH_PFC_PIN_GROUP(msiof3_sync_e),
4352 SH_PFC_PIN_GROUP(msiof3_ss1_e),
4353 SH_PFC_PIN_GROUP(msiof3_ss2_e),
4354 SH_PFC_PIN_GROUP(msiof3_txd_e),
4355 SH_PFC_PIN_GROUP(msiof3_rxd_e),
4356 SH_PFC_PIN_GROUP(pwm0),
4357 SH_PFC_PIN_GROUP(pwm1_a),
4358 SH_PFC_PIN_GROUP(pwm1_b),
4359 SH_PFC_PIN_GROUP(pwm2_a),
4360 SH_PFC_PIN_GROUP(pwm2_b),
4361 SH_PFC_PIN_GROUP(pwm3_a),
4362 SH_PFC_PIN_GROUP(pwm3_b),
4363 SH_PFC_PIN_GROUP(pwm4_a),
4364 SH_PFC_PIN_GROUP(pwm4_b),
4365 SH_PFC_PIN_GROUP(pwm5_a),
4366 SH_PFC_PIN_GROUP(pwm5_b),
4367 SH_PFC_PIN_GROUP(pwm6_a),
4368 SH_PFC_PIN_GROUP(pwm6_b),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4369 SH_PFC_PIN_GROUP(sata0_devslp_a),
4370 SH_PFC_PIN_GROUP(sata0_devslp_b),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4371 SH_PFC_PIN_GROUP(scif0_data),
4372 SH_PFC_PIN_GROUP(scif0_clk),
4373 SH_PFC_PIN_GROUP(scif0_ctrl),
4374 SH_PFC_PIN_GROUP(scif1_data_a),
4375 SH_PFC_PIN_GROUP(scif1_clk),
4376 SH_PFC_PIN_GROUP(scif1_ctrl),
4377 SH_PFC_PIN_GROUP(scif1_data_b),
4378 SH_PFC_PIN_GROUP(scif2_data_a),
4379 SH_PFC_PIN_GROUP(scif2_clk),
4380 SH_PFC_PIN_GROUP(scif2_data_b),
4381 SH_PFC_PIN_GROUP(scif3_data_a),
4382 SH_PFC_PIN_GROUP(scif3_clk),
4383 SH_PFC_PIN_GROUP(scif3_ctrl),
4384 SH_PFC_PIN_GROUP(scif3_data_b),
4385 SH_PFC_PIN_GROUP(scif4_data_a),
4386 SH_PFC_PIN_GROUP(scif4_clk_a),
4387 SH_PFC_PIN_GROUP(scif4_ctrl_a),
4388 SH_PFC_PIN_GROUP(scif4_data_b),
4389 SH_PFC_PIN_GROUP(scif4_clk_b),
4390 SH_PFC_PIN_GROUP(scif4_ctrl_b),
4391 SH_PFC_PIN_GROUP(scif4_data_c),
4392 SH_PFC_PIN_GROUP(scif4_clk_c),
4393 SH_PFC_PIN_GROUP(scif4_ctrl_c),
4394 SH_PFC_PIN_GROUP(scif5_data_a),
4395 SH_PFC_PIN_GROUP(scif5_clk_a),
4396 SH_PFC_PIN_GROUP(scif5_data_b),
4397 SH_PFC_PIN_GROUP(scif5_clk_b),
4398 SH_PFC_PIN_GROUP(scif_clk_a),
4399 SH_PFC_PIN_GROUP(scif_clk_b),
4400 SH_PFC_PIN_GROUP(sdhi0_data1),
4401 SH_PFC_PIN_GROUP(sdhi0_data4),
4402 SH_PFC_PIN_GROUP(sdhi0_ctrl),
4403 SH_PFC_PIN_GROUP(sdhi0_cd),
4404 SH_PFC_PIN_GROUP(sdhi0_wp),
4405 SH_PFC_PIN_GROUP(sdhi1_data1),
4406 SH_PFC_PIN_GROUP(sdhi1_data4),
4407 SH_PFC_PIN_GROUP(sdhi1_ctrl),
4408 SH_PFC_PIN_GROUP(sdhi1_cd),
4409 SH_PFC_PIN_GROUP(sdhi1_wp),
4410 SH_PFC_PIN_GROUP(sdhi2_data1),
4411 SH_PFC_PIN_GROUP(sdhi2_data4),
4412 SH_PFC_PIN_GROUP(sdhi2_data8),
4413 SH_PFC_PIN_GROUP(sdhi2_ctrl),
4414 SH_PFC_PIN_GROUP(sdhi2_cd_a),
4415 SH_PFC_PIN_GROUP(sdhi2_wp_a),
4416 SH_PFC_PIN_GROUP(sdhi2_cd_b),
4417 SH_PFC_PIN_GROUP(sdhi2_wp_b),
4418 SH_PFC_PIN_GROUP(sdhi2_ds),
4419 SH_PFC_PIN_GROUP(sdhi3_data1),
4420 SH_PFC_PIN_GROUP(sdhi3_data4),
4421 SH_PFC_PIN_GROUP(sdhi3_data8),
4422 SH_PFC_PIN_GROUP(sdhi3_ctrl),
4423 SH_PFC_PIN_GROUP(sdhi3_cd),
4424 SH_PFC_PIN_GROUP(sdhi3_wp),
4425 SH_PFC_PIN_GROUP(sdhi3_ds),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4426 SH_PFC_PIN_GROUP(ssi0_data),
4427 SH_PFC_PIN_GROUP(ssi01239_ctrl),
4428 SH_PFC_PIN_GROUP(ssi1_data_a),
4429 SH_PFC_PIN_GROUP(ssi1_data_b),
4430 SH_PFC_PIN_GROUP(ssi1_ctrl_a),
4431 SH_PFC_PIN_GROUP(ssi1_ctrl_b),
4432 SH_PFC_PIN_GROUP(ssi2_data_a),
4433 SH_PFC_PIN_GROUP(ssi2_data_b),
4434 SH_PFC_PIN_GROUP(ssi2_ctrl_a),
4435 SH_PFC_PIN_GROUP(ssi2_ctrl_b),
4436 SH_PFC_PIN_GROUP(ssi3_data),
4437 SH_PFC_PIN_GROUP(ssi349_ctrl),
4438 SH_PFC_PIN_GROUP(ssi4_data),
4439 SH_PFC_PIN_GROUP(ssi4_ctrl),
4440 SH_PFC_PIN_GROUP(ssi5_data),
4441 SH_PFC_PIN_GROUP(ssi5_ctrl),
4442 SH_PFC_PIN_GROUP(ssi6_data),
4443 SH_PFC_PIN_GROUP(ssi6_ctrl),
4444 SH_PFC_PIN_GROUP(ssi7_data),
4445 SH_PFC_PIN_GROUP(ssi78_ctrl),
4446 SH_PFC_PIN_GROUP(ssi8_data),
4447 SH_PFC_PIN_GROUP(ssi9_data_a),
4448 SH_PFC_PIN_GROUP(ssi9_data_b),
4449 SH_PFC_PIN_GROUP(ssi9_ctrl_a),
4450 SH_PFC_PIN_GROUP(ssi9_ctrl_b),
4451 SH_PFC_PIN_GROUP(tmu_tclk1_a),
4452 SH_PFC_PIN_GROUP(tmu_tclk1_b),
4453 SH_PFC_PIN_GROUP(tmu_tclk2_a),
4454 SH_PFC_PIN_GROUP(tmu_tclk2_b),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4455 SH_PFC_PIN_GROUP(usb0),
4456 SH_PFC_PIN_GROUP(usb1),
4457 SH_PFC_PIN_GROUP(usb2),
4458 SH_PFC_PIN_GROUP(usb2_ch3),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4459 SH_PFC_PIN_GROUP(usb30),
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]4460 VIN_DATA_PIN_GROUP(vin4_data, 8, _a),
4461 VIN_DATA_PIN_GROUP(vin4_data, 10, _a),
4462 VIN_DATA_PIN_GROUP(vin4_data, 12, _a),
4463 VIN_DATA_PIN_GROUP(vin4_data, 16, _a),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4464 SH_PFC_PIN_GROUP(vin4_data18_a),
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]4465 VIN_DATA_PIN_GROUP(vin4_data, 20, _a),
4466 VIN_DATA_PIN_GROUP(vin4_data, 24, _a),
4467 VIN_DATA_PIN_GROUP(vin4_data, 8, _b),
4468 VIN_DATA_PIN_GROUP(vin4_data, 10, _b),
4469 VIN_DATA_PIN_GROUP(vin4_data, 12, _b),
4470 VIN_DATA_PIN_GROUP(vin4_data, 16, _b),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4471 SH_PFC_PIN_GROUP(vin4_data18_b),
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]4472 VIN_DATA_PIN_GROUP(vin4_data, 20, _b),
4473 VIN_DATA_PIN_GROUP(vin4_data, 24, _b),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4474 SH_PFC_PIN_GROUP(vin4_sync),
4475 SH_PFC_PIN_GROUP(vin4_field),
4476 SH_PFC_PIN_GROUP(vin4_clkenb),
4477 SH_PFC_PIN_GROUP(vin4_clk),
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]4478 VIN_DATA_PIN_GROUP(vin5_data, 8),
4479 VIN_DATA_PIN_GROUP(vin5_data, 10),
4480 VIN_DATA_PIN_GROUP(vin5_data, 12),
4481 VIN_DATA_PIN_GROUP(vin5_data, 16),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4482 SH_PFC_PIN_GROUP(vin5_sync),
4483 SH_PFC_PIN_GROUP(vin5_field),
4484 SH_PFC_PIN_GROUP(vin5_clkenb),
4485 SH_PFC_PIN_GROUP(vin5_clk),
4486};
4487
4488static const char * const audio_clk_groups[] = {
4489 "audio_clk_a_a",
4490 "audio_clk_a_b",
4491 "audio_clk_a_c",
4492 "audio_clk_b_a",
4493 "audio_clk_b_b",
4494 "audio_clk_c_a",
4495 "audio_clk_c_b",
4496 "audio_clkout_a",
4497 "audio_clkout_b",
4498 "audio_clkout_c",
4499 "audio_clkout_d",
4500 "audio_clkout1_a",
4501 "audio_clkout1_b",
4502 "audio_clkout2_a",
4503 "audio_clkout2_b",
4504 "audio_clkout3_a",
4505 "audio_clkout3_b",
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4506};
4507
4508static const char * const avb_groups[] = {
4509 "avb_link",
4510 "avb_magic",
4511 "avb_phy_int",
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4512 "avb_mdc", /* Deprecated, please use "avb_mdio" instead */
4513 "avb_mdio",
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4514 "avb_mii",
4515 "avb_avtp_pps",
4516 "avb_avtp_match_a",
4517 "avb_avtp_capture_a",
4518 "avb_avtp_match_b",
4519 "avb_avtp_capture_b",
4520};
4521
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4522static const char * const can0_groups[] = {
4523 "can0_data_a",
4524 "can0_data_b",
4525};
4526
4527static const char * const can1_groups[] = {
4528 "can1_data",
4529};
4530
4531static const char * const can_clk_groups[] = {
4532 "can_clk",
4533};
4534
4535static const char * const canfd0_groups[] = {
4536 "canfd0_data_a",
4537 "canfd0_data_b",
4538};
4539
4540static const char * const canfd1_groups[] = {
4541 "canfd1_data",
4542};
4543
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4544static const char * const drif0_groups[] = {
4545 "drif0_ctrl_a",
4546 "drif0_data0_a",
4547 "drif0_data1_a",
4548 "drif0_ctrl_b",
4549 "drif0_data0_b",
4550 "drif0_data1_b",
4551 "drif0_ctrl_c",
4552 "drif0_data0_c",
4553 "drif0_data1_c",
4554};
4555
4556static const char * const drif1_groups[] = {
4557 "drif1_ctrl_a",
4558 "drif1_data0_a",
4559 "drif1_data1_a",
4560 "drif1_ctrl_b",
4561 "drif1_data0_b",
4562 "drif1_data1_b",
4563 "drif1_ctrl_c",
4564 "drif1_data0_c",
4565 "drif1_data1_c",
4566};
4567
4568static const char * const drif2_groups[] = {
4569 "drif2_ctrl_a",
4570 "drif2_data0_a",
4571 "drif2_data1_a",
4572 "drif2_ctrl_b",
4573 "drif2_data0_b",
4574 "drif2_data1_b",
4575};
4576
4577static const char * const drif3_groups[] = {
4578 "drif3_ctrl_a",
4579 "drif3_data0_a",
4580 "drif3_data1_a",
4581 "drif3_ctrl_b",
4582 "drif3_data0_b",
4583 "drif3_data1_b",
4584};
4585
4586static const char * const du_groups[] = {
4587 "du_rgb666",
4588 "du_rgb888",
4589 "du_clk_out_0",
4590 "du_clk_out_1",
4591 "du_sync",
4592 "du_oddf",
4593 "du_cde",
4594 "du_disp",
4595};
4596
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4597static const char * const hscif0_groups[] = {
4598 "hscif0_data",
4599 "hscif0_clk",
4600 "hscif0_ctrl",
4601};
4602
4603static const char * const hscif1_groups[] = {
4604 "hscif1_data_a",
4605 "hscif1_clk_a",
4606 "hscif1_ctrl_a",
4607 "hscif1_data_b",
4608 "hscif1_clk_b",
4609 "hscif1_ctrl_b",
4610};
4611
4612static const char * const hscif2_groups[] = {
4613 "hscif2_data_a",
4614 "hscif2_clk_a",
4615 "hscif2_ctrl_a",
4616 "hscif2_data_b",
4617 "hscif2_clk_b",
4618 "hscif2_ctrl_b",
4619 "hscif2_data_c",
4620 "hscif2_clk_c",
4621 "hscif2_ctrl_c",
4622};
4623
4624static const char * const hscif3_groups[] = {
4625 "hscif3_data_a",
4626 "hscif3_clk",
4627 "hscif3_ctrl",
4628 "hscif3_data_b",
4629 "hscif3_data_c",
4630 "hscif3_data_d",
4631};
4632
4633static const char * const hscif4_groups[] = {
4634 "hscif4_data_a",
4635 "hscif4_clk",
4636 "hscif4_ctrl",
4637 "hscif4_data_b",
4638};
4639
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]4640static const char * const i2c0_groups[] = {
4641 "i2c0",
4642};
4643
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4644static const char * const i2c1_groups[] = {
4645 "i2c1_a",
4646 "i2c1_b",
4647};
4648
4649static const char * const i2c2_groups[] = {
4650 "i2c2_a",
4651 "i2c2_b",
4652};
4653
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]4654static const char * const i2c3_groups[] = {
4655 "i2c3",
4656};
4657
4658static const char * const i2c5_groups[] = {
4659 "i2c5",
4660};
4661
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4662static const char * const i2c6_groups[] = {
4663 "i2c6_a",
4664 "i2c6_b",
4665 "i2c6_c",
4666};
4667
4668static const char * const intc_ex_groups[] = {
4669 "intc_ex_irq0",
4670 "intc_ex_irq1",
4671 "intc_ex_irq2",
4672 "intc_ex_irq3",
4673 "intc_ex_irq4",
4674 "intc_ex_irq5",
4675};
4676
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4677static const char * const msiof0_groups[] = {
4678 "msiof0_clk",
4679 "msiof0_sync",
4680 "msiof0_ss1",
4681 "msiof0_ss2",
4682 "msiof0_txd",
4683 "msiof0_rxd",
4684};
4685
4686static const char * const msiof1_groups[] = {
4687 "msiof1_clk_a",
4688 "msiof1_sync_a",
4689 "msiof1_ss1_a",
4690 "msiof1_ss2_a",
4691 "msiof1_txd_a",
4692 "msiof1_rxd_a",
4693 "msiof1_clk_b",
4694 "msiof1_sync_b",
4695 "msiof1_ss1_b",
4696 "msiof1_ss2_b",
4697 "msiof1_txd_b",
4698 "msiof1_rxd_b",
4699 "msiof1_clk_c",
4700 "msiof1_sync_c",
4701 "msiof1_ss1_c",
4702 "msiof1_ss2_c",
4703 "msiof1_txd_c",
4704 "msiof1_rxd_c",
4705 "msiof1_clk_d",
4706 "msiof1_sync_d",
4707 "msiof1_ss1_d",
4708 "msiof1_ss2_d",
4709 "msiof1_txd_d",
4710 "msiof1_rxd_d",
4711 "msiof1_clk_e",
4712 "msiof1_sync_e",
4713 "msiof1_ss1_e",
4714 "msiof1_ss2_e",
4715 "msiof1_txd_e",
4716 "msiof1_rxd_e",
4717 "msiof1_clk_f",
4718 "msiof1_sync_f",
4719 "msiof1_ss1_f",
4720 "msiof1_ss2_f",
4721 "msiof1_txd_f",
4722 "msiof1_rxd_f",
4723 "msiof1_clk_g",
4724 "msiof1_sync_g",
4725 "msiof1_ss1_g",
4726 "msiof1_ss2_g",
4727 "msiof1_txd_g",
4728 "msiof1_rxd_g",
4729};
4730
4731static const char * const msiof2_groups[] = {
4732 "msiof2_clk_a",
4733 "msiof2_sync_a",
4734 "msiof2_ss1_a",
4735 "msiof2_ss2_a",
4736 "msiof2_txd_a",
4737 "msiof2_rxd_a",
4738 "msiof2_clk_b",
4739 "msiof2_sync_b",
4740 "msiof2_ss1_b",
4741 "msiof2_ss2_b",
4742 "msiof2_txd_b",
4743 "msiof2_rxd_b",
4744 "msiof2_clk_c",
4745 "msiof2_sync_c",
4746 "msiof2_ss1_c",
4747 "msiof2_ss2_c",
4748 "msiof2_txd_c",
4749 "msiof2_rxd_c",
4750 "msiof2_clk_d",
4751 "msiof2_sync_d",
4752 "msiof2_ss1_d",
4753 "msiof2_ss2_d",
4754 "msiof2_txd_d",
4755 "msiof2_rxd_d",
4756};
4757
4758static const char * const msiof3_groups[] = {
4759 "msiof3_clk_a",
4760 "msiof3_sync_a",
4761 "msiof3_ss1_a",
4762 "msiof3_ss2_a",
4763 "msiof3_txd_a",
4764 "msiof3_rxd_a",
4765 "msiof3_clk_b",
4766 "msiof3_sync_b",
4767 "msiof3_ss1_b",
4768 "msiof3_ss2_b",
4769 "msiof3_txd_b",
4770 "msiof3_rxd_b",
4771 "msiof3_clk_c",
4772 "msiof3_sync_c",
4773 "msiof3_txd_c",
4774 "msiof3_rxd_c",
4775 "msiof3_clk_d",
4776 "msiof3_sync_d",
4777 "msiof3_ss1_d",
4778 "msiof3_txd_d",
4779 "msiof3_rxd_d",
4780 "msiof3_clk_e",
4781 "msiof3_sync_e",
4782 "msiof3_ss1_e",
4783 "msiof3_ss2_e",
4784 "msiof3_txd_e",
4785 "msiof3_rxd_e",
4786};
4787
4788static const char * const pwm0_groups[] = {
4789 "pwm0",
4790};
4791
4792static const char * const pwm1_groups[] = {
4793 "pwm1_a",
4794 "pwm1_b",
4795};
4796
4797static const char * const pwm2_groups[] = {
4798 "pwm2_a",
4799 "pwm2_b",
4800};
4801
4802static const char * const pwm3_groups[] = {
4803 "pwm3_a",
4804 "pwm3_b",
4805};
4806
4807static const char * const pwm4_groups[] = {
4808 "pwm4_a",
4809 "pwm4_b",
4810};
4811
4812static const char * const pwm5_groups[] = {
4813 "pwm5_a",
4814 "pwm5_b",
4815};
4816
4817static const char * const pwm6_groups[] = {
4818 "pwm6_a",
4819 "pwm6_b",
4820};
4821
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4822static const char * const sata0_groups[] = {
4823 "sata0_devslp_a",
4824 "sata0_devslp_b",
4825};
4826
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4827static const char * const scif0_groups[] = {
4828 "scif0_data",
4829 "scif0_clk",
4830 "scif0_ctrl",
4831};
4832
4833static const char * const scif1_groups[] = {
4834 "scif1_data_a",
4835 "scif1_clk",
4836 "scif1_ctrl",
4837 "scif1_data_b",
4838};
4839
4840static const char * const scif2_groups[] = {
4841 "scif2_data_a",
4842 "scif2_clk",
4843 "scif2_data_b",
4844};
4845
4846static const char * const scif3_groups[] = {
4847 "scif3_data_a",
4848 "scif3_clk",
4849 "scif3_ctrl",
4850 "scif3_data_b",
4851};
4852
4853static const char * const scif4_groups[] = {
4854 "scif4_data_a",
4855 "scif4_clk_a",
4856 "scif4_ctrl_a",
4857 "scif4_data_b",
4858 "scif4_clk_b",
4859 "scif4_ctrl_b",
4860 "scif4_data_c",
4861 "scif4_clk_c",
4862 "scif4_ctrl_c",
4863};
4864
4865static const char * const scif5_groups[] = {
4866 "scif5_data_a",
4867 "scif5_clk_a",
4868 "scif5_data_b",
4869 "scif5_clk_b",
4870};
4871
4872static const char * const scif_clk_groups[] = {
4873 "scif_clk_a",
4874 "scif_clk_b",
4875};
4876
4877static const char * const sdhi0_groups[] = {
4878 "sdhi0_data1",
4879 "sdhi0_data4",
4880 "sdhi0_ctrl",
4881 "sdhi0_cd",
4882 "sdhi0_wp",
4883};
4884
4885static const char * const sdhi1_groups[] = {
4886 "sdhi1_data1",
4887 "sdhi1_data4",
4888 "sdhi1_ctrl",
4889 "sdhi1_cd",
4890 "sdhi1_wp",
4891};
4892
4893static const char * const sdhi2_groups[] = {
4894 "sdhi2_data1",
4895 "sdhi2_data4",
4896 "sdhi2_data8",
4897 "sdhi2_ctrl",
4898 "sdhi2_cd_a",
4899 "sdhi2_wp_a",
4900 "sdhi2_cd_b",
4901 "sdhi2_wp_b",
4902 "sdhi2_ds",
4903};
4904
4905static const char * const sdhi3_groups[] = {
4906 "sdhi3_data1",
4907 "sdhi3_data4",
4908 "sdhi3_data8",
4909 "sdhi3_ctrl",
4910 "sdhi3_cd",
4911 "sdhi3_wp",
4912 "sdhi3_ds",
4913};
4914
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4915static const char * const ssi_groups[] = {
4916 "ssi0_data",
4917 "ssi01239_ctrl",
4918 "ssi1_data_a",
4919 "ssi1_data_b",
4920 "ssi1_ctrl_a",
4921 "ssi1_ctrl_b",
4922 "ssi2_data_a",
4923 "ssi2_data_b",
4924 "ssi2_ctrl_a",
4925 "ssi2_ctrl_b",
4926 "ssi3_data",
4927 "ssi349_ctrl",
4928 "ssi4_data",
4929 "ssi4_ctrl",
4930 "ssi5_data",
4931 "ssi5_ctrl",
4932 "ssi6_data",
4933 "ssi6_ctrl",
4934 "ssi7_data",
4935 "ssi78_ctrl",
4936 "ssi8_data",
4937 "ssi9_data_a",
4938 "ssi9_data_b",
4939 "ssi9_ctrl_a",
4940 "ssi9_ctrl_b",
4941};
4942
4943static const char * const tmu_groups[] = {
4944 "tmu_tclk1_a",
4945 "tmu_tclk1_b",
4946 "tmu_tclk2_a",
4947 "tmu_tclk2_b",
4948};
4949
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4950static const char * const usb0_groups[] = {
4951 "usb0",
4952};
4953
4954static const char * const usb1_groups[] = {
4955 "usb1",
4956};
4957
4958static const char * const usb2_groups[] = {
4959 "usb2",
4960};
4961
4962static const char * const usb2_ch3_groups[] = {
4963 "usb2_ch3",
4964};
4965
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4966static const char * const usb30_groups[] = {
4967 "usb30",
4968};
4969
4970static const char * const vin4_groups[] = {
4971 "vin4_data8_a",
4972 "vin4_data10_a",
4973 "vin4_data12_a",
4974 "vin4_data16_a",
4975 "vin4_data18_a",
4976 "vin4_data20_a",
4977 "vin4_data24_a",
4978 "vin4_data8_b",
4979 "vin4_data10_b",
4980 "vin4_data12_b",
4981 "vin4_data16_b",
4982 "vin4_data18_b",
4983 "vin4_data20_b",
4984 "vin4_data24_b",
4985 "vin4_sync",
4986 "vin4_field",
4987 "vin4_clkenb",
4988 "vin4_clk",
4989};
4990
4991static const char * const vin5_groups[] = {
4992 "vin5_data8",
4993 "vin5_data10",
4994 "vin5_data12",
4995 "vin5_data16",
4996 "vin5_sync",
4997 "vin5_field",
4998 "vin5_clkenb",
4999 "vin5_clk",
5000};
5001
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5002static const struct sh_pfc_function pinmux_functions[] = {
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5003 SH_PFC_FUNCTION(audio_clk),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5004 SH_PFC_FUNCTION(avb),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5005 SH_PFC_FUNCTION(can0),
5006 SH_PFC_FUNCTION(can1),
5007 SH_PFC_FUNCTION(can_clk),
5008 SH_PFC_FUNCTION(canfd0),
5009 SH_PFC_FUNCTION(canfd1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5010 SH_PFC_FUNCTION(drif0),
5011 SH_PFC_FUNCTION(drif1),
5012 SH_PFC_FUNCTION(drif2),
5013 SH_PFC_FUNCTION(drif3),
5014 SH_PFC_FUNCTION(du),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5015 SH_PFC_FUNCTION(hscif0),
5016 SH_PFC_FUNCTION(hscif1),
5017 SH_PFC_FUNCTION(hscif2),
5018 SH_PFC_FUNCTION(hscif3),
5019 SH_PFC_FUNCTION(hscif4),
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]5020 SH_PFC_FUNCTION(i2c0),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5021 SH_PFC_FUNCTION(i2c1),
5022 SH_PFC_FUNCTION(i2c2),
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]5023 SH_PFC_FUNCTION(i2c3),
5024 SH_PFC_FUNCTION(i2c5),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5025 SH_PFC_FUNCTION(i2c6),
5026 SH_PFC_FUNCTION(intc_ex),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5027 SH_PFC_FUNCTION(msiof0),
5028 SH_PFC_FUNCTION(msiof1),
5029 SH_PFC_FUNCTION(msiof2),
5030 SH_PFC_FUNCTION(msiof3),
5031 SH_PFC_FUNCTION(pwm0),
5032 SH_PFC_FUNCTION(pwm1),
5033 SH_PFC_FUNCTION(pwm2),
5034 SH_PFC_FUNCTION(pwm3),
5035 SH_PFC_FUNCTION(pwm4),
5036 SH_PFC_FUNCTION(pwm5),
5037 SH_PFC_FUNCTION(pwm6),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5038 SH_PFC_FUNCTION(sata0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5039 SH_PFC_FUNCTION(scif0),
5040 SH_PFC_FUNCTION(scif1),
5041 SH_PFC_FUNCTION(scif2),
5042 SH_PFC_FUNCTION(scif3),
5043 SH_PFC_FUNCTION(scif4),
5044 SH_PFC_FUNCTION(scif5),
5045 SH_PFC_FUNCTION(scif_clk),
5046 SH_PFC_FUNCTION(sdhi0),
5047 SH_PFC_FUNCTION(sdhi1),
5048 SH_PFC_FUNCTION(sdhi2),
5049 SH_PFC_FUNCTION(sdhi3),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5050 SH_PFC_FUNCTION(ssi),
5051 SH_PFC_FUNCTION(tmu),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5052 SH_PFC_FUNCTION(usb0),
5053 SH_PFC_FUNCTION(usb1),
5054 SH_PFC_FUNCTION(usb2),
5055 SH_PFC_FUNCTION(usb2_ch3),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5056 SH_PFC_FUNCTION(usb30),
5057 SH_PFC_FUNCTION(vin4),
5058 SH_PFC_FUNCTION(vin5),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5059};
5060
5061static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5062#define F_(x, y) FN_##y
5063#define FM(x) FN_##x
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5064 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5065 0, 0,
5066 0, 0,
5067 0, 0,
5068 0, 0,
5069 0, 0,
5070 0, 0,
5071 0, 0,
5072 0, 0,
5073 0, 0,
5074 0, 0,
5075 0, 0,
5076 0, 0,
5077 0, 0,
5078 0, 0,
5079 0, 0,
5080 0, 0,
5081 GP_0_15_FN, GPSR0_15,
5082 GP_0_14_FN, GPSR0_14,
5083 GP_0_13_FN, GPSR0_13,
5084 GP_0_12_FN, GPSR0_12,
5085 GP_0_11_FN, GPSR0_11,
5086 GP_0_10_FN, GPSR0_10,
5087 GP_0_9_FN, GPSR0_9,
5088 GP_0_8_FN, GPSR0_8,
5089 GP_0_7_FN, GPSR0_7,
5090 GP_0_6_FN, GPSR0_6,
5091 GP_0_5_FN, GPSR0_5,
5092 GP_0_4_FN, GPSR0_4,
5093 GP_0_3_FN, GPSR0_3,
5094 GP_0_2_FN, GPSR0_2,
5095 GP_0_1_FN, GPSR0_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5096 GP_0_0_FN, GPSR0_0, ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5097 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5098 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5099 0, 0,
5100 0, 0,
5101 0, 0,
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5102 GP_1_28_FN, GPSR1_28,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5103 GP_1_27_FN, GPSR1_27,
5104 GP_1_26_FN, GPSR1_26,
5105 GP_1_25_FN, GPSR1_25,
5106 GP_1_24_FN, GPSR1_24,
5107 GP_1_23_FN, GPSR1_23,
5108 GP_1_22_FN, GPSR1_22,
5109 GP_1_21_FN, GPSR1_21,
5110 GP_1_20_FN, GPSR1_20,
5111 GP_1_19_FN, GPSR1_19,
5112 GP_1_18_FN, GPSR1_18,
5113 GP_1_17_FN, GPSR1_17,
5114 GP_1_16_FN, GPSR1_16,
5115 GP_1_15_FN, GPSR1_15,
5116 GP_1_14_FN, GPSR1_14,
5117 GP_1_13_FN, GPSR1_13,
5118 GP_1_12_FN, GPSR1_12,
5119 GP_1_11_FN, GPSR1_11,
5120 GP_1_10_FN, GPSR1_10,
5121 GP_1_9_FN, GPSR1_9,
5122 GP_1_8_FN, GPSR1_8,
5123 GP_1_7_FN, GPSR1_7,
5124 GP_1_6_FN, GPSR1_6,
5125 GP_1_5_FN, GPSR1_5,
5126 GP_1_4_FN, GPSR1_4,
5127 GP_1_3_FN, GPSR1_3,
5128 GP_1_2_FN, GPSR1_2,
5129 GP_1_1_FN, GPSR1_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5130 GP_1_0_FN, GPSR1_0, ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5131 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5132 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5133 0, 0,
5134 0, 0,
5135 0, 0,
5136 0, 0,
5137 0, 0,
5138 0, 0,
5139 0, 0,
5140 0, 0,
5141 0, 0,
5142 0, 0,
5143 0, 0,
5144 0, 0,
5145 0, 0,
5146 0, 0,
5147 0, 0,
5148 0, 0,
5149 0, 0,
5150 GP_2_14_FN, GPSR2_14,
5151 GP_2_13_FN, GPSR2_13,
5152 GP_2_12_FN, GPSR2_12,
5153 GP_2_11_FN, GPSR2_11,
5154 GP_2_10_FN, GPSR2_10,
5155 GP_2_9_FN, GPSR2_9,
5156 GP_2_8_FN, GPSR2_8,
5157 GP_2_7_FN, GPSR2_7,
5158 GP_2_6_FN, GPSR2_6,
5159 GP_2_5_FN, GPSR2_5,
5160 GP_2_4_FN, GPSR2_4,
5161 GP_2_3_FN, GPSR2_3,
5162 GP_2_2_FN, GPSR2_2,
5163 GP_2_1_FN, GPSR2_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5164 GP_2_0_FN, GPSR2_0, ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5165 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5166 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5167 0, 0,
5168 0, 0,
5169 0, 0,
5170 0, 0,
5171 0, 0,
5172 0, 0,
5173 0, 0,
5174 0, 0,
5175 0, 0,
5176 0, 0,
5177 0, 0,
5178 0, 0,
5179 0, 0,
5180 0, 0,
5181 0, 0,
5182 0, 0,
5183 GP_3_15_FN, GPSR3_15,
5184 GP_3_14_FN, GPSR3_14,
5185 GP_3_13_FN, GPSR3_13,
5186 GP_3_12_FN, GPSR3_12,
5187 GP_3_11_FN, GPSR3_11,
5188 GP_3_10_FN, GPSR3_10,
5189 GP_3_9_FN, GPSR3_9,
5190 GP_3_8_FN, GPSR3_8,
5191 GP_3_7_FN, GPSR3_7,
5192 GP_3_6_FN, GPSR3_6,
5193 GP_3_5_FN, GPSR3_5,
5194 GP_3_4_FN, GPSR3_4,
5195 GP_3_3_FN, GPSR3_3,
5196 GP_3_2_FN, GPSR3_2,
5197 GP_3_1_FN, GPSR3_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5198 GP_3_0_FN, GPSR3_0, ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5199 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5200 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5201 0, 0,
5202 0, 0,
5203 0, 0,
5204 0, 0,
5205 0, 0,
5206 0, 0,
5207 0, 0,
5208 0, 0,
5209 0, 0,
5210 0, 0,
5211 0, 0,
5212 0, 0,
5213 0, 0,
5214 0, 0,
5215 GP_4_17_FN, GPSR4_17,
5216 GP_4_16_FN, GPSR4_16,
5217 GP_4_15_FN, GPSR4_15,
5218 GP_4_14_FN, GPSR4_14,
5219 GP_4_13_FN, GPSR4_13,
5220 GP_4_12_FN, GPSR4_12,
5221 GP_4_11_FN, GPSR4_11,
5222 GP_4_10_FN, GPSR4_10,
5223 GP_4_9_FN, GPSR4_9,
5224 GP_4_8_FN, GPSR4_8,
5225 GP_4_7_FN, GPSR4_7,
5226 GP_4_6_FN, GPSR4_6,
5227 GP_4_5_FN, GPSR4_5,
5228 GP_4_4_FN, GPSR4_4,
5229 GP_4_3_FN, GPSR4_3,
5230 GP_4_2_FN, GPSR4_2,
5231 GP_4_1_FN, GPSR4_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5232 GP_4_0_FN, GPSR4_0, ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5233 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5234 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5235 0, 0,
5236 0, 0,
5237 0, 0,
5238 0, 0,
5239 0, 0,
5240 0, 0,
5241 GP_5_25_FN, GPSR5_25,
5242 GP_5_24_FN, GPSR5_24,
5243 GP_5_23_FN, GPSR5_23,
5244 GP_5_22_FN, GPSR5_22,
5245 GP_5_21_FN, GPSR5_21,
5246 GP_5_20_FN, GPSR5_20,
5247 GP_5_19_FN, GPSR5_19,
5248 GP_5_18_FN, GPSR5_18,
5249 GP_5_17_FN, GPSR5_17,
5250 GP_5_16_FN, GPSR5_16,
5251 GP_5_15_FN, GPSR5_15,
5252 GP_5_14_FN, GPSR5_14,
5253 GP_5_13_FN, GPSR5_13,
5254 GP_5_12_FN, GPSR5_12,
5255 GP_5_11_FN, GPSR5_11,
5256 GP_5_10_FN, GPSR5_10,
5257 GP_5_9_FN, GPSR5_9,
5258 GP_5_8_FN, GPSR5_8,
5259 GP_5_7_FN, GPSR5_7,
5260 GP_5_6_FN, GPSR5_6,
5261 GP_5_5_FN, GPSR5_5,
5262 GP_5_4_FN, GPSR5_4,
5263 GP_5_3_FN, GPSR5_3,
5264 GP_5_2_FN, GPSR5_2,
5265 GP_5_1_FN, GPSR5_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5266 GP_5_0_FN, GPSR5_0, ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5267 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5268 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5269 GP_6_31_FN, GPSR6_31,
5270 GP_6_30_FN, GPSR6_30,
5271 GP_6_29_FN, GPSR6_29,
5272 GP_6_28_FN, GPSR6_28,
5273 GP_6_27_FN, GPSR6_27,
5274 GP_6_26_FN, GPSR6_26,
5275 GP_6_25_FN, GPSR6_25,
5276 GP_6_24_FN, GPSR6_24,
5277 GP_6_23_FN, GPSR6_23,
5278 GP_6_22_FN, GPSR6_22,
5279 GP_6_21_FN, GPSR6_21,
5280 GP_6_20_FN, GPSR6_20,
5281 GP_6_19_FN, GPSR6_19,
5282 GP_6_18_FN, GPSR6_18,
5283 GP_6_17_FN, GPSR6_17,
5284 GP_6_16_FN, GPSR6_16,
5285 GP_6_15_FN, GPSR6_15,
5286 GP_6_14_FN, GPSR6_14,
5287 GP_6_13_FN, GPSR6_13,
5288 GP_6_12_FN, GPSR6_12,
5289 GP_6_11_FN, GPSR6_11,
5290 GP_6_10_FN, GPSR6_10,
5291 GP_6_9_FN, GPSR6_9,
5292 GP_6_8_FN, GPSR6_8,
5293 GP_6_7_FN, GPSR6_7,
5294 GP_6_6_FN, GPSR6_6,
5295 GP_6_5_FN, GPSR6_5,
5296 GP_6_4_FN, GPSR6_4,
5297 GP_6_3_FN, GPSR6_3,
5298 GP_6_2_FN, GPSR6_2,
5299 GP_6_1_FN, GPSR6_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5300 GP_6_0_FN, GPSR6_0, ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5301 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5302 { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5303 0, 0,
5304 0, 0,
5305 0, 0,
5306 0, 0,
5307 0, 0,
5308 0, 0,
5309 0, 0,
5310 0, 0,
5311 0, 0,
5312 0, 0,
5313 0, 0,
5314 0, 0,
5315 0, 0,
5316 0, 0,
5317 0, 0,
5318 0, 0,
5319 0, 0,
5320 0, 0,
5321 0, 0,
5322 0, 0,
5323 0, 0,
5324 0, 0,
5325 0, 0,
5326 0, 0,
5327 0, 0,
5328 0, 0,
5329 0, 0,
5330 0, 0,
5331 GP_7_3_FN, GPSR7_3,
5332 GP_7_2_FN, GPSR7_2,
5333 GP_7_1_FN, GPSR7_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5334 GP_7_0_FN, GPSR7_0, ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5335 },
5336#undef F_
5337#undef FM
5338
5339#define F_(x, y) x,
5340#define FM(x) FN_##x,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5341 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5342 IP0_31_28
5343 IP0_27_24
5344 IP0_23_20
5345 IP0_19_16
5346 IP0_15_12
5347 IP0_11_8
5348 IP0_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5349 IP0_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5350 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5351 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5352 IP1_31_28
5353 IP1_27_24
5354 IP1_23_20
5355 IP1_19_16
5356 IP1_15_12
5357 IP1_11_8
5358 IP1_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5359 IP1_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5360 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5361 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5362 IP2_31_28
5363 IP2_27_24
5364 IP2_23_20
5365 IP2_19_16
5366 IP2_15_12
5367 IP2_11_8
5368 IP2_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5369 IP2_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5370 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5371 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5372 IP3_31_28
5373 IP3_27_24
5374 IP3_23_20
5375 IP3_19_16
5376 IP3_15_12
5377 IP3_11_8
5378 IP3_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5379 IP3_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5380 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5381 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5382 IP4_31_28
5383 IP4_27_24
5384 IP4_23_20
5385 IP4_19_16
5386 IP4_15_12
5387 IP4_11_8
5388 IP4_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5389 IP4_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5390 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5391 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5392 IP5_31_28
5393 IP5_27_24
5394 IP5_23_20
5395 IP5_19_16
5396 IP5_15_12
5397 IP5_11_8
5398 IP5_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5399 IP5_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5400 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5401 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5402 IP6_31_28
5403 IP6_27_24
5404 IP6_23_20
5405 IP6_19_16
5406 IP6_15_12
5407 IP6_11_8
5408 IP6_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5409 IP6_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5410 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5411 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5412 IP7_31_28
5413 IP7_27_24
5414 IP7_23_20
5415 IP7_19_16
5416 /* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5417 IP7_11_8
5418 IP7_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5419 IP7_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5420 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5421 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5422 IP8_31_28
5423 IP8_27_24
5424 IP8_23_20
5425 IP8_19_16
5426 IP8_15_12
5427 IP8_11_8
5428 IP8_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5429 IP8_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5430 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5431 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5432 IP9_31_28
5433 IP9_27_24
5434 IP9_23_20
5435 IP9_19_16
5436 IP9_15_12
5437 IP9_11_8
5438 IP9_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5439 IP9_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5440 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5441 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5442 IP10_31_28
5443 IP10_27_24
5444 IP10_23_20
5445 IP10_19_16
5446 IP10_15_12
5447 IP10_11_8
5448 IP10_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5449 IP10_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5450 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5451 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5452 IP11_31_28
5453 IP11_27_24
5454 IP11_23_20
5455 IP11_19_16
5456 IP11_15_12
5457 IP11_11_8
5458 IP11_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5459 IP11_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5460 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5461 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5462 IP12_31_28
5463 IP12_27_24
5464 IP12_23_20
5465 IP12_19_16
5466 IP12_15_12
5467 IP12_11_8
5468 IP12_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5469 IP12_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5470 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5471 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5472 IP13_31_28
5473 IP13_27_24
5474 IP13_23_20
5475 IP13_19_16
5476 IP13_15_12
5477 IP13_11_8
5478 IP13_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5479 IP13_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5480 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5481 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5482 IP14_31_28
5483 IP14_27_24
5484 IP14_23_20
5485 IP14_19_16
5486 IP14_15_12
5487 IP14_11_8
5488 IP14_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5489 IP14_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5490 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5491 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5492 IP15_31_28
5493 IP15_27_24
5494 IP15_23_20
5495 IP15_19_16
5496 IP15_15_12
5497 IP15_11_8
5498 IP15_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5499 IP15_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5500 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5501 { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5502 IP16_31_28
5503 IP16_27_24
5504 IP16_23_20
5505 IP16_19_16
5506 IP16_15_12
5507 IP16_11_8
5508 IP16_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5509 IP16_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5510 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5511 { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5512 IP17_31_28
5513 IP17_27_24
5514 IP17_23_20
5515 IP17_19_16
5516 IP17_15_12
5517 IP17_11_8
5518 IP17_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5519 IP17_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5520 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5521 { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5522 /* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5523 /* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5524 /* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5525 /* IP18_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5526 /* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5527 /* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5528 IP18_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5529 IP18_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5530 },
5531#undef F_
5532#undef FM
5533
5534#define F_(x, y) x,
5535#define FM(x) FN_##x,
5536 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5537 GROUP(3, 2, 3, 1, 1, 1, 1, 1, 2, 1, 1, 2,
5538 1, 1, 1, 2, 2, 1, 2, 3),
5539 GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5540 MOD_SEL0_31_30_29
5541 MOD_SEL0_28_27
5542 MOD_SEL0_26_25_24
5543 MOD_SEL0_23
5544 MOD_SEL0_22
5545 MOD_SEL0_21
5546 MOD_SEL0_20
5547 MOD_SEL0_19
5548 MOD_SEL0_18_17
5549 MOD_SEL0_16
5550 0, 0, /* RESERVED 15 */
5551 MOD_SEL0_14_13
5552 MOD_SEL0_12
5553 MOD_SEL0_11
5554 MOD_SEL0_10
5555 MOD_SEL0_9_8
5556 MOD_SEL0_7_6
5557 MOD_SEL0_5
5558 MOD_SEL0_4_3
5559 /* RESERVED 2, 1, 0 */
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5560 0, 0, 0, 0, 0, 0, 0, 0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5561 },
5562 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5563 GROUP(2, 3, 1, 2, 3, 1, 1, 2, 1, 2, 1, 1,
5564 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1),
5565 GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5566 MOD_SEL1_31_30
5567 MOD_SEL1_29_28_27
5568 MOD_SEL1_26
5569 MOD_SEL1_25_24
5570 MOD_SEL1_23_22_21
5571 MOD_SEL1_20
5572 MOD_SEL1_19
5573 MOD_SEL1_18_17
5574 MOD_SEL1_16
5575 MOD_SEL1_15_14
5576 MOD_SEL1_13
5577 MOD_SEL1_12
5578 MOD_SEL1_11
5579 MOD_SEL1_10
5580 MOD_SEL1_9
5581 0, 0, 0, 0, /* RESERVED 8, 7 */
5582 MOD_SEL1_6
5583 MOD_SEL1_5
5584 MOD_SEL1_4
5585 MOD_SEL1_3
5586 MOD_SEL1_2
5587 MOD_SEL1_1
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5588 MOD_SEL1_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5589 },
5590 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5591 GROUP(1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1,
5592 1, 4, 4, 4, 3, 1),
5593 GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5594 MOD_SEL2_31
5595 MOD_SEL2_30
5596 MOD_SEL2_29
5597 MOD_SEL2_28_27
5598 MOD_SEL2_26
5599 MOD_SEL2_25_24_23
5600 /* RESERVED 22 */
5601 0, 0,
5602 MOD_SEL2_21
5603 MOD_SEL2_20
5604 MOD_SEL2_19
5605 MOD_SEL2_18
5606 MOD_SEL2_17
5607 /* RESERVED 16 */
5608 0, 0,
5609 /* RESERVED 15, 14, 13, 12 */
5610 0, 0, 0, 0, 0, 0, 0, 0,
5611 0, 0, 0, 0, 0, 0, 0, 0,
5612 /* RESERVED 11, 10, 9, 8 */
5613 0, 0, 0, 0, 0, 0, 0, 0,
5614 0, 0, 0, 0, 0, 0, 0, 0,
5615 /* RESERVED 7, 6, 5, 4 */
5616 0, 0, 0, 0, 0, 0, 0, 0,
5617 0, 0, 0, 0, 0, 0, 0, 0,
5618 /* RESERVED 3, 2, 1 */
5619 0, 0, 0, 0, 0, 0, 0, 0,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5620 MOD_SEL2_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5621 },
5622 { },
5623};
5624
5625static const struct pinmux_drive_reg pinmux_drive_regs[] = {
5626 { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
5627 { PIN_NUMBER('W', 3), 28, 2 }, /* QSPI0_SPCLK */
5628 { PIN_A_NUMBER('C', 5), 24, 2 }, /* QSPI0_MOSI_IO0 */
5629 { PIN_A_NUMBER('B', 4), 20, 2 }, /* QSPI0_MISO_IO1 */
5630 { PIN_NUMBER('Y', 6), 16, 2 }, /* QSPI0_IO2 */
5631 { PIN_A_NUMBER('B', 6), 12, 2 }, /* QSPI0_IO3 */
5632 { PIN_NUMBER('Y', 3), 8, 2 }, /* QSPI0_SSL */
5633 { PIN_NUMBER('V', 3), 4, 2 }, /* QSPI1_SPCLK */
5634 { PIN_A_NUMBER('C', 7), 0, 2 }, /* QSPI1_MOSI_IO0 */
5635 } },
5636 { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
5637 { PIN_A_NUMBER('E', 5), 28, 2 }, /* QSPI1_MISO_IO1 */
5638 { PIN_A_NUMBER('E', 4), 24, 2 }, /* QSPI1_IO2 */
5639 { PIN_A_NUMBER('C', 3), 20, 2 }, /* QSPI1_IO3 */
5640 { PIN_NUMBER('V', 5), 16, 2 }, /* QSPI1_SSL */
5641 { PIN_NUMBER('Y', 7), 12, 2 }, /* RPC_INT# */
5642 { PIN_NUMBER('V', 6), 8, 2 }, /* RPC_WP# */
5643 { PIN_NUMBER('V', 7), 4, 2 }, /* RPC_RESET# */
5644 { PIN_NUMBER('A', 16), 0, 3 }, /* AVB_RX_CTL */
5645 } },
5646 { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
5647 { PIN_NUMBER('B', 19), 28, 3 }, /* AVB_RXC */
5648 { PIN_NUMBER('A', 13), 24, 3 }, /* AVB_RD0 */
5649 { PIN_NUMBER('B', 13), 20, 3 }, /* AVB_RD1 */
5650 { PIN_NUMBER('A', 14), 16, 3 }, /* AVB_RD2 */
5651 { PIN_NUMBER('B', 14), 12, 3 }, /* AVB_RD3 */
5652 { PIN_NUMBER('A', 8), 8, 3 }, /* AVB_TX_CTL */
5653 { PIN_NUMBER('A', 19), 4, 3 }, /* AVB_TXC */
5654 { PIN_NUMBER('A', 18), 0, 3 }, /* AVB_TD0 */
5655 } },
5656 { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
5657 { PIN_NUMBER('B', 18), 28, 3 }, /* AVB_TD1 */
5658 { PIN_NUMBER('A', 17), 24, 3 }, /* AVB_TD2 */
5659 { PIN_NUMBER('B', 17), 20, 3 }, /* AVB_TD3 */
5660 { PIN_NUMBER('A', 12), 16, 3 }, /* AVB_TXCREFCLK */
5661 { PIN_NUMBER('A', 9), 12, 3 }, /* AVB_MDIO */
5662 { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
5663 { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
5664 { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
5665 } },
5666 { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
5667 { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */
5668 { RCAR_GP_PIN(2, 13), 24, 3 }, /* AVB_AVTP_MATCH */
5669 { RCAR_GP_PIN(2, 14), 20, 3 }, /* AVB_AVTP_CAPTURE */
5670 { RCAR_GP_PIN(2, 0), 16, 3 }, /* IRQ0 */
5671 { RCAR_GP_PIN(2, 1), 12, 3 }, /* IRQ1 */
5672 { RCAR_GP_PIN(2, 2), 8, 3 }, /* IRQ2 */
5673 { RCAR_GP_PIN(2, 3), 4, 3 }, /* IRQ3 */
5674 { RCAR_GP_PIN(2, 4), 0, 3 }, /* IRQ4 */
5675 } },
5676 { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) {
5677 { RCAR_GP_PIN(2, 5), 28, 3 }, /* IRQ5 */
5678 { RCAR_GP_PIN(2, 6), 24, 3 }, /* PWM0 */
5679 { RCAR_GP_PIN(2, 7), 20, 3 }, /* PWM1 */
5680 { RCAR_GP_PIN(2, 8), 16, 3 }, /* PWM2 */
5681 { RCAR_GP_PIN(1, 0), 12, 3 }, /* A0 */
5682 { RCAR_GP_PIN(1, 1), 8, 3 }, /* A1 */
5683 { RCAR_GP_PIN(1, 2), 4, 3 }, /* A2 */
5684 { RCAR_GP_PIN(1, 3), 0, 3 }, /* A3 */
5685 } },
5686 { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) {
5687 { RCAR_GP_PIN(1, 4), 28, 3 }, /* A4 */
5688 { RCAR_GP_PIN(1, 5), 24, 3 }, /* A5 */
5689 { RCAR_GP_PIN(1, 6), 20, 3 }, /* A6 */
5690 { RCAR_GP_PIN(1, 7), 16, 3 }, /* A7 */
5691 { RCAR_GP_PIN(1, 8), 12, 3 }, /* A8 */
5692 { RCAR_GP_PIN(1, 9), 8, 3 }, /* A9 */
5693 { RCAR_GP_PIN(1, 10), 4, 3 }, /* A10 */
5694 { RCAR_GP_PIN(1, 11), 0, 3 }, /* A11 */
5695 } },
5696 { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) {
5697 { RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */
5698 { RCAR_GP_PIN(1, 13), 24, 3 }, /* A13 */
5699 { RCAR_GP_PIN(1, 14), 20, 3 }, /* A14 */
5700 { RCAR_GP_PIN(1, 15), 16, 3 }, /* A15 */
5701 { RCAR_GP_PIN(1, 16), 12, 3 }, /* A16 */
5702 { RCAR_GP_PIN(1, 17), 8, 3 }, /* A17 */
5703 { RCAR_GP_PIN(1, 18), 4, 3 }, /* A18 */
5704 { RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */
5705 } },
5706 { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5707 { RCAR_GP_PIN(1, 28), 28, 3 }, /* CLKOUT */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5708 { RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */
5709 { RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */
5710 { RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */
5711 { RCAR_GP_PIN(1, 23), 12, 3 }, /* RD */
5712 { RCAR_GP_PIN(1, 24), 8, 3 }, /* RD_WR */
5713 { RCAR_GP_PIN(1, 25), 4, 3 }, /* WE0 */
5714 { RCAR_GP_PIN(1, 26), 0, 3 }, /* WE1 */
5715 } },
5716 { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
5717 { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */
5718 { PIN_NUMBER('C', 1), 24, 3 }, /* PRESETOUT# */
5719 { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */
5720 { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */
5721 { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */
5722 { RCAR_GP_PIN(0, 3), 8, 3 }, /* D3 */
5723 { RCAR_GP_PIN(0, 4), 4, 3 }, /* D4 */
5724 { RCAR_GP_PIN(0, 5), 0, 3 }, /* D5 */
5725 } },
5726 { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
5727 { RCAR_GP_PIN(0, 6), 28, 3 }, /* D6 */
5728 { RCAR_GP_PIN(0, 7), 24, 3 }, /* D7 */
5729 { RCAR_GP_PIN(0, 8), 20, 3 }, /* D8 */
5730 { RCAR_GP_PIN(0, 9), 16, 3 }, /* D9 */
5731 { RCAR_GP_PIN(0, 10), 12, 3 }, /* D10 */
5732 { RCAR_GP_PIN(0, 11), 8, 3 }, /* D11 */
5733 { RCAR_GP_PIN(0, 12), 4, 3 }, /* D12 */
5734 { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */
5735 } },
5736 { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
5737 { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
5738 { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
5739 { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
5740 { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5741 { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */
5742 { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5743 { PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */
5744 { PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */
5745 } },
5746 { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
5747 { PIN_A_NUMBER('R', 7), 28, 2 }, /* DU_DOTCLKIN2 */
5748 { PIN_A_NUMBER('R', 8), 24, 2 }, /* DU_DOTCLKIN3 */
5749 { PIN_A_NUMBER('D', 38), 20, 2 }, /* FSCLKST# */
5750 { PIN_A_NUMBER('R', 30), 4, 2 }, /* TMS */
5751 } },
5752 { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
5753 { PIN_A_NUMBER('T', 28), 28, 2 }, /* TDO */
5754 { PIN_A_NUMBER('T', 30), 24, 2 }, /* ASEBRK */
5755 { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
5756 { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
5757 { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
5758 { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
5759 { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
5760 { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
5761 } },
5762 { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
5763 { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */
5764 { RCAR_GP_PIN(3, 7), 24, 3 }, /* SD1_CMD */
5765 { RCAR_GP_PIN(3, 8), 20, 3 }, /* SD1_DAT0 */
5766 { RCAR_GP_PIN(3, 9), 16, 3 }, /* SD1_DAT1 */
5767 { RCAR_GP_PIN(3, 10), 12, 3 }, /* SD1_DAT2 */
5768 { RCAR_GP_PIN(3, 11), 8, 3 }, /* SD1_DAT3 */
5769 { RCAR_GP_PIN(4, 0), 4, 3 }, /* SD2_CLK */
5770 { RCAR_GP_PIN(4, 1), 0, 3 }, /* SD2_CMD */
5771 } },
5772 { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) {
5773 { RCAR_GP_PIN(4, 2), 28, 3 }, /* SD2_DAT0 */
5774 { RCAR_GP_PIN(4, 3), 24, 3 }, /* SD2_DAT1 */
5775 { RCAR_GP_PIN(4, 4), 20, 3 }, /* SD2_DAT2 */
5776 { RCAR_GP_PIN(4, 5), 16, 3 }, /* SD2_DAT3 */
5777 { RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */
5778 { RCAR_GP_PIN(4, 7), 8, 3 }, /* SD3_CLK */
5779 { RCAR_GP_PIN(4, 8), 4, 3 }, /* SD3_CMD */
5780 { RCAR_GP_PIN(4, 9), 0, 3 }, /* SD3_DAT0 */
5781 } },
5782 { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) {
5783 { RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */
5784 { RCAR_GP_PIN(4, 11), 24, 3 }, /* SD3_DAT2 */
5785 { RCAR_GP_PIN(4, 12), 20, 3 }, /* SD3_DAT3 */
5786 { RCAR_GP_PIN(4, 13), 16, 3 }, /* SD3_DAT4 */
5787 { RCAR_GP_PIN(4, 14), 12, 3 }, /* SD3_DAT5 */
5788 { RCAR_GP_PIN(4, 15), 8, 3 }, /* SD3_DAT6 */
5789 { RCAR_GP_PIN(4, 16), 4, 3 }, /* SD3_DAT7 */
5790 { RCAR_GP_PIN(4, 17), 0, 3 }, /* SD3_DS */
5791 } },
5792 { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) {
5793 { RCAR_GP_PIN(3, 12), 28, 3 }, /* SD0_CD */
5794 { RCAR_GP_PIN(3, 13), 24, 3 }, /* SD0_WP */
5795 { RCAR_GP_PIN(3, 14), 20, 3 }, /* SD1_CD */
5796 { RCAR_GP_PIN(3, 15), 16, 3 }, /* SD1_WP */
5797 { RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */
5798 { RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */
5799 { RCAR_GP_PIN(5, 2), 4, 3 }, /* TX0 */
5800 { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */
5801 } },
5802 { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5803 { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0 */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5804 { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */
5805 { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */
5806 { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5807 { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1 */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5808 { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */
5809 { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */
5810 { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */
5811 } },
5812 { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) {
5813 { RCAR_GP_PIN(5, 12), 28, 3 }, /* HSCK0 */
5814 { RCAR_GP_PIN(5, 13), 24, 3 }, /* HRX0 */
5815 { RCAR_GP_PIN(5, 14), 20, 3 }, /* HTX0 */
5816 { RCAR_GP_PIN(5, 15), 16, 3 }, /* HCTS0 */
5817 { RCAR_GP_PIN(5, 16), 12, 3 }, /* HRTS0 */
5818 { RCAR_GP_PIN(5, 17), 8, 3 }, /* MSIOF0_SCK */
5819 { RCAR_GP_PIN(5, 18), 4, 3 }, /* MSIOF0_SYNC */
5820 { RCAR_GP_PIN(5, 19), 0, 3 }, /* MSIOF0_SS1 */
5821 } },
5822 { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) {
5823 { RCAR_GP_PIN(5, 20), 28, 3 }, /* MSIOF0_TXD */
5824 { RCAR_GP_PIN(5, 21), 24, 3 }, /* MSIOF0_SS2 */
5825 { RCAR_GP_PIN(5, 22), 20, 3 }, /* MSIOF0_RXD */
5826 { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */
5827 { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */
5828 { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */
5829 { PIN_NUMBER('H', 37), 4, 3 }, /* MLB_REF */
5830 { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */
5831 } },
5832 { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
5833 { RCAR_GP_PIN(6, 1), 28, 3 }, /* SSI_WS01239 */
5834 { RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */
5835 { RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */
5836 { RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */
5837 { RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK349 */
5838 { RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS349 */
5839 { RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */
5840 { RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */
5841 } },
5842 { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) {
5843 { RCAR_GP_PIN(6, 9), 28, 3 }, /* SSI_WS4 */
5844 { RCAR_GP_PIN(6, 10), 24, 3 }, /* SSI_SDATA4 */
5845 { RCAR_GP_PIN(6, 11), 20, 3 }, /* SSI_SCK5 */
5846 { RCAR_GP_PIN(6, 12), 16, 3 }, /* SSI_WS5 */
5847 { RCAR_GP_PIN(6, 13), 12, 3 }, /* SSI_SDATA5 */
5848 { RCAR_GP_PIN(6, 14), 8, 3 }, /* SSI_SCK6 */
5849 { RCAR_GP_PIN(6, 15), 4, 3 }, /* SSI_WS6 */
5850 { RCAR_GP_PIN(6, 16), 0, 3 }, /* SSI_SDATA6 */
5851 } },
5852 { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) {
5853 { RCAR_GP_PIN(6, 17), 28, 3 }, /* SSI_SCK78 */
5854 { RCAR_GP_PIN(6, 18), 24, 3 }, /* SSI_WS78 */
5855 { RCAR_GP_PIN(6, 19), 20, 3 }, /* SSI_SDATA7 */
5856 { RCAR_GP_PIN(6, 20), 16, 3 }, /* SSI_SDATA8 */
5857 { RCAR_GP_PIN(6, 21), 12, 3 }, /* SSI_SDATA9 */
5858 { RCAR_GP_PIN(6, 22), 8, 3 }, /* AUDIO_CLKA */
5859 { RCAR_GP_PIN(6, 23), 4, 3 }, /* AUDIO_CLKB */
5860 { RCAR_GP_PIN(6, 24), 0, 3 }, /* USB0_PWEN */
5861 } },
5862 { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) {
5863 { RCAR_GP_PIN(6, 25), 28, 3 }, /* USB0_OVC */
5864 { RCAR_GP_PIN(6, 26), 24, 3 }, /* USB1_PWEN */
5865 { RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */
5866 { RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */
5867 { RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */
5868 { RCAR_GP_PIN(6, 30), 8, 3 }, /* USB2_CH3_PWEN */
5869 { RCAR_GP_PIN(6, 31), 4, 3 }, /* USB2_CH3_OVC */
5870 } },
5871 { },
5872};
5873
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5874enum ioctrl_regs {
5875 POCCTRL,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5876 TDSELCTRL,
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5877};
5878
5879static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
5880 [POCCTRL] = { 0xe6060380, },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5881 [TDSELCTRL] = { 0xe60603c0, },
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5882 { /* sentinel */ },
5883};
5884
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5885static int r8a7795_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
5886{
5887 int bit = -EINVAL;
5888
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5889 *pocctrl = pinmux_ioctrl_regs[POCCTRL].reg;
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5890
5891 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
5892 bit = pin & 0x1f;
5893
5894 if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
5895 bit = (pin & 0x1f) + 12;
5896
5897 return bit;
5898}
5899
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5900static const struct pinmux_bias_reg pinmux_bias_regs[] = {
5901 { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
5902 [ 0] = PIN_NUMBER('W', 3), /* QSPI0_SPCLK */
5903 [ 1] = PIN_A_NUMBER('C', 5), /* QSPI0_MOSI_IO0 */
5904 [ 2] = PIN_A_NUMBER('B', 4), /* QSPI0_MISO_IO1 */
5905 [ 3] = PIN_NUMBER('Y', 6), /* QSPI0_IO2 */
5906 [ 4] = PIN_A_NUMBER('B', 6), /* QSPI0_IO3 */
5907 [ 5] = PIN_NUMBER('Y', 3), /* QSPI0_SSL */
5908 [ 6] = PIN_NUMBER('V', 3), /* QSPI1_SPCLK */
5909 [ 7] = PIN_A_NUMBER('C', 7), /* QSPI1_MOSI_IO0 */
5910 [ 8] = PIN_A_NUMBER('E', 5), /* QSPI1_MISO_IO1 */
5911 [ 9] = PIN_A_NUMBER('E', 4), /* QSPI1_IO2 */
5912 [10] = PIN_A_NUMBER('C', 3), /* QSPI1_IO3 */
5913 [11] = PIN_NUMBER('V', 5), /* QSPI1_SSL */
5914 [12] = PIN_NUMBER('Y', 7), /* RPC_INT# */
5915 [13] = PIN_NUMBER('V', 6), /* RPC_WP# */
5916 [14] = PIN_NUMBER('V', 7), /* RPC_RESET# */
5917 [15] = PIN_NUMBER('A', 16), /* AVB_RX_CTL */
5918 [16] = PIN_NUMBER('B', 19), /* AVB_RXC */
5919 [17] = PIN_NUMBER('A', 13), /* AVB_RD0 */
5920 [18] = PIN_NUMBER('B', 13), /* AVB_RD1 */
5921 [19] = PIN_NUMBER('A', 14), /* AVB_RD2 */
5922 [20] = PIN_NUMBER('B', 14), /* AVB_RD3 */
5923 [21] = PIN_NUMBER('A', 8), /* AVB_TX_CTL */
5924 [22] = PIN_NUMBER('A', 19), /* AVB_TXC */
5925 [23] = PIN_NUMBER('A', 18), /* AVB_TD0 */
5926 [24] = PIN_NUMBER('B', 18), /* AVB_TD1 */
5927 [25] = PIN_NUMBER('A', 17), /* AVB_TD2 */
5928 [26] = PIN_NUMBER('B', 17), /* AVB_TD3 */
5929 [27] = PIN_NUMBER('A', 12), /* AVB_TXCREFCLK */
5930 [28] = PIN_NUMBER('A', 9), /* AVB_MDIO */
5931 [29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */
5932 [30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */
5933 [31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */
5934 } },
5935 { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
5936 [ 0] = RCAR_GP_PIN(2, 12), /* AVB_LINK */
5937 [ 1] = RCAR_GP_PIN(2, 13), /* AVB_AVTP_MATCH_A */
5938 [ 2] = RCAR_GP_PIN(2, 14), /* AVB_AVTP_CAPTURE_A */
5939 [ 3] = RCAR_GP_PIN(2, 0), /* IRQ0 */
5940 [ 4] = RCAR_GP_PIN(2, 1), /* IRQ1 */
5941 [ 5] = RCAR_GP_PIN(2, 2), /* IRQ2 */
5942 [ 6] = RCAR_GP_PIN(2, 3), /* IRQ3 */
5943 [ 7] = RCAR_GP_PIN(2, 4), /* IRQ4 */
5944 [ 8] = RCAR_GP_PIN(2, 5), /* IRQ5 */
5945 [ 9] = RCAR_GP_PIN(2, 6), /* PWM0 */
5946 [10] = RCAR_GP_PIN(2, 7), /* PWM1_A */
5947 [11] = RCAR_GP_PIN(2, 8), /* PWM2_A */
5948 [12] = RCAR_GP_PIN(1, 0), /* A0 */
5949 [13] = RCAR_GP_PIN(1, 1), /* A1 */
5950 [14] = RCAR_GP_PIN(1, 2), /* A2 */
5951 [15] = RCAR_GP_PIN(1, 3), /* A3 */
5952 [16] = RCAR_GP_PIN(1, 4), /* A4 */
5953 [17] = RCAR_GP_PIN(1, 5), /* A5 */
5954 [18] = RCAR_GP_PIN(1, 6), /* A6 */
5955 [19] = RCAR_GP_PIN(1, 7), /* A7 */
5956 [20] = RCAR_GP_PIN(1, 8), /* A8 */
5957 [21] = RCAR_GP_PIN(1, 9), /* A9 */
5958 [22] = RCAR_GP_PIN(1, 10), /* A10 */
5959 [23] = RCAR_GP_PIN(1, 11), /* A11 */
5960 [24] = RCAR_GP_PIN(1, 12), /* A12 */
5961 [25] = RCAR_GP_PIN(1, 13), /* A13 */
5962 [26] = RCAR_GP_PIN(1, 14), /* A14 */
5963 [27] = RCAR_GP_PIN(1, 15), /* A15 */
5964 [28] = RCAR_GP_PIN(1, 16), /* A16 */
5965 [29] = RCAR_GP_PIN(1, 17), /* A17 */
5966 [30] = RCAR_GP_PIN(1, 18), /* A18 */
5967 [31] = RCAR_GP_PIN(1, 19), /* A19 */
5968 } },
5969 { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
5970 [ 0] = RCAR_GP_PIN(1, 28), /* CLKOUT */
5971 [ 1] = RCAR_GP_PIN(1, 20), /* CS0_N */
5972 [ 2] = RCAR_GP_PIN(1, 21), /* CS1_N */
5973 [ 3] = RCAR_GP_PIN(1, 22), /* BS_N */
5974 [ 4] = RCAR_GP_PIN(1, 23), /* RD_N */
5975 [ 5] = RCAR_GP_PIN(1, 24), /* RD_WR_N */
5976 [ 6] = RCAR_GP_PIN(1, 25), /* WE0_N */
5977 [ 7] = RCAR_GP_PIN(1, 26), /* WE1_N */
5978 [ 8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */
5979 [ 9] = PIN_NUMBER('C', 1), /* PRESETOUT# */
5980 [10] = RCAR_GP_PIN(0, 0), /* D0 */
5981 [11] = RCAR_GP_PIN(0, 1), /* D1 */
5982 [12] = RCAR_GP_PIN(0, 2), /* D2 */
5983 [13] = RCAR_GP_PIN(0, 3), /* D3 */
5984 [14] = RCAR_GP_PIN(0, 4), /* D4 */
5985 [15] = RCAR_GP_PIN(0, 5), /* D5 */
5986 [16] = RCAR_GP_PIN(0, 6), /* D6 */
5987 [17] = RCAR_GP_PIN(0, 7), /* D7 */
5988 [18] = RCAR_GP_PIN(0, 8), /* D8 */
5989 [19] = RCAR_GP_PIN(0, 9), /* D9 */
5990 [20] = RCAR_GP_PIN(0, 10), /* D10 */
5991 [21] = RCAR_GP_PIN(0, 11), /* D11 */
5992 [22] = RCAR_GP_PIN(0, 12), /* D12 */
5993 [23] = RCAR_GP_PIN(0, 13), /* D13 */
5994 [24] = RCAR_GP_PIN(0, 14), /* D14 */
5995 [25] = RCAR_GP_PIN(0, 15), /* D15 */
5996 [26] = RCAR_GP_PIN(7, 0), /* AVS1 */
5997 [27] = RCAR_GP_PIN(7, 1), /* AVS2 */
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5998 [28] = RCAR_GP_PIN(7, 2), /* GP7_02 */
5999 [29] = RCAR_GP_PIN(7, 3), /* GP7_03 */
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]6000 [30] = PIN_A_NUMBER('P', 7), /* DU_DOTCLKIN0 */
6001 [31] = PIN_A_NUMBER('P', 8), /* DU_DOTCLKIN1 */
6002 } },
6003 { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
6004 [ 0] = PIN_A_NUMBER('R', 7), /* DU_DOTCLKIN2 */
6005 [ 1] = PIN_A_NUMBER('R', 8), /* DU_DOTCLKIN3 */
6006 [ 2] = PIN_A_NUMBER('D', 38), /* FSCLKST# */
6007 [ 3] = PIN_A_NUMBER('D', 39), /* EXTALR*/
6008 [ 4] = PIN_A_NUMBER('R', 26), /* TRST# */
6009 [ 5] = PIN_A_NUMBER('T', 27), /* TCK */
6010 [ 6] = PIN_A_NUMBER('R', 30), /* TMS */
6011 [ 7] = PIN_A_NUMBER('R', 29), /* TDI */
6012 [ 8] = PIN_NONE,
6013 [ 9] = PIN_A_NUMBER('T', 30), /* ASEBRK */
6014 [10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */
6015 [11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */
6016 [12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */
6017 [13] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */
6018 [14] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */
6019 [15] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */
6020 [16] = RCAR_GP_PIN(3, 6), /* SD1_CLK */
6021 [17] = RCAR_GP_PIN(3, 7), /* SD1_CMD */
6022 [18] = RCAR_GP_PIN(3, 8), /* SD1_DAT0 */
6023 [19] = RCAR_GP_PIN(3, 9), /* SD1_DAT1 */
6024 [20] = RCAR_GP_PIN(3, 10), /* SD1_DAT2 */
6025 [21] = RCAR_GP_PIN(3, 11), /* SD1_DAT3 */
6026 [22] = RCAR_GP_PIN(4, 0), /* SD2_CLK */
6027 [23] = RCAR_GP_PIN(4, 1), /* SD2_CMD */
6028 [24] = RCAR_GP_PIN(4, 2), /* SD2_DAT0 */
6029 [25] = RCAR_GP_PIN(4, 3), /* SD2_DAT1 */
6030 [26] = RCAR_GP_PIN(4, 4), /* SD2_DAT2 */
6031 [27] = RCAR_GP_PIN(4, 5), /* SD2_DAT3 */
6032 [28] = RCAR_GP_PIN(4, 6), /* SD2_DS */
6033 [29] = RCAR_GP_PIN(4, 7), /* SD3_CLK */
6034 [30] = RCAR_GP_PIN(4, 8), /* SD3_CMD */
6035 [31] = RCAR_GP_PIN(4, 9), /* SD3_DAT0 */
6036 } },
6037 { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
6038 [ 0] = RCAR_GP_PIN(4, 10), /* SD3_DAT1 */
6039 [ 1] = RCAR_GP_PIN(4, 11), /* SD3_DAT2 */
6040 [ 2] = RCAR_GP_PIN(4, 12), /* SD3_DAT3 */
6041 [ 3] = RCAR_GP_PIN(4, 13), /* SD3_DAT4 */
6042 [ 4] = RCAR_GP_PIN(4, 14), /* SD3_DAT5 */
6043 [ 5] = RCAR_GP_PIN(4, 15), /* SD3_DAT6 */
6044 [ 6] = RCAR_GP_PIN(4, 16), /* SD3_DAT7 */
6045 [ 7] = RCAR_GP_PIN(4, 17), /* SD3_DS */
6046 [ 8] = RCAR_GP_PIN(3, 12), /* SD0_CD */
6047 [ 9] = RCAR_GP_PIN(3, 13), /* SD0_WP */
6048 [10] = RCAR_GP_PIN(3, 14), /* SD1_CD */
6049 [11] = RCAR_GP_PIN(3, 15), /* SD1_WP */
6050 [12] = RCAR_GP_PIN(5, 0), /* SCK0 */
6051 [13] = RCAR_GP_PIN(5, 1), /* RX0 */
6052 [14] = RCAR_GP_PIN(5, 2), /* TX0 */
6053 [15] = RCAR_GP_PIN(5, 3), /* CTS0_N */
6054 [16] = RCAR_GP_PIN(5, 4), /* RTS0_N */
6055 [17] = RCAR_GP_PIN(5, 5), /* RX1_A */
6056 [18] = RCAR_GP_PIN(5, 6), /* TX1_A */
6057 [19] = RCAR_GP_PIN(5, 7), /* CTS1_N */
6058 [20] = RCAR_GP_PIN(5, 8), /* RTS1_N */
6059 [21] = RCAR_GP_PIN(5, 9), /* SCK2 */
6060 [22] = RCAR_GP_PIN(5, 10), /* TX2_A */
6061 [23] = RCAR_GP_PIN(5, 11), /* RX2_A */
6062 [24] = RCAR_GP_PIN(5, 12), /* HSCK0 */
6063 [25] = RCAR_GP_PIN(5, 13), /* HRX0 */
6064 [26] = RCAR_GP_PIN(5, 14), /* HTX0 */
6065 [27] = RCAR_GP_PIN(5, 15), /* HCTS0_N */
6066 [28] = RCAR_GP_PIN(5, 16), /* HRTS0_N */
6067 [29] = RCAR_GP_PIN(5, 17), /* MSIOF0_SCK */
6068 [30] = RCAR_GP_PIN(5, 18), /* MSIOF0_SYNC */
6069 [31] = RCAR_GP_PIN(5, 19), /* MSIOF0_SS1 */
6070 } },
6071 { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
6072 [ 0] = RCAR_GP_PIN(5, 20), /* MSIOF0_TXD */
6073 [ 1] = RCAR_GP_PIN(5, 21), /* MSIOF0_SS2 */
6074 [ 2] = RCAR_GP_PIN(5, 22), /* MSIOF0_RXD */
6075 [ 3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */
6076 [ 4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */
6077 [ 5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */
6078 [ 6] = PIN_NUMBER('H', 37), /* MLB_REF */
6079 [ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */
6080 [ 8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */
6081 [ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */
6082 [10] = RCAR_GP_PIN(6, 3), /* SSI_SDATA1_A */
6083 [11] = RCAR_GP_PIN(6, 4), /* SSI_SDATA2_A */
6084 [12] = RCAR_GP_PIN(6, 5), /* SSI_SCK349 */
6085 [13] = RCAR_GP_PIN(6, 6), /* SSI_WS349 */
6086 [14] = RCAR_GP_PIN(6, 7), /* SSI_SDATA3 */
6087 [15] = RCAR_GP_PIN(6, 8), /* SSI_SCK4 */
6088 [16] = RCAR_GP_PIN(6, 9), /* SSI_WS4 */
6089 [17] = RCAR_GP_PIN(6, 10), /* SSI_SDATA4 */
6090 [18] = RCAR_GP_PIN(6, 11), /* SSI_SCK5 */
6091 [19] = RCAR_GP_PIN(6, 12), /* SSI_WS5 */
6092 [20] = RCAR_GP_PIN(6, 13), /* SSI_SDATA5 */
6093 [21] = RCAR_GP_PIN(6, 14), /* SSI_SCK6 */
6094 [22] = RCAR_GP_PIN(6, 15), /* SSI_WS6 */
6095 [23] = RCAR_GP_PIN(6, 16), /* SSI_SDATA6 */
6096 [24] = RCAR_GP_PIN(6, 17), /* SSI_SCK78 */
6097 [25] = RCAR_GP_PIN(6, 18), /* SSI_WS78 */
6098 [26] = RCAR_GP_PIN(6, 19), /* SSI_SDATA7 */
6099 [27] = RCAR_GP_PIN(6, 20), /* SSI_SDATA8 */
6100 [28] = RCAR_GP_PIN(6, 21), /* SSI_SDATA9_A */
6101 [29] = RCAR_GP_PIN(6, 22), /* AUDIO_CLKA_A */
6102 [30] = RCAR_GP_PIN(6, 23), /* AUDIO_CLKB_B */
6103 [31] = RCAR_GP_PIN(6, 24), /* USB0_PWEN */
6104 } },
6105 { PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) {
6106 [ 0] = RCAR_GP_PIN(6, 25), /* USB0_OVC */
6107 [ 1] = RCAR_GP_PIN(6, 26), /* USB1_PWEN */
6108 [ 2] = RCAR_GP_PIN(6, 27), /* USB1_OVC */
6109 [ 3] = RCAR_GP_PIN(6, 28), /* USB30_PWEN */
6110 [ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */
6111 [ 5] = RCAR_GP_PIN(6, 30), /* USB2_CH3_PWEN */
6112 [ 6] = RCAR_GP_PIN(6, 31), /* USB2_CH3_OVC */
6113 [ 7] = PIN_NONE,
6114 [ 8] = PIN_NONE,
6115 [ 9] = PIN_NONE,
6116 [10] = PIN_NONE,
6117 [11] = PIN_NONE,
6118 [12] = PIN_NONE,
6119 [13] = PIN_NONE,
6120 [14] = PIN_NONE,
6121 [15] = PIN_NONE,
6122 [16] = PIN_NONE,
6123 [17] = PIN_NONE,
6124 [18] = PIN_NONE,
6125 [19] = PIN_NONE,
6126 [20] = PIN_NONE,
6127 [21] = PIN_NONE,
6128 [22] = PIN_NONE,
6129 [23] = PIN_NONE,
6130 [24] = PIN_NONE,
6131 [25] = PIN_NONE,
6132 [26] = PIN_NONE,
6133 [27] = PIN_NONE,
6134 [28] = PIN_NONE,
6135 [29] = PIN_NONE,
6136 [30] = PIN_NONE,
6137 [31] = PIN_NONE,
6138 } },
6139 { /* sentinel */ },
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6140};
6141
6142static unsigned int r8a7795_pinmux_get_bias(struct sh_pfc *pfc,
6143 unsigned int pin)
6144{
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]6145 const struct pinmux_bias_reg *reg;
6146 unsigned int bit;
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6147
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]6148 reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
6149 if (!reg)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6150 return PIN_CONFIG_BIAS_DISABLE;
6151
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]6152 if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6153 return PIN_CONFIG_BIAS_DISABLE;
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]6154 else if (sh_pfc_read(pfc, reg->pud) & BIT(bit))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6155 return PIN_CONFIG_BIAS_PULL_UP;
6156 else
6157 return PIN_CONFIG_BIAS_PULL_DOWN;
6158}
6159
6160static void r8a7795_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
6161 unsigned int bias)
6162{
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]6163 const struct pinmux_bias_reg *reg;
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6164 u32 enable, updown;
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]6165 unsigned int bit;
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6166
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]6167 reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
6168 if (!reg)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6169 return;
6170
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]6171 enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit);
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6172 if (bias != PIN_CONFIG_BIAS_DISABLE)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]6173 enable |= BIT(bit);
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6174
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]6175 updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6176 if (bias == PIN_CONFIG_BIAS_PULL_UP)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]6177 updown |= BIT(bit);
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6178
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]6179 sh_pfc_write(pfc, reg->pud, updown);
6180 sh_pfc_write(pfc, reg->puen, enable);
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6181}
6182
6183static const struct sh_pfc_soc_operations r8a7795_pinmux_ops = {
6184 .pin_to_pocctrl = r8a7795_pin_to_pocctrl,
6185 .get_bias = r8a7795_pinmux_get_bias,
6186 .set_bias = r8a7795_pinmux_set_bias,
6187};
6188
6189const struct sh_pfc_soc_info r8a7795_pinmux_info = {
6190 .name = "r8a77951_pfc",
6191 .ops = &r8a7795_pinmux_ops,
6192 .unlock_reg = 0xe6060000, /* PMMR */
6193
6194 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6195
6196 .pins = pinmux_pins,
6197 .nr_pins = ARRAY_SIZE(pinmux_pins),
6198 .groups = pinmux_groups,
6199 .nr_groups = ARRAY_SIZE(pinmux_groups),
6200 .functions = pinmux_functions,
6201 .nr_functions = ARRAY_SIZE(pinmux_functions),
6202
6203 .cfg_regs = pinmux_config_regs,
6204 .drive_regs = pinmux_drive_regs,
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]6205 .bias_regs = pinmux_bias_regs,
6206 .ioctrl_regs = pinmux_ioctrl_regs,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6207
6208 .pinmux_data = pinmux_data,
6209 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
6210};