Tom Rini | 2467224 | 2018-06-01 21:10:18 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Marek Vasut | 2a46a0b | 2018-04-26 13:31:39 +0200 | [diff] [blame] | 2 | /* |
| 3 | * board/renesas/ebisu/ebisu.c |
| 4 | * This file is Ebisu board support. |
| 5 | * |
| 6 | * Copyright (C) 2018 Marek Vasut <marek.vasut+renesas@gmail.com> |
Marek Vasut | 2a46a0b | 2018-04-26 13:31:39 +0200 | [diff] [blame] | 7 | */ |
| 8 | |
| 9 | #include <common.h> |
Simon Glass | afb0215 | 2019-12-28 10:45:01 -0700 | [diff] [blame] | 10 | #include <cpu_func.h> |
Simon Glass | f11478f | 2019-12-28 10:45:07 -0700 | [diff] [blame] | 11 | #include <hang.h> |
Simon Glass | 9758973 | 2020-05-10 11:40:02 -0600 | [diff] [blame] | 12 | #include <init.h> |
Marek Vasut | 2a46a0b | 2018-04-26 13:31:39 +0200 | [diff] [blame] | 13 | #include <malloc.h> |
| 14 | #include <netdev.h> |
| 15 | #include <dm.h> |
| 16 | #include <dm/platform_data/serial_sh.h> |
| 17 | #include <asm/processor.h> |
| 18 | #include <asm/mach-types.h> |
| 19 | #include <asm/io.h> |
| 20 | #include <linux/errno.h> |
| 21 | #include <asm/arch/sys_proto.h> |
| 22 | #include <asm/gpio.h> |
| 23 | #include <asm/arch/gpio.h> |
| 24 | #include <asm/arch/rmobile.h> |
| 25 | #include <asm/arch/rcar-mstp.h> |
| 26 | #include <asm/arch/sh_sdhi.h> |
| 27 | #include <i2c.h> |
| 28 | #include <mmc.h> |
| 29 | |
| 30 | DECLARE_GLOBAL_DATA_PTR; |
| 31 | |
| 32 | void s_init(void) |
| 33 | { |
| 34 | } |
| 35 | |
Marek Vasut | 2a46a0b | 2018-04-26 13:31:39 +0200 | [diff] [blame] | 36 | int board_early_init_f(void) |
| 37 | { |
Marek Vasut | 2a46a0b | 2018-04-26 13:31:39 +0200 | [diff] [blame] | 38 | return 0; |
| 39 | } |
| 40 | |
| 41 | int board_init(void) |
| 42 | { |
| 43 | /* adress of boot parameters */ |
| 44 | gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000; |
| 45 | |
| 46 | return 0; |
| 47 | } |
| 48 | |
Marek Vasut | 2a46a0b | 2018-04-26 13:31:39 +0200 | [diff] [blame] | 49 | #define RST_BASE 0xE6160000 |
| 50 | #define RST_CA57RESCNT (RST_BASE + 0x40) |
| 51 | #define RST_CA53RESCNT (RST_BASE + 0x44) |
| 52 | #define RST_RSTOUTCR (RST_BASE + 0x58) |
| 53 | #define RST_CA57_CODE 0xA5A5000F |
| 54 | #define RST_CA53_CODE 0x5A5A000F |
| 55 | |
| 56 | void reset_cpu(ulong addr) |
| 57 | { |
| 58 | unsigned long midr, cputype; |
| 59 | |
| 60 | asm volatile("mrs %0, midr_el1" : "=r" (midr)); |
| 61 | cputype = (midr >> 4) & 0xfff; |
| 62 | |
| 63 | if (cputype == 0xd03) |
| 64 | writel(RST_CA53_CODE, RST_CA53RESCNT); |
| 65 | else if (cputype == 0xd07) |
| 66 | writel(RST_CA57_CODE, RST_CA57RESCNT); |
| 67 | else |
| 68 | hang(); |
| 69 | } |