blob: 9f45c48e4e0c5f561314ad314db4bd0a23c1705e [file] [log] [blame]
Simon Glassb2c1cac2014-02-26 15:59:21 -07001/dts-v1/;
2
Patrick Delaunay23aee612020-01-13 11:35:13 +01003#include <dt-bindings/gpio/gpio.h>
4#include <dt-bindings/gpio/sandbox-gpio.h>
5
Simon Glassb2c1cac2014-02-26 15:59:21 -07006/ {
7 model = "sandbox";
8 compatible = "sandbox";
9 #address-cells = <1>;
Simon Glasscf61f742015-07-06 12:54:36 -060010 #size-cells = <1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -070011
Simon Glassfef72b72014-07-23 06:55:03 -060012 aliases {
13 console = &uart0;
Simon Glass5b968632015-05-22 15:42:15 -060014 eth0 = "/eth@10002000";
Bin Meng04a11cb2015-08-27 22:25:53 -070015 eth3 = &eth_3;
Simon Glass5b968632015-05-22 15:42:15 -060016 eth5 = &eth_5;
Simon Glass5620cf82018-10-01 12:22:40 -060017 gpio1 = &gpio_a;
18 gpio2 = &gpio_b;
Patrick Delaunay28bdaa52020-01-13 11:35:14 +010019 gpio3 = &gpio_c;
Simon Glass0ccb0972015-01-25 08:27:05 -070020 i2c0 = "/i2c@0";
Simon Glasse4fef742017-04-23 20:02:07 -060021 mmc0 = "/mmc0";
22 mmc1 = "/mmc1";
Bin Meng408e5902018-08-03 01:14:41 -070023 pci0 = &pci0;
24 pci1 = &pci1;
Bin Meng510dddb2018-08-03 01:14:50 -070025 pci2 = &pci2;
Michael Walle7c41a222020-06-02 01:47:09 +020026 remoteproc0 = &rproc_1;
27 remoteproc1 = &rproc_2;
Simon Glass336b2952015-05-22 15:42:17 -060028 rtc0 = &rtc_0;
29 rtc1 = &rtc_1;
Simon Glass5b968632015-05-22 15:42:15 -060030 spi0 = "/spi@0";
Przemyslaw Marczak3dbb55e2015-05-13 13:38:34 +020031 testfdt6 = "/e-test";
Simon Glass0ccb0972015-01-25 08:27:05 -070032 testbus3 = "/some-bus";
33 testfdt0 = "/some-bus/c-test@0";
34 testfdt1 = "/some-bus/c-test@1";
35 testfdt3 = "/b-test";
36 testfdt5 = "/some-bus/c-test@5";
37 testfdt8 = "/a-test";
Eugeniu Rosca5ba71e52018-05-19 14:13:55 +020038 fdt-dummy0 = "/translation-test@8000/dev@0,0";
39 fdt-dummy1 = "/translation-test@8000/dev@1,100";
40 fdt-dummy2 = "/translation-test@8000/dev@2,200";
41 fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
Simon Glass31680482015-03-25 12:23:05 -060042 usb0 = &usb_0;
43 usb1 = &usb_1;
44 usb2 = &usb_2;
Mario Six95922152018-08-09 14:51:19 +020045 axi0 = &axi;
Mario Six02ad6fb2018-09-27 09:19:31 +020046 osd0 = "/osd";
Simon Glassfef72b72014-07-23 06:55:03 -060047 };
48
Simon Glassed96cde2018-12-10 10:37:33 -070049 audio: audio-codec {
50 compatible = "sandbox,audio-codec";
51 #sound-dai-cells = <1>;
52 };
53
Philippe Reynes1ee26482020-07-24 18:19:51 +020054 buttons {
55 compatible = "gpio-keys";
56
57 summer {
58 gpios = <&gpio_a 3 0>;
59 label = "summer";
60 };
61
62 christmas {
63 gpios = <&gpio_a 4 0>;
64 label = "christmas";
65 };
66 };
67
Simon Glassc953aaf2018-12-10 10:37:34 -070068 cros_ec: cros-ec {
Simon Glass699c9ca2018-10-01 12:22:08 -060069 reg = <0 0>;
70 compatible = "google,cros-ec-sandbox";
71
72 /*
73 * This describes the flash memory within the EC. Note
74 * that the STM32L flash erases to 0, not 0xff.
75 */
76 flash {
77 image-pos = <0x08000000>;
78 size = <0x20000>;
79 erase-value = <0>;
80
81 /* Information for sandbox */
82 ro {
83 image-pos = <0>;
84 size = <0xf000>;
85 };
86 wp-ro {
87 image-pos = <0xf000>;
88 size = <0x1000>;
89 };
90 rw {
91 image-pos = <0x10000>;
92 size = <0x10000>;
93 };
94 };
95 };
96
Yannick Fertré9712c822019-10-07 15:29:05 +020097 dsi_host: dsi_host {
98 compatible = "sandbox,dsi-host";
99 };
100
Simon Glassb2c1cac2014-02-26 15:59:21 -0700101 a-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600102 reg = <0 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700103 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600104 ping-expect = <0>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700105 ping-add = <0>;
Simon Glassfef72b72014-07-23 06:55:03 -0600106 u-boot,dm-pre-reloc;
Patrick Delaunay23aee612020-01-13 11:35:13 +0100107 test-gpios = <&gpio_a 1>, <&gpio_a 4>,
108 <&gpio_b 5 GPIO_ACTIVE_HIGH 3 2 1>,
Simon Glass16e10402015-01-05 20:05:29 -0700109 <0>, <&gpio_a 12>;
Patrick Delaunay23aee612020-01-13 11:35:13 +0100110 test2-gpios = <&gpio_a 1>, <&gpio_a 4>,
111 <&gpio_b 6 GPIO_ACTIVE_LOW 3 2 1>,
112 <&gpio_b 7 GPIO_IN 3 2 1>,
113 <&gpio_b 8 GPIO_OUT 3 2 1>,
114 <&gpio_b 9 (GPIO_OUT|GPIO_OUT_ACTIVE) 3 2 1>;
Patrick Delaunay28bdaa52020-01-13 11:35:14 +0100115 test3-gpios =
116 <&gpio_c 0 (GPIO_OUT|GPIO_OPEN_DRAIN)>,
117 <&gpio_c 1 (GPIO_OUT|GPIO_OPEN_SOURCE)>,
118 <&gpio_c 2 GPIO_OUT>,
119 <&gpio_c 3 (GPIO_IN|GPIO_PULL_UP)>,
120 <&gpio_c 4 (GPIO_IN|GPIO_PULL_DOWN)>,
Neil Armstrong643778b2020-05-05 10:43:18 +0200121 <&gpio_c 5 GPIO_IN>,
122 <&gpio_c 6 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_DRAIN)>,
123 <&gpio_c 7 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_SOURCE)>;
Simon Glass6df01f92018-12-10 10:37:37 -0700124 int-value = <1234>;
125 uint-value = <(-1234)>;
Dario Binacchi421e81e2020-03-29 18:04:40 +0200126 int64-value = /bits/ 64 <0x1111222233334444>;
Dario Binacchi81d80b52020-03-29 18:04:41 +0200127 int-array = <5678 9123 4567>;
Simon Glassdd0ed902020-07-07 13:11:58 -0600128 str-value = "test string";
Simon Glass515dcff2020-02-06 09:55:00 -0700129 interrupts-extended = <&irq 3 0>;
Simon Glass09642392020-07-07 13:12:11 -0600130 acpi,name = "GHIJ";
Simon Glassb2c1cac2014-02-26 15:59:21 -0700131 };
132
133 junk {
Simon Glasscf61f742015-07-06 12:54:36 -0600134 reg = <1 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700135 compatible = "not,compatible";
136 };
137
138 no-compatible {
Simon Glasscf61f742015-07-06 12:54:36 -0600139 reg = <2 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700140 };
141
Simon Glass5620cf82018-10-01 12:22:40 -0600142 backlight: backlight {
143 compatible = "pwm-backlight";
144 enable-gpios = <&gpio_a 1>;
145 power-supply = <&ldo_1>;
146 pwms = <&pwm 0 1000>;
147 default-brightness-level = <5>;
148 brightness-levels = <0 16 32 64 128 170 202 234 255>;
149 };
150
Jean-Jacques Hiblote83a31b2018-08-09 16:17:46 +0200151 bind-test {
Patrice Chotard7b7f9392020-07-28 09:13:33 +0200152 compatible = "simple-bus";
Jean-Jacques Hiblote83a31b2018-08-09 16:17:46 +0200153 bind-test-child1 {
154 compatible = "sandbox,phy";
155 #phy-cells = <1>;
156 };
157
158 bind-test-child2 {
159 compatible = "simple-bus";
160 };
161 };
162
Simon Glassb2c1cac2014-02-26 15:59:21 -0700163 b-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600164 reg = <3 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700165 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600166 ping-expect = <3>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700167 ping-add = <3>;
168 };
169
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200170 phy_provider0: gen_phy@0 {
171 compatible = "sandbox,phy";
172 #phy-cells = <1>;
173 };
174
175 phy_provider1: gen_phy@1 {
176 compatible = "sandbox,phy";
177 #phy-cells = <0>;
178 broken;
179 };
180
developer71092972020-05-02 11:35:12 +0200181 phy_provider2: gen_phy@2 {
182 compatible = "sandbox,phy";
183 #phy-cells = <0>;
184 };
185
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200186 gen_phy_user: gen_phy_user {
187 compatible = "simple-bus";
188 phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
189 phy-names = "phy1", "phy2", "phy3";
190 };
191
developer71092972020-05-02 11:35:12 +0200192 gen_phy_user1: gen_phy_user1 {
193 compatible = "simple-bus";
194 phys = <&phy_provider0 0>, <&phy_provider2>;
195 phy-names = "phy1", "phy2";
196 };
197
Simon Glassb2c1cac2014-02-26 15:59:21 -0700198 some-bus {
199 #address-cells = <1>;
200 #size-cells = <0>;
Simon Glass40717422014-07-23 06:55:18 -0600201 compatible = "denx,u-boot-test-bus";
Simon Glasscf61f742015-07-06 12:54:36 -0600202 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600203 ping-expect = <4>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700204 ping-add = <4>;
Simon Glass40717422014-07-23 06:55:18 -0600205 c-test@5 {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700206 compatible = "denx,u-boot-fdt-test";
207 reg = <5>;
Simon Glass40717422014-07-23 06:55:18 -0600208 ping-expect = <5>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700209 ping-add = <5>;
210 };
Simon Glass40717422014-07-23 06:55:18 -0600211 c-test@0 {
212 compatible = "denx,u-boot-fdt-test";
213 reg = <0>;
214 ping-expect = <6>;
215 ping-add = <6>;
216 };
217 c-test@1 {
218 compatible = "denx,u-boot-fdt-test";
219 reg = <1>;
220 ping-expect = <7>;
221 ping-add = <7>;
222 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700223 };
224
225 d-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600226 reg = <3 1>;
Simon Glassdb6f0202014-07-23 06:55:12 -0600227 ping-expect = <6>;
228 ping-add = <6>;
229 compatible = "google,another-fdt-test";
230 };
231
232 e-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600233 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600234 ping-expect = <6>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700235 ping-add = <6>;
236 compatible = "google,another-fdt-test";
237 };
238
Simon Glass0ccb0972015-01-25 08:27:05 -0700239 f-test {
240 compatible = "denx,u-boot-fdt-test";
241 };
242
243 g-test {
244 compatible = "denx,u-boot-fdt-test";
245 };
246
Bin Mengd9d24782018-10-10 22:07:01 -0700247 h-test {
248 compatible = "denx,u-boot-fdt-test1";
249 };
250
developercf8bc132020-05-02 11:35:10 +0200251 i-test {
252 compatible = "mediatek,u-boot-fdt-test";
253 #address-cells = <1>;
254 #size-cells = <0>;
255
256 subnode@0 {
257 reg = <0>;
258 };
259
260 subnode@1 {
261 reg = <1>;
262 };
263
264 subnode@2 {
265 reg = <2>;
266 };
267 };
268
Simon Glass204675c2019-12-29 21:19:25 -0700269 devres-test {
270 compatible = "denx,u-boot-devres-test";
271 };
272
Simon Glass3c601b12020-07-07 13:12:06 -0600273 acpi_test1: acpi-test {
Simon Glass2d67fdf2020-04-08 16:57:34 -0600274 compatible = "denx,u-boot-acpi-test";
Simon Glassd43e0ba2020-07-07 13:12:03 -0600275 acpi-ssdt-test-data = "ab";
Simon Glass990cd5b2020-07-07 13:12:08 -0600276 acpi-dsdt-test-data = "hi";
Simon Glassebb2e832020-07-07 13:11:39 -0600277 child {
278 compatible = "denx,u-boot-acpi-test";
279 };
Simon Glass2d67fdf2020-04-08 16:57:34 -0600280 };
281
Simon Glass3c601b12020-07-07 13:12:06 -0600282 acpi_test2: acpi-test2 {
Simon Glass17968c32020-04-26 09:19:46 -0600283 compatible = "denx,u-boot-acpi-test";
Simon Glassd43e0ba2020-07-07 13:12:03 -0600284 acpi-ssdt-test-data = "cd";
Simon Glass990cd5b2020-07-07 13:12:08 -0600285 acpi-dsdt-test-data = "jk";
Simon Glass17968c32020-04-26 09:19:46 -0600286 };
287
Patrice Chotard9cc2d142017-09-04 14:55:57 +0200288 clocks {
289 clk_fixed: clk-fixed {
290 compatible = "fixed-clock";
291 #clock-cells = <0>;
292 clock-frequency = <1234>;
293 };
Anup Patel8d28c3c2019-02-25 08:14:55 +0000294
295 clk_fixed_factor: clk-fixed-factor {
296 compatible = "fixed-factor-clock";
297 #clock-cells = <0>;
298 clock-div = <3>;
299 clock-mult = <2>;
300 clocks = <&clk_fixed>;
301 };
Lukasz Majewskiccafcdd2019-06-24 15:50:47 +0200302
303 osc {
304 compatible = "fixed-clock";
305 #clock-cells = <0>;
306 clock-frequency = <20000000>;
307 };
Stephen Warrena9622432016-06-17 09:44:00 -0600308 };
309
310 clk_sandbox: clk-sbox {
Simon Glass8cc4d822015-07-06 12:54:24 -0600311 compatible = "sandbox,clk";
Stephen Warrena9622432016-06-17 09:44:00 -0600312 #clock-cells = <1>;
Jean-Jacques Hiblotc1e9c942019-10-22 14:00:07 +0200313 assigned-clocks = <&clk_sandbox 3>;
314 assigned-clock-rates = <321>;
Stephen Warrena9622432016-06-17 09:44:00 -0600315 };
316
317 clk-test {
318 compatible = "sandbox,clk-test";
319 clocks = <&clk_fixed>,
320 <&clk_sandbox 1>,
Jean-Jacques Hiblot98e84182019-10-22 14:00:05 +0200321 <&clk_sandbox 0>,
322 <&clk_sandbox 3>,
323 <&clk_sandbox 2>;
324 clock-names = "fixed", "i2c", "spi", "uart2", "uart1";
Simon Glass8cc4d822015-07-06 12:54:24 -0600325 };
326
Lukasz Majewski8c0709b2019-06-24 15:50:50 +0200327 ccf: clk-ccf {
328 compatible = "sandbox,clk-ccf";
329 };
330
Simon Glass5b968632015-05-22 15:42:15 -0600331 eth@10002000 {
332 compatible = "sandbox,eth";
333 reg = <0x10002000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500334 fake-host-hwaddr = [00 00 66 44 22 00];
Simon Glass5b968632015-05-22 15:42:15 -0600335 };
336
337 eth_5: eth@10003000 {
338 compatible = "sandbox,eth";
339 reg = <0x10003000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500340 fake-host-hwaddr = [00 00 66 44 22 11];
Simon Glass5b968632015-05-22 15:42:15 -0600341 };
342
Bin Meng04a11cb2015-08-27 22:25:53 -0700343 eth_3: sbe5 {
344 compatible = "sandbox,eth";
345 reg = <0x10005000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500346 fake-host-hwaddr = [00 00 66 44 22 33];
Bin Meng04a11cb2015-08-27 22:25:53 -0700347 };
348
Simon Glass5b968632015-05-22 15:42:15 -0600349 eth@10004000 {
350 compatible = "sandbox,eth";
351 reg = <0x10004000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500352 fake-host-hwaddr = [00 00 66 44 22 22];
Simon Glass5b968632015-05-22 15:42:15 -0600353 };
354
Rajan Vajab3b2ddb2018-09-19 03:43:46 -0700355 firmware {
356 sandbox_firmware: sandbox-firmware {
357 compatible = "sandbox,firmware";
358 };
359 };
360
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100361 pinctrl-gpio {
362 compatible = "sandbox,pinctrl-gpio";
Simon Glassb2c1cac2014-02-26 15:59:21 -0700363
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100364 gpio_a: base-gpios {
365 compatible = "sandbox,gpio";
366 gpio-controller;
367 #gpio-cells = <1>;
368 gpio-bank-name = "a";
369 sandbox,gpio-count = <20>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200370 hog_input_active_low {
371 gpio-hog;
372 input;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200373 gpios = <10 GPIO_ACTIVE_LOW>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200374 };
375 hog_input_active_high {
376 gpio-hog;
377 input;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200378 gpios = <11 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200379 };
380 hog_output_low {
381 gpio-hog;
382 output-low;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200383 gpios = <12 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200384 };
385 hog_output_high {
386 gpio-hog;
387 output-high;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200388 gpios = <13 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200389 };
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100390 };
391
392 gpio_b: extra-gpios {
393 compatible = "sandbox,gpio";
394 gpio-controller;
395 #gpio-cells = <5>;
396 gpio-bank-name = "b";
397 sandbox,gpio-count = <10>;
398 };
Simon Glass25348a42014-10-13 23:42:11 -0600399
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100400 gpio_c: pinmux-gpios {
401 compatible = "sandbox,gpio";
402 gpio-controller;
403 #gpio-cells = <2>;
404 gpio-bank-name = "c";
405 sandbox,gpio-count = <10>;
406 };
Patrick Delaunay28bdaa52020-01-13 11:35:14 +0100407 };
408
Simon Glass7df766e2014-12-10 08:55:55 -0700409 i2c@0 {
410 #address-cells = <1>;
411 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -0600412 reg = <0 1>;
Simon Glass7df766e2014-12-10 08:55:55 -0700413 compatible = "sandbox,i2c";
414 clock-frequency = <100000>;
415 eeprom@2c {
416 reg = <0x2c>;
417 compatible = "i2c-eeprom";
Simon Glass17b56f62018-11-18 08:14:34 -0700418 sandbox,emul = <&emul_eeprom>;
Michal Simek4f18f922020-05-28 11:48:55 +0200419 partitions {
420 compatible = "fixed-partitions";
421 #address-cells = <1>;
422 #size-cells = <1>;
423 bootcount_i2c: bootcount@10 {
424 reg = <10 2>;
425 };
426 };
Simon Glass7df766e2014-12-10 08:55:55 -0700427 };
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200428
Simon Glass336b2952015-05-22 15:42:17 -0600429 rtc_0: rtc@43 {
430 reg = <0x43>;
431 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700432 sandbox,emul = <&emul0>;
Simon Glass336b2952015-05-22 15:42:17 -0600433 };
434
435 rtc_1: rtc@61 {
436 reg = <0x61>;
437 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700438 sandbox,emul = <&emul1>;
439 };
440
441 i2c_emul: emul {
442 reg = <0xff>;
443 compatible = "sandbox,i2c-emul-parent";
444 emul_eeprom: emul-eeprom {
445 compatible = "sandbox,i2c-eeprom";
446 sandbox,filename = "i2c.bin";
447 sandbox,size = <256>;
448 };
449 emul0: emul0 {
450 compatible = "sandbox,i2c-rtc";
451 };
452 emul1: emull {
Simon Glass336b2952015-05-22 15:42:17 -0600453 compatible = "sandbox,i2c-rtc";
454 };
455 };
456
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200457 sandbox_pmic: sandbox_pmic {
458 reg = <0x40>;
Simon Glass17b56f62018-11-18 08:14:34 -0700459 sandbox,emul = <&emul_pmic0>;
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200460 };
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200461
462 mc34708: pmic@41 {
463 reg = <0x41>;
Simon Glass17b56f62018-11-18 08:14:34 -0700464 sandbox,emul = <&emul_pmic1>;
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200465 };
Simon Glass7df766e2014-12-10 08:55:55 -0700466 };
467
Philipp Tomsich1fc53302018-12-14 21:14:29 +0100468 bootcount@0 {
469 compatible = "u-boot,bootcount-rtc";
470 rtc = <&rtc_1>;
471 offset = <0x13>;
472 };
473
Michal Simek4f18f922020-05-28 11:48:55 +0200474 bootcount {
475 compatible = "u-boot,bootcount-i2c-eeprom";
476 i2c-eeprom = <&bootcount_i2c>;
477 };
478
Przemyslaw Marczak1bc7f232015-10-27 13:08:06 +0100479 adc@0 {
480 compatible = "sandbox,adc";
481 vdd-supply = <&buck2>;
482 vss-microvolts = <0>;
483 };
484
Simon Glass515dcff2020-02-06 09:55:00 -0700485 irq: irq {
Simon Glass54028bc2019-12-06 21:41:59 -0700486 compatible = "sandbox,irq";
Simon Glass515dcff2020-02-06 09:55:00 -0700487 interrupt-controller;
488 #interrupt-cells = <2>;
Simon Glass54028bc2019-12-06 21:41:59 -0700489 };
490
Simon Glass90b6fef2016-01-18 19:52:26 -0700491 lcd {
492 u-boot,dm-pre-reloc;
493 compatible = "sandbox,lcd-sdl";
494 xres = <1366>;
495 yres = <768>;
496 };
497
Simon Glassd783eb32015-07-06 12:54:34 -0600498 leds {
499 compatible = "gpio-leds";
500
501 iracibble {
502 gpios = <&gpio_a 1 0>;
503 label = "sandbox:red";
504 };
505
506 martinet {
507 gpios = <&gpio_a 2 0>;
508 label = "sandbox:green";
509 };
Patrick Bruennb58adfe2018-04-11 11:16:29 +0200510
511 default_on {
512 gpios = <&gpio_a 5 0>;
513 label = "sandbox:default_on";
514 default-state = "on";
515 };
516
517 default_off {
518 gpios = <&gpio_a 6 0>;
519 label = "sandbox:default_off";
520 default-state = "off";
521 };
Simon Glassd783eb32015-07-06 12:54:34 -0600522 };
523
Stephen Warren62f2c902016-05-16 17:41:37 -0600524 mbox: mbox {
525 compatible = "sandbox,mbox";
526 #mbox-cells = <1>;
527 };
528
529 mbox-test {
530 compatible = "sandbox,mbox-test";
531 mboxes = <&mbox 100>, <&mbox 1>;
532 mbox-names = "other", "test";
533 };
534
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900535 cpus {
536 cpu-test1 {
537 compatible = "sandbox,cpu_sandbox";
538 u-boot,dm-pre-reloc;
539 };
Mario Sixdea5df72018-08-06 10:23:44 +0200540
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900541 cpu-test2 {
542 compatible = "sandbox,cpu_sandbox";
543 u-boot,dm-pre-reloc;
544 };
Mario Sixdea5df72018-08-06 10:23:44 +0200545
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900546 cpu-test3 {
547 compatible = "sandbox,cpu_sandbox";
548 u-boot,dm-pre-reloc;
549 };
Mario Sixdea5df72018-08-06 10:23:44 +0200550 };
551
Dave Gerlach75dbdfc2020-07-15 23:39:58 -0500552 chipid: chipid {
553 compatible = "sandbox,soc";
554 };
555
Simon Glassc953aaf2018-12-10 10:37:34 -0700556 i2s: i2s {
557 compatible = "sandbox,i2s";
558 #sound-dai-cells = <1>;
Simon Glass4d5814c2019-02-16 20:24:56 -0700559 sandbox,silent; /* Don't emit sounds while testing */
Simon Glassc953aaf2018-12-10 10:37:34 -0700560 };
561
Jean-Jacques Hiblotdb97c7f2019-07-05 09:33:57 +0200562 nop-test_0 {
563 compatible = "sandbox,nop_sandbox1";
564 nop-test_1 {
565 compatible = "sandbox,nop_sandbox2";
566 bind = "True";
567 };
568 nop-test_2 {
569 compatible = "sandbox,nop_sandbox2";
570 bind = "False";
571 };
572 };
573
Mario Sixa8ce0ee2018-07-31 14:24:14 +0200574 misc-test {
575 compatible = "sandbox,misc_sandbox";
576 };
577
Simon Glasse4fef742017-04-23 20:02:07 -0600578 mmc2 {
579 compatible = "sandbox,mmc";
580 };
581
582 mmc1 {
583 compatible = "sandbox,mmc";
584 };
585
586 mmc0 {
Simon Glassd3e58e42015-07-06 12:54:32 -0600587 compatible = "sandbox,mmc";
588 };
589
Simon Glass53a68b32019-02-16 20:24:50 -0700590 pch {
591 compatible = "sandbox,pch";
592 };
593
Tom Rini4a3ca482020-02-11 12:41:23 -0500594 pci0: pci@0 {
Simon Glass3a6eae62015-03-05 12:25:34 -0700595 compatible = "sandbox,pci";
596 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -0500597 bus-range = <0x00 0xff>;
Simon Glass3a6eae62015-03-05 12:25:34 -0700598 #address-cells = <3>;
599 #size-cells = <2>;
Simon Glass35464f72019-09-25 08:56:08 -0600600 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000000
Simon Glass3a6eae62015-03-05 12:25:34 -0700601 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Bin Mengcbf071b2018-08-03 01:14:39 -0700602 pci@0,0 {
603 compatible = "pci-generic";
604 reg = <0x0000 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600605 sandbox,emul = <&swap_case_emul0_0>;
Bin Mengcbf071b2018-08-03 01:14:39 -0700606 };
Alex Margineanf1274432019-06-07 11:24:24 +0300607 pci@1,0 {
608 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -0600609 /* reg 0 is at 0x14, using FDT_PCI_SPACE_MEM32 */
610 reg = <0x02000814 0 0 0 0
611 0x01000810 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600612 sandbox,emul = <&swap_case_emul0_1>;
Alex Margineanf1274432019-06-07 11:24:24 +0300613 };
Simon Glass937bb472019-12-06 21:41:57 -0700614 p2sb-pci@2,0 {
615 compatible = "sandbox,p2sb";
616 reg = <0x02001010 0 0 0 0>;
617 sandbox,emul = <&p2sb_emul>;
618
619 adder {
620 intel,p2sb-port-id = <3>;
621 compatible = "sandbox,adder";
622 };
623 };
Simon Glass8c501022019-12-06 21:41:54 -0700624 pci@1e,0 {
625 compatible = "sandbox,pmc";
626 reg = <0xf000 0 0 0 0>;
627 sandbox,emul = <&pmc_emul1e>;
628 acpi-base = <0x400>;
629 gpe0-dwx-mask = <0xf>;
630 gpe0-dwx-shift-base = <4>;
631 gpe0-dw = <6 7 9>;
632 gpe0-sts = <0x20>;
633 gpe0-en = <0x30>;
634 };
Simon Glass3a6eae62015-03-05 12:25:34 -0700635 pci@1f,0 {
636 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -0600637 /* reg 0 is at 0x10, using FDT_PCI_SPACE_IO */
638 reg = <0x0100f810 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600639 sandbox,emul = <&swap_case_emul0_1f>;
Simon Glass3a6eae62015-03-05 12:25:34 -0700640 };
641 };
642
Simon Glassb98ba4c2019-09-25 08:56:10 -0600643 pci-emul0 {
644 compatible = "sandbox,pci-emul-parent";
645 swap_case_emul0_0: emul0@0,0 {
646 compatible = "sandbox,swap-case";
647 };
648 swap_case_emul0_1: emul0@1,0 {
649 compatible = "sandbox,swap-case";
650 use-ea;
651 };
652 swap_case_emul0_1f: emul0@1f,0 {
653 compatible = "sandbox,swap-case";
654 };
Simon Glass937bb472019-12-06 21:41:57 -0700655 p2sb_emul: emul@2,0 {
656 compatible = "sandbox,p2sb-emul";
657 };
Simon Glass8c501022019-12-06 21:41:54 -0700658 pmc_emul1e: emul@1e,0 {
659 compatible = "sandbox,pmc-emul";
660 };
Simon Glassb98ba4c2019-09-25 08:56:10 -0600661 };
662
Tom Rini4a3ca482020-02-11 12:41:23 -0500663 pci1: pci@1 {
Bin Meng408e5902018-08-03 01:14:41 -0700664 compatible = "sandbox,pci";
665 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -0500666 bus-range = <0x00 0xff>;
Bin Meng408e5902018-08-03 01:14:41 -0700667 #address-cells = <3>;
668 #size-cells = <2>;
Suneel Garapati3ac3aec2019-10-19 17:10:20 -0700669 ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000 // MEM0
670 0x02000000 0 0x31000000 0x31000000 0 0x2000 // MEM1
671 0x01000000 0 0x40000000 0x40000000 0 0x2000>;
Bin Meng5fed5362018-08-03 01:14:47 -0700672 sandbox,dev-info = <0x08 0x00 0x1234 0x5678
Marek Vasute5733222018-10-10 21:27:08 +0200673 0x0c 0x00 0x1234 0x5678
674 0x10 0x00 0x1234 0x5678>;
675 pci@10,0 {
676 reg = <0x8000 0 0 0 0>;
677 };
Bin Meng408e5902018-08-03 01:14:41 -0700678 };
679
Tom Rini4a3ca482020-02-11 12:41:23 -0500680 pci2: pci@2 {
Bin Meng510dddb2018-08-03 01:14:50 -0700681 compatible = "sandbox,pci";
682 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -0500683 bus-range = <0x00 0xff>;
Bin Meng510dddb2018-08-03 01:14:50 -0700684 #address-cells = <3>;
685 #size-cells = <2>;
686 ranges = <0x02000000 0 0x50000000 0x50000000 0 0x2000
687 0x01000000 0 0x60000000 0x60000000 0 0x2000>;
688 sandbox,dev-info = <0x08 0x00 0x1234 0x5678>;
689 pci@1f,0 {
690 compatible = "pci-generic";
691 reg = <0xf800 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600692 sandbox,emul = <&swap_case_emul2_1f>;
693 };
694 };
695
696 pci-emul2 {
697 compatible = "sandbox,pci-emul-parent";
698 swap_case_emul2_1f: emul2@1f,0 {
699 compatible = "sandbox,swap-case";
Bin Meng510dddb2018-08-03 01:14:50 -0700700 };
701 };
702
Ramon Friedc64f19b2019-04-27 11:15:23 +0300703 pci_ep: pci_ep {
704 compatible = "sandbox,pci_ep";
705 };
706
Simon Glass9c433fe2017-04-23 20:10:44 -0600707 probing {
708 compatible = "simple-bus";
709 test1 {
710 compatible = "denx,u-boot-probe-test";
711 };
712
713 test2 {
714 compatible = "denx,u-boot-probe-test";
715 };
716
717 test3 {
718 compatible = "denx,u-boot-probe-test";
719 };
720
721 test4 {
722 compatible = "denx,u-boot-probe-test";
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +0100723 first-syscon = <&syscon0>;
724 second-sys-ctrl = <&another_system_controller>;
Patrick Delaunayee010432019-03-07 09:57:13 +0100725 third-syscon = <&syscon2>;
Simon Glass9c433fe2017-04-23 20:10:44 -0600726 };
727 };
728
Stephen Warren92c67fa2016-07-13 13:45:31 -0600729 pwrdom: power-domain {
730 compatible = "sandbox,power-domain";
731 #power-domain-cells = <1>;
732 };
733
734 power-domain-test {
735 compatible = "sandbox,power-domain-test";
736 power-domains = <&pwrdom 2>;
737 };
738
Simon Glass5620cf82018-10-01 12:22:40 -0600739 pwm: pwm {
Simon Glasse62f4be2017-04-16 21:01:11 -0600740 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -0600741 #pwm-cells = <2>;
Simon Glasse62f4be2017-04-16 21:01:11 -0600742 };
743
744 pwm2 {
745 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -0600746 #pwm-cells = <2>;
Simon Glasse62f4be2017-04-16 21:01:11 -0600747 };
748
Simon Glass3d355e62015-07-06 12:54:31 -0600749 ram {
750 compatible = "sandbox,ram";
751 };
752
Simon Glassd860f222015-07-06 12:54:29 -0600753 reset@0 {
754 compatible = "sandbox,warm-reset";
755 };
756
757 reset@1 {
758 compatible = "sandbox,reset";
759 };
760
Stephen Warren6488e642016-06-17 09:43:59 -0600761 resetc: reset-ctl {
762 compatible = "sandbox,reset-ctl";
763 #reset-cells = <1>;
764 };
765
766 reset-ctl-test {
767 compatible = "sandbox,reset-ctl-test";
768 resets = <&resetc 100>, <&resetc 2>;
769 reset-names = "other", "test";
770 };
771
Sughosh Ganu23e37512019-12-28 23:58:31 +0530772 rng {
773 compatible = "sandbox,sandbox-rng";
774 };
775
Nishanth Menonedf85812015-09-17 15:42:41 -0500776 rproc_1: rproc@1 {
777 compatible = "sandbox,test-processor";
778 remoteproc-name = "remoteproc-test-dev1";
779 };
780
781 rproc_2: rproc@2 {
782 compatible = "sandbox,test-processor";
783 internal-memory-mapped;
784 remoteproc-name = "remoteproc-test-dev2";
785 };
786
Simon Glass5620cf82018-10-01 12:22:40 -0600787 panel {
788 compatible = "simple-panel";
789 backlight = <&backlight 0 100>;
790 };
791
Ramon Fried26ed32e2018-07-02 02:57:59 +0300792 smem@0 {
793 compatible = "sandbox,smem";
794 };
795
Simon Glass76072ac2018-12-10 10:37:36 -0700796 sound {
797 compatible = "sandbox,sound";
798 cpu {
799 sound-dai = <&i2s 0>;
800 };
801
802 codec {
803 sound-dai = <&audio 0>;
804 };
805 };
806
Simon Glass25348a42014-10-13 23:42:11 -0600807 spi@0 {
808 #address-cells = <1>;
809 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -0600810 reg = <0 1>;
Simon Glass25348a42014-10-13 23:42:11 -0600811 compatible = "sandbox,spi";
812 cs-gpios = <0>, <&gpio_a 0>;
813 spi.bin@0 {
814 reg = <0>;
Neil Armstronga009fa72019-02-10 10:16:20 +0000815 compatible = "spansion,m25p16", "jedec,spi-nor";
Simon Glass25348a42014-10-13 23:42:11 -0600816 spi-max-frequency = <40000000>;
817 sandbox,filename = "spi.bin";
818 };
819 };
820
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +0100821 syscon0: syscon@0 {
Simon Glasscd556522015-07-06 12:54:35 -0600822 compatible = "sandbox,syscon0";
Mario Sixe3f59f42018-10-04 09:00:40 +0200823 reg = <0x10 16>;
Simon Glasscd556522015-07-06 12:54:35 -0600824 };
825
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +0100826 another_system_controller: syscon@1 {
Simon Glasscd556522015-07-06 12:54:35 -0600827 compatible = "sandbox,syscon1";
Simon Glasscf61f742015-07-06 12:54:36 -0600828 reg = <0x20 5
829 0x28 6
830 0x30 7
831 0x38 8>;
Simon Glasscd556522015-07-06 12:54:35 -0600832 };
833
Patrick Delaunayee010432019-03-07 09:57:13 +0100834 syscon2: syscon@2 {
Masahiro Yamada42ab1072018-04-23 13:26:53 +0900835 compatible = "simple-mfd", "syscon";
836 reg = <0x40 5
837 0x48 6
838 0x50 7
839 0x58 8>;
840 };
841
Thomas Chou6f2cfbf2015-12-11 16:27:34 +0800842 timer {
843 compatible = "sandbox,timer";
844 clock-frequency = <1000000>;
845 };
846
Miquel Raynal80938c12018-05-15 11:57:27 +0200847 tpm2 {
848 compatible = "sandbox,tpm2";
849 };
850
Simon Glass5b968632015-05-22 15:42:15 -0600851 uart0: serial {
852 compatible = "sandbox,serial";
853 u-boot,dm-pre-reloc;
Joe Hershberger4c197242015-03-22 17:09:15 -0500854 };
855
Simon Glass31680482015-03-25 12:23:05 -0600856 usb_0: usb@0 {
857 compatible = "sandbox,usb";
858 status = "disabled";
859 hub {
860 compatible = "sandbox,usb-hub";
861 #address-cells = <1>;
862 #size-cells = <0>;
863 flash-stick {
864 reg = <0>;
865 compatible = "sandbox,usb-flash";
866 };
867 };
868 };
869
870 usb_1: usb@1 {
871 compatible = "sandbox,usb";
872 hub {
873 compatible = "usb-hub";
874 usb,device-class = <9>;
Michael Walle7c961322020-06-02 01:47:07 +0200875 #address-cells = <1>;
876 #size-cells = <0>;
Simon Glass31680482015-03-25 12:23:05 -0600877 hub-emul {
878 compatible = "sandbox,usb-hub";
879 #address-cells = <1>;
880 #size-cells = <0>;
Simon Glass4700fe52015-11-08 23:48:01 -0700881 flash-stick@0 {
Simon Glass31680482015-03-25 12:23:05 -0600882 reg = <0>;
883 compatible = "sandbox,usb-flash";
884 sandbox,filepath = "testflash.bin";
885 };
886
Simon Glass4700fe52015-11-08 23:48:01 -0700887 flash-stick@1 {
888 reg = <1>;
889 compatible = "sandbox,usb-flash";
890 sandbox,filepath = "testflash1.bin";
891 };
892
893 flash-stick@2 {
894 reg = <2>;
895 compatible = "sandbox,usb-flash";
896 sandbox,filepath = "testflash2.bin";
897 };
898
Simon Glassc0ccc722015-11-08 23:48:08 -0700899 keyb@3 {
900 reg = <3>;
901 compatible = "sandbox,usb-keyb";
902 };
903
Simon Glass31680482015-03-25 12:23:05 -0600904 };
Michael Walle7c961322020-06-02 01:47:07 +0200905
906 usbstor@1 {
907 reg = <1>;
908 };
909 usbstor@3 {
910 reg = <3>;
911 };
Simon Glass31680482015-03-25 12:23:05 -0600912 };
913 };
914
915 usb_2: usb@2 {
916 compatible = "sandbox,usb";
917 status = "disabled";
918 };
919
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +0200920 spmi: spmi@0 {
921 compatible = "sandbox,spmi";
922 #address-cells = <0x1>;
923 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -0600924 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +0200925 pm8916@0 {
926 compatible = "qcom,spmi-pmic";
927 reg = <0x0 0x1>;
928 #address-cells = <0x1>;
929 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -0600930 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +0200931
932 spmi_gpios: gpios@c000 {
933 compatible = "qcom,pm8916-gpio";
934 reg = <0xc000 0x400>;
935 gpio-controller;
936 gpio-count = <4>;
937 #gpio-cells = <2>;
938 gpio-bank-name="spmi";
939 };
940 };
941 };
maxims@google.comdaea6d42017-04-17 12:00:21 -0700942
943 wdt0: wdt@0 {
944 compatible = "sandbox,wdt";
945 };
Rob Clarka471b672018-01-10 11:33:30 +0100946
Mario Six95922152018-08-09 14:51:19 +0200947 axi: axi@0 {
948 compatible = "sandbox,axi";
949 #address-cells = <0x1>;
950 #size-cells = <0x1>;
951 store@0 {
952 compatible = "sandbox,sandbox_store";
953 reg = <0x0 0x400>;
954 };
955 };
956
Rob Clarka471b672018-01-10 11:33:30 +0100957 chosen {
Simon Glass305ac9a2018-02-03 10:36:58 -0700958 #address-cells = <1>;
959 #size-cells = <1>;
Simon Glassf3455962020-01-27 08:49:43 -0700960 setting = "sunrise ohoka";
961 other-node = "/some-bus/c-test@5";
Simon Glasse09223c2020-01-27 08:49:46 -0700962 int-values = <0x1937 72993>;
Simon Glass3c601b12020-07-07 13:12:06 -0600963 u-boot,acpi-ssdt-order = <&acpi_test2 &acpi_test1>;
Rob Clarka471b672018-01-10 11:33:30 +0100964 chosen-test {
965 compatible = "denx,u-boot-fdt-test";
966 reg = <9 1>;
967 };
968 };
Mario Six35616ef2018-03-12 14:53:33 +0100969
970 translation-test@8000 {
971 compatible = "simple-bus";
972 reg = <0x8000 0x4000>;
973
974 #address-cells = <0x2>;
975 #size-cells = <0x1>;
976
977 ranges = <0 0x0 0x8000 0x1000
978 1 0x100 0x9000 0x1000
979 2 0x200 0xA000 0x1000
980 3 0x300 0xB000 0x1000
981 >;
982
Fabien Dessenne22236e02019-05-31 15:11:30 +0200983 dma-ranges = <0 0x000 0x10000000 0x1000
984 1 0x100 0x20000000 0x1000
985 >;
986
Mario Six35616ef2018-03-12 14:53:33 +0100987 dev@0,0 {
988 compatible = "denx,u-boot-fdt-dummy";
989 reg = <0 0x0 0x1000>;
Álvaro Fernández Rojasa3181152018-12-03 19:37:09 +0100990 reg-names = "sandbox-dummy-0";
Mario Six35616ef2018-03-12 14:53:33 +0100991 };
992
993 dev@1,100 {
994 compatible = "denx,u-boot-fdt-dummy";
995 reg = <1 0x100 0x1000>;
996
997 };
998
999 dev@2,200 {
1000 compatible = "denx,u-boot-fdt-dummy";
1001 reg = <2 0x200 0x1000>;
1002 };
1003
1004
1005 noxlatebus@3,300 {
1006 compatible = "simple-bus";
1007 reg = <3 0x300 0x1000>;
1008
1009 #address-cells = <0x1>;
1010 #size-cells = <0x0>;
1011
1012 dev@42 {
1013 compatible = "denx,u-boot-fdt-dummy";
1014 reg = <0x42>;
1015 };
1016 };
1017 };
Mario Six02ad6fb2018-09-27 09:19:31 +02001018
1019 osd {
1020 compatible = "sandbox,sandbox_osd";
1021 };
Tom Rinib93eea72018-09-30 18:16:51 -04001022
Mario Sixab664ff2018-07-31 11:44:13 +02001023 board {
1024 compatible = "sandbox,board_sandbox";
1025 };
Jens Wiklander86afaa62018-09-25 16:40:16 +02001026
1027 sandbox_tee {
1028 compatible = "sandbox,tee";
1029 };
Bin Meng1bb290d2018-10-15 02:21:26 -07001030
1031 sandbox_virtio1 {
1032 compatible = "sandbox,virtio1";
1033 };
1034
1035 sandbox_virtio2 {
1036 compatible = "sandbox,virtio2";
1037 };
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001038
1039 pinctrl {
1040 compatible = "sandbox,pinctrl";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001041
1042 pinctrl-names = "default";
1043 pinctrl-0 = <&gpios>;
1044
1045 gpios: gpios {
1046 gpio0 {
1047 pins = "GPIO0";
1048 bias-pull-up;
1049 input-disable;
1050 };
1051 gpio1 {
1052 pins = "GPIO1";
1053 output-high;
1054 drive-open-drain;
1055 };
1056 gpio2 {
1057 pins = "GPIO2";
1058 bias-pull-down;
1059 input-enable;
1060 };
1061 gpio3 {
1062 pins = "GPIO3";
1063 bias-disable;
1064 };
1065 };
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001066 };
Benjamin Gaignarda550b542018-11-27 13:49:50 +01001067
1068 hwspinlock@0 {
1069 compatible = "sandbox,hwspinlock";
1070 };
Grygorii Strashko19ebf0b2018-11-28 19:17:51 +01001071
1072 dma: dma {
1073 compatible = "sandbox,dma";
1074 #dma-cells = <1>;
1075
1076 dmas = <&dma 0>, <&dma 1>, <&dma 2>;
1077 dma-names = "m2m", "tx0", "rx0";
1078 };
Alex Marginean0daa53a2019-06-03 19:12:28 +03001079
Alex Marginean0649be52019-07-12 10:13:53 +03001080 /*
1081 * keep mdio-mux ahead of mdio so that the mux is removed first at the
1082 * end of the test. If parent mdio is removed first, clean-up of the
1083 * mux will trigger a 2nd probe of parent-mdio, leaving parent-mdio
1084 * active at the end of the test. That it turn doesn't allow the mdio
1085 * class to be destroyed, triggering an error.
1086 */
1087 mdio-mux-test {
1088 compatible = "sandbox,mdio-mux";
1089 #address-cells = <1>;
1090 #size-cells = <0>;
1091 mdio-parent-bus = <&mdio>;
1092
1093 mdio-ch-test@0 {
1094 reg = <0>;
1095 };
1096 mdio-ch-test@1 {
1097 reg = <1>;
1098 };
1099 };
1100
1101 mdio: mdio-test {
Alex Marginean0daa53a2019-06-03 19:12:28 +03001102 compatible = "sandbox,mdio";
1103 };
Sean Andersonb7860542020-06-24 06:41:12 -04001104
1105 pm-bus-test {
1106 compatible = "simple-pm-bus";
1107 clocks = <&clk_sandbox 4>;
1108 power-domains = <&pwrdom 1>;
1109 };
Sean Anderson0c1f6bf2020-06-24 06:41:14 -04001110
1111 resetc2: syscon-reset {
1112 compatible = "syscon-reset";
1113 #reset-cells = <1>;
1114 regmap = <&syscon0>;
1115 offset = <1>;
1116 mask = <0x27FFFFFF>;
1117 assert-high = <0>;
1118 };
1119
1120 syscon-reset-test {
1121 compatible = "sandbox,misc_sandbox";
1122 resets = <&resetc2 15>, <&resetc2 30>, <&resetc2 60>;
1123 reset-names = "valid", "no_mask", "out_of_range";
1124 };
Simon Glassb2c1cac2014-02-26 15:59:21 -07001125};
Przemyslaw Marczak77bee052015-05-13 13:38:35 +02001126
1127#include "sandbox_pmic.dtsi"