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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Rajeshwari Shinde9b4ae502012-05-02 19:18:51 +05302/*
Rajeshwari Shindedad39d42012-05-21 16:38:03 +05303 * SAMSUNG EXYNOS USB HOST EHCI Controller
Rajeshwari Shinde9b4ae502012-05-02 19:18:51 +05304 *
5 * Copyright (C) 2012 Samsung Electronics Co.Ltd
6 * Vivek Gautam <gautam.vivek@samsung.com>
Rajeshwari Shinde9b4ae502012-05-02 19:18:51 +05307 */
8
Simon Glass2b8ceec2015-03-25 12:22:44 -06009#include <dm.h>
Rajeshwari Shinde23fbde52013-01-07 23:35:03 +000010#include <fdtdec.h>
Simon Glass0f2af882020-05-10 11:40:05 -060011#include <log.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060012#include <asm/global_data.h>
Simon Glassdbd79542020-05-10 11:40:11 -060013#include <linux/delay.h>
Masahiro Yamada75f82d02018-03-05 01:20:11 +090014#include <linux/libfdt.h>
Rajeshwari Shinde23fbde52013-01-07 23:35:03 +000015#include <malloc.h>
Rajeshwari Shinde9b4ae502012-05-02 19:18:51 +053016#include <usb.h>
17#include <asm/arch/cpu.h>
Rajeshwari Shindedad39d42012-05-21 16:38:03 +053018#include <asm/arch/ehci.h>
Rajeshwari Shinde84448072012-05-14 05:52:02 +000019#include <asm/arch/system.h>
Rajeshwari Shinde21965ac2012-05-14 05:52:03 +000020#include <asm/arch/power.h>
Julius Wernerddcb9bd2013-09-14 14:02:52 +053021#include <asm/gpio.h>
Masahiro Yamada64e4f7f2016-09-21 11:28:57 +090022#include <linux/errno.h>
Rajeshwari Shinde23fbde52013-01-07 23:35:03 +000023#include <linux/compat.h>
Rajeshwari Shinde9b4ae502012-05-02 19:18:51 +053024#include "ehci.h"
Rajeshwari Shinde9b4ae502012-05-02 19:18:51 +053025
Rajeshwari Shinde23fbde52013-01-07 23:35:03 +000026/* Declare global data pointer */
27DECLARE_GLOBAL_DATA_PTR;
28
Simon Glassb75b15b2020-12-03 16:55:23 -070029struct exynos_ehci_plat {
30 struct usb_plat usb_plat;
Simon Glass2b8ceec2015-03-25 12:22:44 -060031 fdt_addr_t hcd_base;
32 fdt_addr_t phy_base;
33 struct gpio_desc vbus_gpio;
34};
Simon Glass2b8ceec2015-03-25 12:22:44 -060035
Rajeshwari Shinde23fbde52013-01-07 23:35:03 +000036/**
37 * Contains pointers to register base addresses
38 * for the usb controller.
39 */
40struct exynos_ehci {
Simon Glass2b8ceec2015-03-25 12:22:44 -060041 struct ehci_ctrl ctrl;
Rajeshwari Shinde23fbde52013-01-07 23:35:03 +000042 struct exynos_usb_phy *usb;
Vivek Gautambab686c2013-03-06 14:18:32 +053043 struct ehci_hccr *hcd;
Rajeshwari Shinde23fbde52013-01-07 23:35:03 +000044};
45
Simon Glassaad29ae2020-12-03 16:55:21 -070046static int ehci_usb_of_to_plat(struct udevice *dev)
Simon Glass2b8ceec2015-03-25 12:22:44 -060047{
Simon Glassb75b15b2020-12-03 16:55:23 -070048 struct exynos_ehci_plat *plat = dev_get_plat(dev);
Simon Glass2b8ceec2015-03-25 12:22:44 -060049 const void *blob = gd->fdt_blob;
50 unsigned int node;
51 int depth;
52
53 /*
54 * Get the base address for XHCI controller from the device node
55 */
Masahiro Yamadaa89b4de2020-07-17 14:36:48 +090056 plat->hcd_base = dev_read_addr(dev);
Simon Glass2b8ceec2015-03-25 12:22:44 -060057 if (plat->hcd_base == FDT_ADDR_T_NONE) {
58 debug("Can't get the XHCI register base address\n");
59 return -ENXIO;
60 }
61
62 depth = 0;
Simon Glassdd79d6e2017-01-17 16:52:55 -070063 node = fdtdec_next_compatible_subnode(blob, dev_of_offset(dev),
Simon Glass2b8ceec2015-03-25 12:22:44 -060064 COMPAT_SAMSUNG_EXYNOS_USB_PHY, &depth);
65 if (node <= 0) {
66 debug("XHCI: Can't get device node for usb3-phy controller\n");
67 return -ENODEV;
68 }
69
70 /*
71 * Get the base address for usbphy from the device node
72 */
73 plat->phy_base = fdtdec_get_addr(blob, node, "reg");
74 if (plat->phy_base == FDT_ADDR_T_NONE) {
75 debug("Can't get the usbphy register address\n");
76 return -ENXIO;
77 }
78
79 /* Vbus gpio */
80 gpio_request_by_name(dev, "samsung,vbus-gpio", 0,
81 &plat->vbus_gpio, GPIOD_IS_OUT);
82
83 return 0;
84}
Rajeshwari Shinde23fbde52013-01-07 23:35:03 +000085
Suriyan Ramasami97f4ef62014-10-29 09:22:43 -070086static void exynos5_setup_usb_phy(struct exynos_usb_phy *usb)
Rajeshwari Shinde9b4ae502012-05-02 19:18:51 +053087{
Inderpal Singh2eb65612014-01-08 09:19:56 +053088 u32 hsic_ctrl;
89
Rajeshwari Shinde9b4ae502012-05-02 19:18:51 +053090 clrbits_le32(&usb->usbphyctrl0,
91 HOST_CTRL0_FSEL_MASK |
92 HOST_CTRL0_COMMONON_N |
93 /* HOST Phy setting */
94 HOST_CTRL0_PHYSWRST |
95 HOST_CTRL0_PHYSWRSTALL |
96 HOST_CTRL0_SIDDQ |
97 HOST_CTRL0_FORCESUSPEND |
98 HOST_CTRL0_FORCESLEEP);
99
100 setbits_le32(&usb->usbphyctrl0,
101 /* Setting up the ref freq */
102 (CLK_24MHZ << 16) |
103 /* HOST Phy setting */
104 HOST_CTRL0_LINKSWRST |
105 HOST_CTRL0_UTMISWRST);
106 udelay(10);
107 clrbits_le32(&usb->usbphyctrl0,
108 HOST_CTRL0_LINKSWRST |
109 HOST_CTRL0_UTMISWRST);
Inderpal Singh2eb65612014-01-08 09:19:56 +0530110
111 /* HSIC Phy Setting */
112 hsic_ctrl = (HSIC_CTRL_FORCESUSPEND |
113 HSIC_CTRL_FORCESLEEP |
114 HSIC_CTRL_SIDDQ);
115
116 clrbits_le32(&usb->hsicphyctrl1, hsic_ctrl);
117 clrbits_le32(&usb->hsicphyctrl2, hsic_ctrl);
118
119 hsic_ctrl = (((HSIC_CTRL_REFCLKDIV_12 & HSIC_CTRL_REFCLKDIV_MASK)
120 << HSIC_CTRL_REFCLKDIV_SHIFT)
121 | ((HSIC_CTRL_REFCLKSEL & HSIC_CTRL_REFCLKSEL_MASK)
122 << HSIC_CTRL_REFCLKSEL_SHIFT)
123 | HSIC_CTRL_UTMISWRST);
124
125 setbits_le32(&usb->hsicphyctrl1, hsic_ctrl);
126 setbits_le32(&usb->hsicphyctrl2, hsic_ctrl);
127
128 udelay(10);
129
130 clrbits_le32(&usb->hsicphyctrl1, HSIC_CTRL_PHYSWRST |
131 HSIC_CTRL_UTMISWRST);
132
133 clrbits_le32(&usb->hsicphyctrl2, HSIC_CTRL_PHYSWRST |
134 HSIC_CTRL_UTMISWRST);
135
Rajeshwari Shinde9b4ae502012-05-02 19:18:51 +0530136 udelay(20);
137
138 /* EHCI Ctrl setting */
139 setbits_le32(&usb->ehcictrl,
140 EHCICTRL_ENAINCRXALIGN |
141 EHCICTRL_ENAINCR4 |
142 EHCICTRL_ENAINCR8 |
143 EHCICTRL_ENAINCR16);
144}
145
Suriyan Ramasami97f4ef62014-10-29 09:22:43 -0700146static void exynos4412_setup_usb_phy(struct exynos4412_usb_phy *usb)
147{
148 writel(CLK_24MHZ, &usb->usbphyclk);
149
150 clrbits_le32(&usb->usbphyctrl, (PHYPWR_NORMAL_MASK_HSIC0 |
151 PHYPWR_NORMAL_MASK_HSIC1 | PHYPWR_NORMAL_MASK_PHY1 |
152 PHYPWR_NORMAL_MASK_PHY0));
153
154 setbits_le32(&usb->usbphyrstcon, (RSTCON_HOSTPHY_SWRST | RSTCON_SWRST));
155 udelay(10);
156 clrbits_le32(&usb->usbphyrstcon, (RSTCON_HOSTPHY_SWRST | RSTCON_SWRST));
157}
158
159static void setup_usb_phy(struct exynos_usb_phy *usb)
160{
161 set_usbhost_mode(USB20_PHY_CFG_HOST_LINK_EN);
162
163 set_usbhost_phy_ctrl(POWER_USB_HOST_PHY_CTRL_EN);
164
165 if (cpu_is_exynos5())
166 exynos5_setup_usb_phy(usb);
167 else if (cpu_is_exynos4())
168 if (proid_is_exynos4412())
169 exynos4412_setup_usb_phy((struct exynos4412_usb_phy *)
170 usb);
171}
172
173static void exynos5_reset_usb_phy(struct exynos_usb_phy *usb)
Rajeshwari Shinde9b4ae502012-05-02 19:18:51 +0530174{
Inderpal Singh2eb65612014-01-08 09:19:56 +0530175 u32 hsic_ctrl;
176
Rajeshwari Shinde9b4ae502012-05-02 19:18:51 +0530177 /* HOST_PHY reset */
178 setbits_le32(&usb->usbphyctrl0,
179 HOST_CTRL0_PHYSWRST |
180 HOST_CTRL0_PHYSWRSTALL |
181 HOST_CTRL0_SIDDQ |
182 HOST_CTRL0_FORCESUSPEND |
183 HOST_CTRL0_FORCESLEEP);
Rajeshwari Shinde21965ac2012-05-14 05:52:03 +0000184
Inderpal Singh2eb65612014-01-08 09:19:56 +0530185 /* HSIC Phy reset */
186 hsic_ctrl = (HSIC_CTRL_FORCESUSPEND |
187 HSIC_CTRL_FORCESLEEP |
188 HSIC_CTRL_SIDDQ |
189 HSIC_CTRL_PHYSWRST);
190
191 setbits_le32(&usb->hsicphyctrl1, hsic_ctrl);
192 setbits_le32(&usb->hsicphyctrl2, hsic_ctrl);
Suriyan Ramasami97f4ef62014-10-29 09:22:43 -0700193}
194
195static void exynos4412_reset_usb_phy(struct exynos4412_usb_phy *usb)
196{
197 setbits_le32(&usb->usbphyctrl, (PHYPWR_NORMAL_MASK_HSIC0 |
198 PHYPWR_NORMAL_MASK_HSIC1 | PHYPWR_NORMAL_MASK_PHY1 |
199 PHYPWR_NORMAL_MASK_PHY0));
200}
201
202/* Reset the EHCI host controller. */
203static void reset_usb_phy(struct exynos_usb_phy *usb)
204{
205 if (cpu_is_exynos5())
206 exynos5_reset_usb_phy(usb);
207 else if (cpu_is_exynos4())
208 if (proid_is_exynos4412())
209 exynos4412_reset_usb_phy((struct exynos4412_usb_phy *)
210 usb);
Inderpal Singh2eb65612014-01-08 09:19:56 +0530211
Rajeshwari Shinde21965ac2012-05-14 05:52:03 +0000212 set_usbhost_phy_ctrl(POWER_USB_HOST_PHY_CTRL_DISABLE);
Rajeshwari Shinde9b4ae502012-05-02 19:18:51 +0530213}
Simon Glass2b8ceec2015-03-25 12:22:44 -0600214
Simon Glass2b8ceec2015-03-25 12:22:44 -0600215static int ehci_usb_probe(struct udevice *dev)
216{
Simon Glassb75b15b2020-12-03 16:55:23 -0700217 struct exynos_ehci_plat *plat = dev_get_plat(dev);
Simon Glass2b8ceec2015-03-25 12:22:44 -0600218 struct exynos_ehci *ctx = dev_get_priv(dev);
219 struct ehci_hcor *hcor;
220
221 ctx->hcd = (struct ehci_hccr *)plat->hcd_base;
222 ctx->usb = (struct exynos_usb_phy *)plat->phy_base;
Simon Glass2b8ceec2015-03-25 12:22:44 -0600223
224 /* setup the Vbus gpio here */
225 if (dm_gpio_is_valid(&plat->vbus_gpio))
226 dm_gpio_set_value(&plat->vbus_gpio, 1);
227
228 setup_usb_phy(ctx->usb);
Lukasz Majewskia9f74bb2015-12-10 16:32:25 +0100229 hcor = (struct ehci_hcor *)((uint32_t)ctx->hcd +
230 HC_LENGTH(ehci_readl(&ctx->hcd->cr_capbase)));
Simon Glass2b8ceec2015-03-25 12:22:44 -0600231
232 return ehci_register(dev, ctx->hcd, hcor, NULL, 0, USB_INIT_HOST);
233}
234
235static int ehci_usb_remove(struct udevice *dev)
236{
237 struct exynos_ehci *ctx = dev_get_priv(dev);
238 int ret;
239
240 ret = ehci_deregister(dev);
241 if (ret)
242 return ret;
243 reset_usb_phy(ctx->usb);
244
245 return 0;
246}
247
248static const struct udevice_id ehci_usb_ids[] = {
249 { .compatible = "samsung,exynos-ehci" },
250 { }
251};
252
253U_BOOT_DRIVER(usb_ehci) = {
254 .name = "ehci_exynos",
255 .id = UCLASS_USB,
256 .of_match = ehci_usb_ids,
Simon Glassaad29ae2020-12-03 16:55:21 -0700257 .of_to_plat = ehci_usb_of_to_plat,
Simon Glass2b8ceec2015-03-25 12:22:44 -0600258 .probe = ehci_usb_probe,
259 .remove = ehci_usb_remove,
260 .ops = &ehci_usb_ops,
Simon Glass8a2b47f2020-12-03 16:55:17 -0700261 .priv_auto = sizeof(struct exynos_ehci),
Simon Glassb75b15b2020-12-03 16:55:23 -0700262 .plat_auto = sizeof(struct exynos_ehci_plat),
Simon Glass2b8ceec2015-03-25 12:22:44 -0600263 .flags = DM_FLAG_ALLOC_PRIV_DMA,
264};