developer | 7b27b8d | 2019-08-22 12:26:50 +0200 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* |
| 3 | * Copyright (c) 2015 - 2019 MediaTek Inc. |
| 4 | * Author: Chunfeng Yun <chunfeng.yun@mediatek.com> |
| 5 | * Ryder Lee <ryder.lee@mediatek.com> |
| 6 | */ |
| 7 | |
developer | 7b27b8d | 2019-08-22 12:26:50 +0200 | [diff] [blame] | 8 | #include <clk.h> |
| 9 | #include <dm.h> |
| 10 | #include <generic-phy.h> |
Simon Glass | 9bc1564 | 2020-02-03 07:36:16 -0700 | [diff] [blame] | 11 | #include <malloc.h> |
developer | 7b27b8d | 2019-08-22 12:26:50 +0200 | [diff] [blame] | 12 | #include <mapmem.h> |
| 13 | #include <asm/io.h> |
Simon Glass | 9bc1564 | 2020-02-03 07:36:16 -0700 | [diff] [blame] | 14 | #include <dm/device_compat.h> |
Simon Glass | d66c5f7 | 2020-02-03 07:36:15 -0700 | [diff] [blame] | 15 | #include <dm/devres.h> |
developer | ad4890f | 2023-02-17 17:04:08 +0800 | [diff] [blame] | 16 | #include <linux/bitfield.h> |
Simon Glass | 4dcacfc | 2020-05-10 11:40:13 -0600 | [diff] [blame] | 17 | #include <linux/bitops.h> |
Simon Glass | dbd7954 | 2020-05-10 11:40:11 -0600 | [diff] [blame] | 18 | #include <linux/delay.h> |
developer | 7b27b8d | 2019-08-22 12:26:50 +0200 | [diff] [blame] | 19 | |
| 20 | #include <dt-bindings/phy/phy.h> |
| 21 | |
| 22 | /* version V1 sub-banks offset base address */ |
| 23 | /* banks shared by multiple phys */ |
| 24 | #define SSUSB_SIFSLV_V1_SPLLC 0x000 /* shared by u3 phys */ |
developer | 8a17d5f | 2020-05-02 11:35:15 +0200 | [diff] [blame] | 25 | #define SSUSB_SIFSLV_V1_U2FREQ 0x100 /* shared by u2 phys */ |
developer | 7b27b8d | 2019-08-22 12:26:50 +0200 | [diff] [blame] | 26 | #define SSUSB_SIFSLV_V1_CHIP 0x300 /* shared by u3 phys */ |
developer | 8a17d5f | 2020-05-02 11:35:15 +0200 | [diff] [blame] | 27 | /* u2 phy bank */ |
| 28 | #define SSUSB_SIFSLV_V1_U2PHY_COM 0x000 |
developer | 7b27b8d | 2019-08-22 12:26:50 +0200 | [diff] [blame] | 29 | /* u3/pcie/sata phy banks */ |
| 30 | #define SSUSB_SIFSLV_V1_U3PHYD 0x000 |
| 31 | #define SSUSB_SIFSLV_V1_U3PHYA 0x200 |
| 32 | |
developer | 8b30260 | 2020-05-02 11:35:16 +0200 | [diff] [blame] | 33 | /* version V2 sub-banks offset base address */ |
| 34 | /* u2 phy banks */ |
| 35 | #define SSUSB_SIFSLV_V2_MISC 0x000 |
| 36 | #define SSUSB_SIFSLV_V2_U2FREQ 0x100 |
| 37 | #define SSUSB_SIFSLV_V2_U2PHY_COM 0x300 |
| 38 | /* u3/pcie/sata phy banks */ |
| 39 | #define SSUSB_SIFSLV_V2_SPLLC 0x000 |
| 40 | #define SSUSB_SIFSLV_V2_CHIP 0x100 |
| 41 | #define SSUSB_SIFSLV_V2_U3PHYD 0x200 |
| 42 | #define SSUSB_SIFSLV_V2_U3PHYA 0x400 |
| 43 | |
developer | 8a17d5f | 2020-05-02 11:35:15 +0200 | [diff] [blame] | 44 | #define U3P_USBPHYACR0 0x000 |
| 45 | #define PA0_RG_U2PLL_FORCE_ON BIT(15) |
developer | 53cecc0 | 2023-02-17 17:04:09 +0800 | [diff] [blame] | 46 | #define PA0_USB20_PLL_PREDIV GENMASK(7, 6) |
developer | 8a17d5f | 2020-05-02 11:35:15 +0200 | [diff] [blame] | 47 | #define PA0_RG_USB20_INTR_EN BIT(5) |
| 48 | |
developer | 9a9c334 | 2023-12-13 14:41:34 +0800 | [diff] [blame] | 49 | #define U3P_USBPHYACR1 0x004 |
| 50 | #define PA1_RG_INTR_CAL GENMASK(23, 19) |
| 51 | #define PA1_RG_VRT_SEL GENMASK(14, 12) |
| 52 | #define PA1_RG_TERM_SEL GENMASK(10, 8) |
| 53 | |
developer | 53cecc0 | 2023-02-17 17:04:09 +0800 | [diff] [blame] | 54 | #define U3P_USBPHYACR2 0x008 |
| 55 | #define PA2_RG_U2PLL_BW GENMASK(21, 19) |
| 56 | |
developer | 8a17d5f | 2020-05-02 11:35:15 +0200 | [diff] [blame] | 57 | #define U3P_USBPHYACR5 0x014 |
| 58 | #define PA5_RG_U2_HSTX_SRCAL_EN BIT(15) |
| 59 | #define PA5_RG_U2_HSTX_SRCTRL GENMASK(14, 12) |
developer | 8a17d5f | 2020-05-02 11:35:15 +0200 | [diff] [blame] | 60 | #define PA5_RG_U2_HS_100U_U3_EN BIT(11) |
| 61 | |
| 62 | #define U3P_USBPHYACR6 0x018 |
developer | 9a9c334 | 2023-12-13 14:41:34 +0800 | [diff] [blame] | 63 | #define PA6_RG_U2_PRE_EMP GENMASK(31, 30) |
developer | 8a17d5f | 2020-05-02 11:35:15 +0200 | [diff] [blame] | 64 | #define PA6_RG_U2_BC11_SW_EN BIT(23) |
| 65 | #define PA6_RG_U2_OTG_VBUSCMP_EN BIT(20) |
developer | 9a9c334 | 2023-12-13 14:41:34 +0800 | [diff] [blame] | 66 | #define PA6_RG_U2_DISCTH GENMASK(7, 4) |
developer | 8a17d5f | 2020-05-02 11:35:15 +0200 | [diff] [blame] | 67 | #define PA6_RG_U2_SQTH GENMASK(3, 0) |
developer | 8a17d5f | 2020-05-02 11:35:15 +0200 | [diff] [blame] | 68 | |
| 69 | #define U3P_U2PHYACR4 0x020 |
| 70 | #define P2C_RG_USB20_GPIO_CTL BIT(9) |
| 71 | #define P2C_USB20_GPIO_MODE BIT(8) |
| 72 | #define P2C_U2_GPIO_CTR_MSK \ |
| 73 | (P2C_RG_USB20_GPIO_CTL | P2C_USB20_GPIO_MODE) |
| 74 | |
developer | 53cecc0 | 2023-02-17 17:04:09 +0800 | [diff] [blame] | 75 | #define U3P_U2PHYA_RESV 0x030 |
| 76 | #define P2R_RG_U2PLL_FBDIV_26M 0x1bb13b |
| 77 | #define P2R_RG_U2PLL_FBDIV_48M 0x3c0000 |
| 78 | |
| 79 | #define U3P_U2PHYA_RESV1 0x044 |
| 80 | #define P2R_RG_U2PLL_REFCLK_SEL BIT(5) |
| 81 | #define P2R_RG_U2PLL_FRA_EN BIT(3) |
| 82 | |
developer | 8a17d5f | 2020-05-02 11:35:15 +0200 | [diff] [blame] | 83 | #define U3P_U2PHYDTM0 0x068 |
| 84 | #define P2C_FORCE_UART_EN BIT(26) |
| 85 | #define P2C_FORCE_DATAIN BIT(23) |
| 86 | #define P2C_FORCE_DM_PULLDOWN BIT(21) |
| 87 | #define P2C_FORCE_DP_PULLDOWN BIT(20) |
| 88 | #define P2C_FORCE_XCVRSEL BIT(19) |
| 89 | #define P2C_FORCE_SUSPENDM BIT(18) |
| 90 | #define P2C_FORCE_TERMSEL BIT(17) |
| 91 | #define P2C_RG_DATAIN GENMASK(13, 10) |
developer | 8a17d5f | 2020-05-02 11:35:15 +0200 | [diff] [blame] | 92 | #define P2C_RG_DMPULLDOWN BIT(7) |
| 93 | #define P2C_RG_DPPULLDOWN BIT(6) |
| 94 | #define P2C_RG_XCVRSEL GENMASK(5, 4) |
developer | 8a17d5f | 2020-05-02 11:35:15 +0200 | [diff] [blame] | 95 | #define P2C_RG_SUSPENDM BIT(3) |
| 96 | #define P2C_RG_TERMSEL BIT(2) |
| 97 | #define P2C_DTM0_PART_MASK \ |
| 98 | (P2C_FORCE_DATAIN | P2C_FORCE_DM_PULLDOWN | \ |
| 99 | P2C_FORCE_DP_PULLDOWN | P2C_FORCE_XCVRSEL | \ |
| 100 | P2C_FORCE_TERMSEL | P2C_RG_DMPULLDOWN | \ |
| 101 | P2C_RG_DPPULLDOWN | P2C_RG_TERMSEL) |
| 102 | |
| 103 | #define U3P_U2PHYDTM1 0x06C |
| 104 | #define P2C_RG_UART_EN BIT(16) |
| 105 | #define P2C_FORCE_IDDIG BIT(9) |
| 106 | #define P2C_RG_VBUSVALID BIT(5) |
| 107 | #define P2C_RG_SESSEND BIT(4) |
| 108 | #define P2C_RG_AVALID BIT(2) |
| 109 | #define P2C_RG_IDDIG BIT(1) |
| 110 | |
developer | 7b27b8d | 2019-08-22 12:26:50 +0200 | [diff] [blame] | 111 | #define U3P_U3_CHIP_GPIO_CTLD 0x0c |
| 112 | #define P3C_REG_IP_SW_RST BIT(31) |
| 113 | #define P3C_MCU_BUS_CK_GATE_EN BIT(30) |
| 114 | #define P3C_FORCE_IP_SW_RST BIT(29) |
| 115 | |
| 116 | #define U3P_U3_CHIP_GPIO_CTLE 0x10 |
| 117 | #define P3C_RG_SWRST_U3_PHYD BIT(25) |
| 118 | #define P3C_RG_SWRST_U3_PHYD_FORCE_EN BIT(24) |
| 119 | |
| 120 | #define U3P_U3_PHYA_REG0 0x000 |
| 121 | #define P3A_RG_CLKDRV_OFF GENMASK(3, 2) |
developer | 7b27b8d | 2019-08-22 12:26:50 +0200 | [diff] [blame] | 122 | |
| 123 | #define U3P_U3_PHYA_REG1 0x004 |
| 124 | #define P3A_RG_CLKDRV_AMP GENMASK(31, 29) |
developer | 7b27b8d | 2019-08-22 12:26:50 +0200 | [diff] [blame] | 125 | |
developer | 8a17d5f | 2020-05-02 11:35:15 +0200 | [diff] [blame] | 126 | #define U3P_U3_PHYA_REG6 0x018 |
| 127 | #define P3A_RG_TX_EIDLE_CM GENMASK(31, 28) |
developer | 8a17d5f | 2020-05-02 11:35:15 +0200 | [diff] [blame] | 128 | |
| 129 | #define U3P_U3_PHYA_REG9 0x024 |
| 130 | #define P3A_RG_RX_DAC_MUX GENMASK(5, 1) |
developer | 8a17d5f | 2020-05-02 11:35:15 +0200 | [diff] [blame] | 131 | |
developer | 7b27b8d | 2019-08-22 12:26:50 +0200 | [diff] [blame] | 132 | #define U3P_U3_PHYA_DA_REG0 0x100 |
| 133 | #define P3A_RG_XTAL_EXT_PE2H GENMASK(17, 16) |
developer | 7b27b8d | 2019-08-22 12:26:50 +0200 | [diff] [blame] | 134 | #define P3A_RG_XTAL_EXT_PE1H GENMASK(13, 12) |
developer | 7b27b8d | 2019-08-22 12:26:50 +0200 | [diff] [blame] | 135 | #define P3A_RG_XTAL_EXT_EN_U3 GENMASK(11, 10) |
developer | 7b27b8d | 2019-08-22 12:26:50 +0200 | [diff] [blame] | 136 | |
| 137 | #define U3P_U3_PHYA_DA_REG4 0x108 |
| 138 | #define P3A_RG_PLL_DIVEN_PE2H GENMASK(21, 19) |
| 139 | #define P3A_RG_PLL_BC_PE2H GENMASK(7, 6) |
developer | 7b27b8d | 2019-08-22 12:26:50 +0200 | [diff] [blame] | 140 | |
| 141 | #define U3P_U3_PHYA_DA_REG5 0x10c |
| 142 | #define P3A_RG_PLL_BR_PE2H GENMASK(29, 28) |
developer | 7b27b8d | 2019-08-22 12:26:50 +0200 | [diff] [blame] | 143 | #define P3A_RG_PLL_IC_PE2H GENMASK(15, 12) |
developer | 7b27b8d | 2019-08-22 12:26:50 +0200 | [diff] [blame] | 144 | |
| 145 | #define U3P_U3_PHYA_DA_REG6 0x110 |
| 146 | #define P3A_RG_PLL_IR_PE2H GENMASK(19, 16) |
developer | 7b27b8d | 2019-08-22 12:26:50 +0200 | [diff] [blame] | 147 | |
| 148 | #define U3P_U3_PHYA_DA_REG7 0x114 |
| 149 | #define P3A_RG_PLL_BP_PE2H GENMASK(19, 16) |
developer | 7b27b8d | 2019-08-22 12:26:50 +0200 | [diff] [blame] | 150 | |
| 151 | #define U3P_U3_PHYA_DA_REG20 0x13c |
| 152 | #define P3A_RG_PLL_DELTA1_PE2H GENMASK(31, 16) |
developer | 7b27b8d | 2019-08-22 12:26:50 +0200 | [diff] [blame] | 153 | |
| 154 | #define U3P_U3_PHYA_DA_REG25 0x148 |
| 155 | #define P3A_RG_PLL_DELTA_PE2H GENMASK(15, 0) |
developer | 7b27b8d | 2019-08-22 12:26:50 +0200 | [diff] [blame] | 156 | |
developer | 8a17d5f | 2020-05-02 11:35:15 +0200 | [diff] [blame] | 157 | #define U3P_U3_PHYD_LFPS1 0x00c |
| 158 | #define P3D_RG_FWAKE_TH GENMASK(21, 16) |
developer | 8a17d5f | 2020-05-02 11:35:15 +0200 | [diff] [blame] | 159 | |
| 160 | #define U3P_U3_PHYD_CDR1 0x05c |
| 161 | #define P3D_RG_CDR_BIR_LTD1 GENMASK(28, 24) |
developer | 8a17d5f | 2020-05-02 11:35:15 +0200 | [diff] [blame] | 162 | #define P3D_RG_CDR_BIR_LTD0 GENMASK(12, 8) |
developer | 8a17d5f | 2020-05-02 11:35:15 +0200 | [diff] [blame] | 163 | |
developer | 7b27b8d | 2019-08-22 12:26:50 +0200 | [diff] [blame] | 164 | #define U3P_U3_PHYD_RXDET1 0x128 |
| 165 | #define P3D_RG_RXDET_STB2_SET GENMASK(17, 9) |
developer | 7b27b8d | 2019-08-22 12:26:50 +0200 | [diff] [blame] | 166 | |
| 167 | #define U3P_U3_PHYD_RXDET2 0x12c |
| 168 | #define P3D_RG_RXDET_STB2_SET_P3 GENMASK(8, 0) |
developer | 7b27b8d | 2019-08-22 12:26:50 +0200 | [diff] [blame] | 169 | |
developer | 8a17d5f | 2020-05-02 11:35:15 +0200 | [diff] [blame] | 170 | #define U3P_SPLLC_XTALCTL3 0x018 |
| 171 | #define XC3_RG_U3_XTAL_RX_PWD BIT(9) |
| 172 | #define XC3_RG_U3_FRC_XTAL_RX_PWD BIT(8) |
| 173 | |
Frank Wunderlich | e84a29f | 2020-08-13 10:20:45 +0200 | [diff] [blame] | 174 | /* SATA register setting */ |
| 175 | #define PHYD_CTRL_SIGNAL_MODE4 0x1c |
| 176 | /* CDR Charge Pump P-path current adjustment */ |
| 177 | #define RG_CDR_BICLTD1_GEN1_MSK GENMASK(23, 20) |
Frank Wunderlich | e84a29f | 2020-08-13 10:20:45 +0200 | [diff] [blame] | 178 | #define RG_CDR_BICLTD0_GEN1_MSK GENMASK(11, 8) |
Frank Wunderlich | e84a29f | 2020-08-13 10:20:45 +0200 | [diff] [blame] | 179 | |
| 180 | #define PHYD_DESIGN_OPTION2 0x24 |
| 181 | /* Symbol lock count selection */ |
| 182 | #define RG_LOCK_CNT_SEL_MSK GENMASK(5, 4) |
Frank Wunderlich | e84a29f | 2020-08-13 10:20:45 +0200 | [diff] [blame] | 183 | |
| 184 | #define PHYD_DESIGN_OPTION9 0x40 |
| 185 | /* COMWAK GAP width window */ |
| 186 | #define RG_TG_MAX_MSK GENMASK(20, 16) |
Frank Wunderlich | e84a29f | 2020-08-13 10:20:45 +0200 | [diff] [blame] | 187 | /* COMINIT GAP width window */ |
| 188 | #define RG_T2_MAX_MSK GENMASK(13, 8) |
Frank Wunderlich | e84a29f | 2020-08-13 10:20:45 +0200 | [diff] [blame] | 189 | /* COMWAK GAP width window */ |
| 190 | #define RG_TG_MIN_MSK GENMASK(7, 5) |
Frank Wunderlich | e84a29f | 2020-08-13 10:20:45 +0200 | [diff] [blame] | 191 | /* COMINIT GAP width window */ |
| 192 | #define RG_T2_MIN_MSK GENMASK(4, 0) |
Frank Wunderlich | e84a29f | 2020-08-13 10:20:45 +0200 | [diff] [blame] | 193 | |
| 194 | #define ANA_RG_CTRL_SIGNAL1 0x4c |
| 195 | /* TX driver tail current control for 0dB de-empahsis mdoe for Gen1 speed */ |
| 196 | #define RG_IDRV_0DB_GEN1_MSK GENMASK(13, 8) |
Frank Wunderlich | e84a29f | 2020-08-13 10:20:45 +0200 | [diff] [blame] | 197 | |
| 198 | #define ANA_RG_CTRL_SIGNAL4 0x58 |
| 199 | #define RG_CDR_BICLTR_GEN1_MSK GENMASK(23, 20) |
Frank Wunderlich | e84a29f | 2020-08-13 10:20:45 +0200 | [diff] [blame] | 200 | /* Loop filter R1 resistance adjustment for Gen1 speed */ |
| 201 | #define RG_CDR_BR_GEN2_MSK GENMASK(10, 8) |
Frank Wunderlich | e84a29f | 2020-08-13 10:20:45 +0200 | [diff] [blame] | 202 | |
| 203 | #define ANA_RG_CTRL_SIGNAL6 0x60 |
| 204 | /* I-path capacitance adjustment for Gen1 */ |
| 205 | #define RG_CDR_BC_GEN1_MSK GENMASK(28, 24) |
Frank Wunderlich | e84a29f | 2020-08-13 10:20:45 +0200 | [diff] [blame] | 206 | #define RG_CDR_BIRLTR_GEN1_MSK GENMASK(4, 0) |
Frank Wunderlich | e84a29f | 2020-08-13 10:20:45 +0200 | [diff] [blame] | 207 | |
| 208 | #define ANA_EQ_EYE_CTRL_SIGNAL1 0x6c |
| 209 | /* RX Gen1 LEQ tuning step */ |
| 210 | #define RG_EQ_DLEQ_LFI_GEN1_MSK GENMASK(11, 8) |
Frank Wunderlich | e84a29f | 2020-08-13 10:20:45 +0200 | [diff] [blame] | 211 | |
| 212 | #define ANA_EQ_EYE_CTRL_SIGNAL4 0xd8 |
| 213 | #define RG_CDR_BIRLTD0_GEN1_MSK GENMASK(20, 16) |
Frank Wunderlich | e84a29f | 2020-08-13 10:20:45 +0200 | [diff] [blame] | 214 | |
| 215 | #define ANA_EQ_EYE_CTRL_SIGNAL5 0xdc |
| 216 | #define RG_CDR_BIRLTD0_GEN3_MSK GENMASK(4, 0) |
Frank Wunderlich | e84a29f | 2020-08-13 10:20:45 +0200 | [diff] [blame] | 217 | |
developer | 8b30260 | 2020-05-02 11:35:16 +0200 | [diff] [blame] | 218 | enum mtk_phy_version { |
| 219 | MTK_TPHY_V1 = 1, |
| 220 | MTK_TPHY_V2, |
| 221 | }; |
| 222 | |
developer | 53cecc0 | 2023-02-17 17:04:09 +0800 | [diff] [blame] | 223 | struct tphy_pdata { |
| 224 | enum mtk_phy_version version; |
| 225 | |
| 226 | /* |
| 227 | * workaround only for mt8195: |
| 228 | * u2phy should use integer mode instead of fractional mode of |
| 229 | * 48M PLL, fix it by switching PLL to 26M from default 48M |
| 230 | */ |
| 231 | bool sw_pll_48m_to_26m; |
| 232 | }; |
| 233 | |
developer | 8a17d5f | 2020-05-02 11:35:15 +0200 | [diff] [blame] | 234 | struct u2phy_banks { |
| 235 | void __iomem *misc; |
| 236 | void __iomem *fmreg; |
| 237 | void __iomem *com; |
| 238 | }; |
| 239 | |
developer | 7b27b8d | 2019-08-22 12:26:50 +0200 | [diff] [blame] | 240 | struct u3phy_banks { |
| 241 | void __iomem *spllc; |
| 242 | void __iomem *chip; |
| 243 | void __iomem *phyd; /* include u3phyd_bank2 */ |
| 244 | void __iomem *phya; /* include u3phya_da */ |
| 245 | }; |
| 246 | |
| 247 | struct mtk_phy_instance { |
| 248 | void __iomem *port_base; |
developer | 9a9c334 | 2023-12-13 14:41:34 +0800 | [diff] [blame] | 249 | struct device_node *np; |
developer | 8a17d5f | 2020-05-02 11:35:15 +0200 | [diff] [blame] | 250 | union { |
| 251 | struct u2phy_banks u2_banks; |
| 252 | struct u3phy_banks u3_banks; |
| 253 | }; |
developer | 7b27b8d | 2019-08-22 12:26:50 +0200 | [diff] [blame] | 254 | |
developer | 54acbc3 | 2020-05-02 11:35:17 +0200 | [diff] [blame] | 255 | struct clk ref_clk; /* reference clock of (digital) phy */ |
| 256 | struct clk da_ref_clk; /* reference clock of analog phy */ |
developer | 7b27b8d | 2019-08-22 12:26:50 +0200 | [diff] [blame] | 257 | u32 index; |
developer | 8a17d5f | 2020-05-02 11:35:15 +0200 | [diff] [blame] | 258 | u32 type; |
developer | 9a9c334 | 2023-12-13 14:41:34 +0800 | [diff] [blame] | 259 | |
| 260 | u32 eye_vrt; |
| 261 | u32 eye_term; |
| 262 | u32 discth; |
| 263 | u32 pre_emphasis; |
developer | 7b27b8d | 2019-08-22 12:26:50 +0200 | [diff] [blame] | 264 | }; |
| 265 | |
| 266 | struct mtk_tphy { |
developer | 8a17d5f | 2020-05-02 11:35:15 +0200 | [diff] [blame] | 267 | struct udevice *dev; |
developer | 7b27b8d | 2019-08-22 12:26:50 +0200 | [diff] [blame] | 268 | void __iomem *sif_base; |
developer | 53cecc0 | 2023-02-17 17:04:09 +0800 | [diff] [blame] | 269 | const struct tphy_pdata *pdata; |
developer | 7b27b8d | 2019-08-22 12:26:50 +0200 | [diff] [blame] | 270 | struct mtk_phy_instance **phys; |
| 271 | int nphys; |
| 272 | }; |
| 273 | |
developer | 53cecc0 | 2023-02-17 17:04:09 +0800 | [diff] [blame] | 274 | /* workaround only for mt8195 */ |
| 275 | static void u2_phy_pll_26m_set(struct mtk_tphy *tphy, |
| 276 | struct mtk_phy_instance *instance) |
| 277 | { |
| 278 | struct u2phy_banks *u2_banks = &instance->u2_banks; |
| 279 | |
| 280 | if (!tphy->pdata->sw_pll_48m_to_26m) |
| 281 | return; |
| 282 | |
| 283 | clrsetbits_le32(u2_banks->com + U3P_USBPHYACR0, PA0_USB20_PLL_PREDIV, |
| 284 | FIELD_PREP(PA0_USB20_PLL_PREDIV, 0)); |
| 285 | |
| 286 | clrsetbits_le32(u2_banks->com + U3P_USBPHYACR2, PA2_RG_U2PLL_BW, |
| 287 | FIELD_PREP(PA2_RG_U2PLL_BW, 3)); |
| 288 | |
| 289 | writel(P2R_RG_U2PLL_FBDIV_26M, u2_banks->com + U3P_U2PHYA_RESV); |
| 290 | |
| 291 | setbits_le32(u2_banks->com + U3P_U2PHYA_RESV1, |
| 292 | P2R_RG_U2PLL_FRA_EN | P2R_RG_U2PLL_REFCLK_SEL); |
| 293 | } |
| 294 | |
developer | 8a17d5f | 2020-05-02 11:35:15 +0200 | [diff] [blame] | 295 | static void u2_phy_instance_init(struct mtk_tphy *tphy, |
| 296 | struct mtk_phy_instance *instance) |
| 297 | { |
| 298 | struct u2phy_banks *u2_banks = &instance->u2_banks; |
| 299 | |
| 300 | /* switch to USB function, and enable usb pll */ |
| 301 | clrsetbits_le32(u2_banks->com + U3P_U2PHYDTM0, |
| 302 | P2C_FORCE_UART_EN | P2C_FORCE_SUSPENDM, |
developer | ad4890f | 2023-02-17 17:04:08 +0800 | [diff] [blame] | 303 | FIELD_PREP(P2C_RG_XCVRSEL, 1) | |
| 304 | FIELD_PREP(P2C_RG_DATAIN, 0)); |
developer | 8a17d5f | 2020-05-02 11:35:15 +0200 | [diff] [blame] | 305 | |
| 306 | clrbits_le32(u2_banks->com + U3P_U2PHYDTM1, P2C_RG_UART_EN); |
| 307 | setbits_le32(u2_banks->com + U3P_USBPHYACR0, PA0_RG_USB20_INTR_EN); |
| 308 | |
| 309 | /* disable switch 100uA current to SSUSB */ |
| 310 | clrbits_le32(u2_banks->com + U3P_USBPHYACR5, PA5_RG_U2_HS_100U_U3_EN); |
| 311 | |
| 312 | clrbits_le32(u2_banks->com + U3P_U2PHYACR4, P2C_U2_GPIO_CTR_MSK); |
| 313 | |
| 314 | /* DP/DM BC1.1 path Disable */ |
| 315 | clrsetbits_le32(u2_banks->com + U3P_USBPHYACR6, |
| 316 | PA6_RG_U2_BC11_SW_EN | PA6_RG_U2_SQTH, |
developer | ad4890f | 2023-02-17 17:04:08 +0800 | [diff] [blame] | 317 | FIELD_PREP(PA6_RG_U2_SQTH, 2)); |
developer | 8a17d5f | 2020-05-02 11:35:15 +0200 | [diff] [blame] | 318 | |
| 319 | /* set HS slew rate */ |
| 320 | clrsetbits_le32(u2_banks->com + U3P_USBPHYACR5, |
developer | ad4890f | 2023-02-17 17:04:08 +0800 | [diff] [blame] | 321 | PA5_RG_U2_HSTX_SRCTRL, |
| 322 | FIELD_PREP(PA5_RG_U2_HSTX_SRCTRL, 4)); |
developer | 8a17d5f | 2020-05-02 11:35:15 +0200 | [diff] [blame] | 323 | |
developer | 53cecc0 | 2023-02-17 17:04:09 +0800 | [diff] [blame] | 324 | u2_phy_pll_26m_set(tphy, instance); |
| 325 | |
developer | 8a17d5f | 2020-05-02 11:35:15 +0200 | [diff] [blame] | 326 | dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index); |
| 327 | } |
| 328 | |
| 329 | static void u2_phy_instance_power_on(struct mtk_tphy *tphy, |
| 330 | struct mtk_phy_instance *instance) |
| 331 | { |
| 332 | struct u2phy_banks *u2_banks = &instance->u2_banks; |
| 333 | |
| 334 | clrbits_le32(u2_banks->com + U3P_U2PHYDTM0, |
| 335 | P2C_RG_XCVRSEL | P2C_RG_DATAIN | P2C_DTM0_PART_MASK); |
| 336 | |
| 337 | /* OTG Enable */ |
| 338 | setbits_le32(u2_banks->com + U3P_USBPHYACR6, |
| 339 | PA6_RG_U2_OTG_VBUSCMP_EN); |
| 340 | |
| 341 | clrsetbits_le32(u2_banks->com + U3P_U2PHYDTM1, |
| 342 | P2C_RG_SESSEND, P2C_RG_VBUSVALID | P2C_RG_AVALID); |
| 343 | |
| 344 | dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index); |
| 345 | } |
| 346 | |
| 347 | static void u2_phy_instance_power_off(struct mtk_tphy *tphy, |
| 348 | struct mtk_phy_instance *instance) |
| 349 | { |
| 350 | struct u2phy_banks *u2_banks = &instance->u2_banks; |
| 351 | |
| 352 | clrbits_le32(u2_banks->com + U3P_U2PHYDTM0, |
| 353 | P2C_RG_XCVRSEL | P2C_RG_DATAIN); |
| 354 | |
| 355 | /* OTG Disable */ |
| 356 | clrbits_le32(u2_banks->com + U3P_USBPHYACR6, |
| 357 | PA6_RG_U2_OTG_VBUSCMP_EN); |
| 358 | |
| 359 | clrsetbits_le32(u2_banks->com + U3P_U2PHYDTM1, |
| 360 | P2C_RG_VBUSVALID | P2C_RG_AVALID, P2C_RG_SESSEND); |
| 361 | |
| 362 | dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index); |
| 363 | } |
| 364 | |
| 365 | static void u3_phy_instance_init(struct mtk_tphy *tphy, |
| 366 | struct mtk_phy_instance *instance) |
| 367 | { |
| 368 | struct u3phy_banks *u3_banks = &instance->u3_banks; |
| 369 | |
| 370 | /* gating PCIe Analog XTAL clock */ |
| 371 | setbits_le32(u3_banks->spllc + U3P_SPLLC_XTALCTL3, |
| 372 | XC3_RG_U3_XTAL_RX_PWD | XC3_RG_U3_FRC_XTAL_RX_PWD); |
| 373 | |
| 374 | /* gating XSQ */ |
| 375 | clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG0, |
developer | ad4890f | 2023-02-17 17:04:08 +0800 | [diff] [blame] | 376 | P3A_RG_XTAL_EXT_EN_U3, |
| 377 | FIELD_PREP(P3A_RG_XTAL_EXT_EN_U3, 2)); |
developer | 8a17d5f | 2020-05-02 11:35:15 +0200 | [diff] [blame] | 378 | |
| 379 | clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_REG9, |
developer | ad4890f | 2023-02-17 17:04:08 +0800 | [diff] [blame] | 380 | P3A_RG_RX_DAC_MUX, FIELD_PREP(P3A_RG_RX_DAC_MUX, 4)); |
developer | 8a17d5f | 2020-05-02 11:35:15 +0200 | [diff] [blame] | 381 | |
| 382 | clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_REG6, |
developer | ad4890f | 2023-02-17 17:04:08 +0800 | [diff] [blame] | 383 | P3A_RG_TX_EIDLE_CM, |
| 384 | FIELD_PREP(P3A_RG_TX_EIDLE_CM, 0xe)); |
developer | 8a17d5f | 2020-05-02 11:35:15 +0200 | [diff] [blame] | 385 | |
| 386 | clrsetbits_le32(u3_banks->phyd + U3P_U3_PHYD_CDR1, |
| 387 | P3D_RG_CDR_BIR_LTD0 | P3D_RG_CDR_BIR_LTD1, |
developer | ad4890f | 2023-02-17 17:04:08 +0800 | [diff] [blame] | 388 | FIELD_PREP(P3D_RG_CDR_BIR_LTD0, 0xc) | |
| 389 | FIELD_PREP(P3D_RG_CDR_BIR_LTD1, 0x3)); |
developer | 8a17d5f | 2020-05-02 11:35:15 +0200 | [diff] [blame] | 390 | |
| 391 | clrsetbits_le32(u3_banks->phyd + U3P_U3_PHYD_LFPS1, |
developer | ad4890f | 2023-02-17 17:04:08 +0800 | [diff] [blame] | 392 | P3D_RG_FWAKE_TH, FIELD_PREP(P3D_RG_FWAKE_TH, 0x34)); |
developer | 8a17d5f | 2020-05-02 11:35:15 +0200 | [diff] [blame] | 393 | |
| 394 | clrsetbits_le32(u3_banks->phyd + U3P_U3_PHYD_RXDET1, |
developer | ad4890f | 2023-02-17 17:04:08 +0800 | [diff] [blame] | 395 | P3D_RG_RXDET_STB2_SET, |
| 396 | FIELD_PREP(P3D_RG_RXDET_STB2_SET, 0x10)); |
developer | 8a17d5f | 2020-05-02 11:35:15 +0200 | [diff] [blame] | 397 | |
| 398 | clrsetbits_le32(u3_banks->phyd + U3P_U3_PHYD_RXDET2, |
| 399 | P3D_RG_RXDET_STB2_SET_P3, |
developer | ad4890f | 2023-02-17 17:04:08 +0800 | [diff] [blame] | 400 | FIELD_PREP(P3D_RG_RXDET_STB2_SET_P3, 0x10)); |
developer | 8a17d5f | 2020-05-02 11:35:15 +0200 | [diff] [blame] | 401 | |
| 402 | dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index); |
| 403 | } |
| 404 | |
developer | 7b27b8d | 2019-08-22 12:26:50 +0200 | [diff] [blame] | 405 | static void pcie_phy_instance_init(struct mtk_tphy *tphy, |
| 406 | struct mtk_phy_instance *instance) |
| 407 | { |
| 408 | struct u3phy_banks *u3_banks = &instance->u3_banks; |
| 409 | |
developer | 53cecc0 | 2023-02-17 17:04:09 +0800 | [diff] [blame] | 410 | if (tphy->pdata->version != MTK_TPHY_V1) |
developer | 8b30260 | 2020-05-02 11:35:16 +0200 | [diff] [blame] | 411 | return; |
| 412 | |
developer | 7b27b8d | 2019-08-22 12:26:50 +0200 | [diff] [blame] | 413 | clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG0, |
| 414 | P3A_RG_XTAL_EXT_PE1H | P3A_RG_XTAL_EXT_PE2H, |
developer | ad4890f | 2023-02-17 17:04:08 +0800 | [diff] [blame] | 415 | FIELD_PREP(P3A_RG_XTAL_EXT_PE1H, 0x2) | |
| 416 | FIELD_PREP(P3A_RG_XTAL_EXT_PE2H, 0x2)); |
developer | 7b27b8d | 2019-08-22 12:26:50 +0200 | [diff] [blame] | 417 | |
| 418 | /* ref clk drive */ |
| 419 | clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_REG1, P3A_RG_CLKDRV_AMP, |
developer | ad4890f | 2023-02-17 17:04:08 +0800 | [diff] [blame] | 420 | FIELD_PREP(P3A_RG_CLKDRV_AMP, 0x4)); |
developer | 7b27b8d | 2019-08-22 12:26:50 +0200 | [diff] [blame] | 421 | clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_REG0, P3A_RG_CLKDRV_OFF, |
developer | ad4890f | 2023-02-17 17:04:08 +0800 | [diff] [blame] | 422 | FIELD_PREP(P3A_RG_CLKDRV_OFF, 0x1)); |
developer | 7b27b8d | 2019-08-22 12:26:50 +0200 | [diff] [blame] | 423 | |
| 424 | /* SSC delta -5000ppm */ |
| 425 | clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG20, |
| 426 | P3A_RG_PLL_DELTA1_PE2H, |
developer | ad4890f | 2023-02-17 17:04:08 +0800 | [diff] [blame] | 427 | FIELD_PREP(P3A_RG_PLL_DELTA1_PE2H, 0x3c)); |
developer | 7b27b8d | 2019-08-22 12:26:50 +0200 | [diff] [blame] | 428 | |
| 429 | clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG25, |
| 430 | P3A_RG_PLL_DELTA_PE2H, |
developer | ad4890f | 2023-02-17 17:04:08 +0800 | [diff] [blame] | 431 | FIELD_PREP(P3A_RG_PLL_DELTA_PE2H, 0x36)); |
developer | 7b27b8d | 2019-08-22 12:26:50 +0200 | [diff] [blame] | 432 | |
| 433 | /* change pll BW 0.6M */ |
| 434 | clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG5, |
| 435 | P3A_RG_PLL_BR_PE2H | P3A_RG_PLL_IC_PE2H, |
developer | ad4890f | 2023-02-17 17:04:08 +0800 | [diff] [blame] | 436 | FIELD_PREP(P3A_RG_PLL_BR_PE2H, 0x1) | |
| 437 | FIELD_PREP(P3A_RG_PLL_IC_PE2H, 0x1)); |
developer | 7b27b8d | 2019-08-22 12:26:50 +0200 | [diff] [blame] | 438 | clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG4, |
| 439 | P3A_RG_PLL_DIVEN_PE2H | P3A_RG_PLL_BC_PE2H, |
developer | ad4890f | 2023-02-17 17:04:08 +0800 | [diff] [blame] | 440 | FIELD_PREP(P3A_RG_PLL_BC_PE2H, 0x3)); |
developer | 7b27b8d | 2019-08-22 12:26:50 +0200 | [diff] [blame] | 441 | |
| 442 | clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG6, |
developer | ad4890f | 2023-02-17 17:04:08 +0800 | [diff] [blame] | 443 | P3A_RG_PLL_IR_PE2H, |
| 444 | FIELD_PREP(P3A_RG_PLL_IR_PE2H, 0x2)); |
developer | 7b27b8d | 2019-08-22 12:26:50 +0200 | [diff] [blame] | 445 | clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG7, |
developer | ad4890f | 2023-02-17 17:04:08 +0800 | [diff] [blame] | 446 | P3A_RG_PLL_BP_PE2H, |
| 447 | FIELD_PREP(P3A_RG_PLL_BP_PE2H, 0xa)); |
developer | 7b27b8d | 2019-08-22 12:26:50 +0200 | [diff] [blame] | 448 | |
| 449 | /* Tx Detect Rx Timing: 10us -> 5us */ |
| 450 | clrsetbits_le32(u3_banks->phyd + U3P_U3_PHYD_RXDET1, |
| 451 | P3D_RG_RXDET_STB2_SET, |
developer | ad4890f | 2023-02-17 17:04:08 +0800 | [diff] [blame] | 452 | FIELD_PREP(P3D_RG_RXDET_STB2_SET, 0x10)); |
developer | 7b27b8d | 2019-08-22 12:26:50 +0200 | [diff] [blame] | 453 | clrsetbits_le32(u3_banks->phyd + U3P_U3_PHYD_RXDET2, |
| 454 | P3D_RG_RXDET_STB2_SET_P3, |
developer | ad4890f | 2023-02-17 17:04:08 +0800 | [diff] [blame] | 455 | FIELD_PREP(P3D_RG_RXDET_STB2_SET_P3, 0x10)); |
developer | 7b27b8d | 2019-08-22 12:26:50 +0200 | [diff] [blame] | 456 | |
| 457 | /* wait for PCIe subsys register to active */ |
| 458 | udelay(3000); |
| 459 | } |
| 460 | |
Frank Wunderlich | e84a29f | 2020-08-13 10:20:45 +0200 | [diff] [blame] | 461 | static void sata_phy_instance_init(struct mtk_tphy *tphy, |
| 462 | struct mtk_phy_instance *instance) |
| 463 | { |
| 464 | struct u3phy_banks *u3_banks = &instance->u3_banks; |
| 465 | |
| 466 | clrsetbits_le32(u3_banks->phyd + ANA_RG_CTRL_SIGNAL6, |
| 467 | RG_CDR_BIRLTR_GEN1_MSK | RG_CDR_BC_GEN1_MSK, |
developer | ad4890f | 2023-02-17 17:04:08 +0800 | [diff] [blame] | 468 | FIELD_PREP(RG_CDR_BIRLTR_GEN1_MSK, 0x6) | |
| 469 | FIELD_PREP(RG_CDR_BC_GEN1_MSK, 0x1a)); |
Frank Wunderlich | e84a29f | 2020-08-13 10:20:45 +0200 | [diff] [blame] | 470 | clrsetbits_le32(u3_banks->phyd + ANA_EQ_EYE_CTRL_SIGNAL4, |
| 471 | RG_CDR_BIRLTD0_GEN1_MSK, |
developer | ad4890f | 2023-02-17 17:04:08 +0800 | [diff] [blame] | 472 | FIELD_PREP(RG_CDR_BIRLTD0_GEN1_MSK, 0x18)); |
Frank Wunderlich | e84a29f | 2020-08-13 10:20:45 +0200 | [diff] [blame] | 473 | clrsetbits_le32(u3_banks->phyd + ANA_EQ_EYE_CTRL_SIGNAL5, |
| 474 | RG_CDR_BIRLTD0_GEN3_MSK, |
developer | ad4890f | 2023-02-17 17:04:08 +0800 | [diff] [blame] | 475 | FIELD_PREP(RG_CDR_BIRLTD0_GEN3_MSK, 0x06)); |
Frank Wunderlich | e84a29f | 2020-08-13 10:20:45 +0200 | [diff] [blame] | 476 | clrsetbits_le32(u3_banks->phyd + ANA_RG_CTRL_SIGNAL4, |
| 477 | RG_CDR_BICLTR_GEN1_MSK | RG_CDR_BR_GEN2_MSK, |
developer | ad4890f | 2023-02-17 17:04:08 +0800 | [diff] [blame] | 478 | FIELD_PREP(RG_CDR_BICLTR_GEN1_MSK, 0x0c) | |
| 479 | FIELD_PREP(RG_CDR_BR_GEN2_MSK, 0x07)); |
Frank Wunderlich | e84a29f | 2020-08-13 10:20:45 +0200 | [diff] [blame] | 480 | clrsetbits_le32(u3_banks->phyd + PHYD_CTRL_SIGNAL_MODE4, |
| 481 | RG_CDR_BICLTD0_GEN1_MSK | RG_CDR_BICLTD1_GEN1_MSK, |
developer | ad4890f | 2023-02-17 17:04:08 +0800 | [diff] [blame] | 482 | FIELD_PREP(RG_CDR_BICLTD0_GEN1_MSK, 0x08) | |
| 483 | FIELD_PREP(RG_CDR_BICLTD1_GEN1_MSK, 0x02)); |
Frank Wunderlich | e84a29f | 2020-08-13 10:20:45 +0200 | [diff] [blame] | 484 | clrsetbits_le32(u3_banks->phyd + PHYD_DESIGN_OPTION2, |
| 485 | RG_LOCK_CNT_SEL_MSK, |
developer | ad4890f | 2023-02-17 17:04:08 +0800 | [diff] [blame] | 486 | FIELD_PREP(RG_LOCK_CNT_SEL_MSK, 0x02)); |
Frank Wunderlich | e84a29f | 2020-08-13 10:20:45 +0200 | [diff] [blame] | 487 | clrsetbits_le32(u3_banks->phyd + PHYD_DESIGN_OPTION9, |
| 488 | RG_T2_MIN_MSK | RG_TG_MIN_MSK | |
| 489 | RG_T2_MAX_MSK | RG_TG_MAX_MSK, |
developer | ad4890f | 2023-02-17 17:04:08 +0800 | [diff] [blame] | 490 | FIELD_PREP(RG_T2_MIN_MSK, 0x12) | |
| 491 | FIELD_PREP(RG_TG_MIN_MSK, 0x04) | |
| 492 | FIELD_PREP(RG_T2_MAX_MSK, 0x31) | |
| 493 | FIELD_PREP(RG_TG_MAX_MSK, 0x0e)); |
Frank Wunderlich | e84a29f | 2020-08-13 10:20:45 +0200 | [diff] [blame] | 494 | clrsetbits_le32(u3_banks->phyd + ANA_RG_CTRL_SIGNAL1, |
| 495 | RG_IDRV_0DB_GEN1_MSK, |
developer | ad4890f | 2023-02-17 17:04:08 +0800 | [diff] [blame] | 496 | FIELD_PREP(RG_IDRV_0DB_GEN1_MSK, 0x20)); |
Frank Wunderlich | e84a29f | 2020-08-13 10:20:45 +0200 | [diff] [blame] | 497 | clrsetbits_le32(u3_banks->phyd + ANA_EQ_EYE_CTRL_SIGNAL1, |
| 498 | RG_EQ_DLEQ_LFI_GEN1_MSK, |
developer | ad4890f | 2023-02-17 17:04:08 +0800 | [diff] [blame] | 499 | FIELD_PREP(RG_EQ_DLEQ_LFI_GEN1_MSK, 0x03)); |
Frank Wunderlich | e84a29f | 2020-08-13 10:20:45 +0200 | [diff] [blame] | 500 | } |
| 501 | |
developer | 7b27b8d | 2019-08-22 12:26:50 +0200 | [diff] [blame] | 502 | static void pcie_phy_instance_power_on(struct mtk_tphy *tphy, |
| 503 | struct mtk_phy_instance *instance) |
| 504 | { |
| 505 | struct u3phy_banks *bank = &instance->u3_banks; |
| 506 | |
| 507 | clrbits_le32(bank->chip + U3P_U3_CHIP_GPIO_CTLD, |
| 508 | P3C_FORCE_IP_SW_RST | P3C_REG_IP_SW_RST); |
| 509 | clrbits_le32(bank->chip + U3P_U3_CHIP_GPIO_CTLE, |
| 510 | P3C_RG_SWRST_U3_PHYD_FORCE_EN | P3C_RG_SWRST_U3_PHYD); |
| 511 | } |
| 512 | |
| 513 | static void pcie_phy_instance_power_off(struct mtk_tphy *tphy, |
| 514 | struct mtk_phy_instance *instance) |
| 515 | |
| 516 | { |
| 517 | struct u3phy_banks *bank = &instance->u3_banks; |
| 518 | |
| 519 | setbits_le32(bank->chip + U3P_U3_CHIP_GPIO_CTLD, |
| 520 | P3C_FORCE_IP_SW_RST | P3C_REG_IP_SW_RST); |
| 521 | setbits_le32(bank->chip + U3P_U3_CHIP_GPIO_CTLE, |
| 522 | P3C_RG_SWRST_U3_PHYD_FORCE_EN | P3C_RG_SWRST_U3_PHYD); |
| 523 | } |
| 524 | |
| 525 | static void phy_v1_banks_init(struct mtk_tphy *tphy, |
| 526 | struct mtk_phy_instance *instance) |
| 527 | { |
developer | 8a17d5f | 2020-05-02 11:35:15 +0200 | [diff] [blame] | 528 | struct u2phy_banks *u2_banks = &instance->u2_banks; |
developer | 7b27b8d | 2019-08-22 12:26:50 +0200 | [diff] [blame] | 529 | struct u3phy_banks *u3_banks = &instance->u3_banks; |
| 530 | |
| 531 | switch (instance->type) { |
developer | 8a17d5f | 2020-05-02 11:35:15 +0200 | [diff] [blame] | 532 | case PHY_TYPE_USB2: |
| 533 | u2_banks->misc = NULL; |
| 534 | u2_banks->fmreg = tphy->sif_base + SSUSB_SIFSLV_V1_U2FREQ; |
| 535 | u2_banks->com = instance->port_base + SSUSB_SIFSLV_V1_U2PHY_COM; |
| 536 | break; |
| 537 | case PHY_TYPE_USB3: |
developer | 7b27b8d | 2019-08-22 12:26:50 +0200 | [diff] [blame] | 538 | case PHY_TYPE_PCIE: |
| 539 | u3_banks->spllc = tphy->sif_base + SSUSB_SIFSLV_V1_SPLLC; |
| 540 | u3_banks->chip = tphy->sif_base + SSUSB_SIFSLV_V1_CHIP; |
| 541 | u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V1_U3PHYD; |
| 542 | u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V1_U3PHYA; |
| 543 | break; |
Frank Wunderlich | e84a29f | 2020-08-13 10:20:45 +0200 | [diff] [blame] | 544 | case PHY_TYPE_SATA: |
| 545 | u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V1_U3PHYD; |
| 546 | break; |
developer | 7b27b8d | 2019-08-22 12:26:50 +0200 | [diff] [blame] | 547 | default: |
developer | 8a17d5f | 2020-05-02 11:35:15 +0200 | [diff] [blame] | 548 | dev_err(tphy->dev, "incompatible PHY type\n"); |
developer | 7b27b8d | 2019-08-22 12:26:50 +0200 | [diff] [blame] | 549 | return; |
| 550 | } |
| 551 | } |
| 552 | |
developer | 8b30260 | 2020-05-02 11:35:16 +0200 | [diff] [blame] | 553 | static void phy_v2_banks_init(struct mtk_tphy *tphy, |
| 554 | struct mtk_phy_instance *instance) |
| 555 | { |
| 556 | struct u2phy_banks *u2_banks = &instance->u2_banks; |
| 557 | struct u3phy_banks *u3_banks = &instance->u3_banks; |
| 558 | |
| 559 | switch (instance->type) { |
| 560 | case PHY_TYPE_USB2: |
| 561 | u2_banks->misc = instance->port_base + SSUSB_SIFSLV_V2_MISC; |
| 562 | u2_banks->fmreg = instance->port_base + SSUSB_SIFSLV_V2_U2FREQ; |
| 563 | u2_banks->com = instance->port_base + SSUSB_SIFSLV_V2_U2PHY_COM; |
| 564 | break; |
| 565 | case PHY_TYPE_USB3: |
| 566 | case PHY_TYPE_PCIE: |
| 567 | u3_banks->spllc = instance->port_base + SSUSB_SIFSLV_V2_SPLLC; |
| 568 | u3_banks->chip = instance->port_base + SSUSB_SIFSLV_V2_CHIP; |
| 569 | u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V2_U3PHYD; |
| 570 | u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V2_U3PHYA; |
| 571 | break; |
| 572 | default: |
| 573 | dev_err(tphy->dev, "incompatible PHY type\n"); |
| 574 | return; |
| 575 | } |
| 576 | } |
| 577 | |
developer | 9a9c334 | 2023-12-13 14:41:34 +0800 | [diff] [blame] | 578 | static void phy_parse_property(struct mtk_tphy *tphy, |
| 579 | struct mtk_phy_instance *instance) |
| 580 | { |
| 581 | ofnode node = np_to_ofnode(instance->np); |
| 582 | |
| 583 | if (instance->type != PHY_TYPE_USB2) |
| 584 | return; |
| 585 | |
| 586 | ofnode_read_u32(node, "mediatek,eye-vrt", &instance->eye_vrt); |
| 587 | ofnode_read_u32(node, "mediatek,eye-term", &instance->eye_term); |
| 588 | ofnode_read_u32(node, "mediatek,discth", &instance->discth); |
| 589 | ofnode_read_u32(node, "mediatek,pre-emphasis", &instance->pre_emphasis); |
| 590 | |
| 591 | dev_dbg(tphy->dev, "vrt:%d, term:%d, disc:%d, emp:%d\n", |
| 592 | instance->eye_vrt, instance->eye_term, |
| 593 | instance->discth, instance->pre_emphasis); |
| 594 | } |
| 595 | |
| 596 | static void u2_phy_props_set(struct mtk_tphy *tphy, |
| 597 | struct mtk_phy_instance *instance) |
| 598 | { |
| 599 | struct u2phy_banks *u2_banks = &instance->u2_banks; |
| 600 | void __iomem *com = u2_banks->com; |
| 601 | |
| 602 | if (instance->eye_vrt) |
| 603 | clrsetbits_le32(com + U3P_USBPHYACR1, PA1_RG_VRT_SEL, |
| 604 | FIELD_PREP(PA1_RG_VRT_SEL, instance->eye_vrt)); |
| 605 | |
| 606 | if (instance->eye_term) |
| 607 | clrsetbits_le32(com + U3P_USBPHYACR1, PA1_RG_TERM_SEL, |
| 608 | FIELD_PREP(PA1_RG_TERM_SEL, instance->eye_term)); |
| 609 | |
| 610 | if (instance->discth) |
| 611 | clrsetbits_le32(com + U3P_USBPHYACR6, PA6_RG_U2_DISCTH, |
| 612 | FIELD_PREP(PA6_RG_U2_DISCTH, instance->discth)); |
| 613 | |
| 614 | if (instance->pre_emphasis) |
| 615 | clrsetbits_le32(com + U3P_USBPHYACR6, PA6_RG_U2_PRE_EMP, |
| 616 | FIELD_PREP(PA6_RG_U2_PRE_EMP, instance->pre_emphasis)); |
| 617 | } |
| 618 | |
developer | 7b27b8d | 2019-08-22 12:26:50 +0200 | [diff] [blame] | 619 | static int mtk_phy_init(struct phy *phy) |
| 620 | { |
| 621 | struct mtk_tphy *tphy = dev_get_priv(phy->dev); |
| 622 | struct mtk_phy_instance *instance = tphy->phys[phy->id]; |
| 623 | int ret; |
| 624 | |
developer | 7b27b8d | 2019-08-22 12:26:50 +0200 | [diff] [blame] | 625 | ret = clk_enable(&instance->ref_clk); |
developer | 54acbc3 | 2020-05-02 11:35:17 +0200 | [diff] [blame] | 626 | if (ret < 0) { |
| 627 | dev_err(tphy->dev, "failed to enable ref_clk\n"); |
developer | 7b27b8d | 2019-08-22 12:26:50 +0200 | [diff] [blame] | 628 | return ret; |
developer | 54acbc3 | 2020-05-02 11:35:17 +0200 | [diff] [blame] | 629 | } |
| 630 | |
| 631 | ret = clk_enable(&instance->da_ref_clk); |
| 632 | if (ret < 0) { |
| 633 | dev_err(tphy->dev, "failed to enable da_ref_clk %d\n", ret); |
| 634 | clk_disable(&instance->ref_clk); |
| 635 | return ret; |
| 636 | } |
developer | 7b27b8d | 2019-08-22 12:26:50 +0200 | [diff] [blame] | 637 | |
| 638 | switch (instance->type) { |
developer | 8a17d5f | 2020-05-02 11:35:15 +0200 | [diff] [blame] | 639 | case PHY_TYPE_USB2: |
| 640 | u2_phy_instance_init(tphy, instance); |
developer | 9a9c334 | 2023-12-13 14:41:34 +0800 | [diff] [blame] | 641 | u2_phy_props_set(tphy, instance); |
developer | 8a17d5f | 2020-05-02 11:35:15 +0200 | [diff] [blame] | 642 | break; |
| 643 | case PHY_TYPE_USB3: |
| 644 | u3_phy_instance_init(tphy, instance); |
| 645 | break; |
developer | 7b27b8d | 2019-08-22 12:26:50 +0200 | [diff] [blame] | 646 | case PHY_TYPE_PCIE: |
| 647 | pcie_phy_instance_init(tphy, instance); |
| 648 | break; |
Frank Wunderlich | e84a29f | 2020-08-13 10:20:45 +0200 | [diff] [blame] | 649 | case PHY_TYPE_SATA: |
| 650 | sata_phy_instance_init(tphy, instance); |
| 651 | break; |
developer | 7b27b8d | 2019-08-22 12:26:50 +0200 | [diff] [blame] | 652 | default: |
developer | 8a17d5f | 2020-05-02 11:35:15 +0200 | [diff] [blame] | 653 | dev_err(tphy->dev, "incompatible PHY type\n"); |
developer | 7b27b8d | 2019-08-22 12:26:50 +0200 | [diff] [blame] | 654 | return -EINVAL; |
| 655 | } |
| 656 | |
| 657 | return 0; |
| 658 | } |
| 659 | |
| 660 | static int mtk_phy_power_on(struct phy *phy) |
| 661 | { |
| 662 | struct mtk_tphy *tphy = dev_get_priv(phy->dev); |
| 663 | struct mtk_phy_instance *instance = tphy->phys[phy->id]; |
| 664 | |
developer | 8a17d5f | 2020-05-02 11:35:15 +0200 | [diff] [blame] | 665 | if (instance->type == PHY_TYPE_USB2) |
| 666 | u2_phy_instance_power_on(tphy, instance); |
| 667 | else if (instance->type == PHY_TYPE_PCIE) |
| 668 | pcie_phy_instance_power_on(tphy, instance); |
developer | 7b27b8d | 2019-08-22 12:26:50 +0200 | [diff] [blame] | 669 | |
| 670 | return 0; |
| 671 | } |
| 672 | |
| 673 | static int mtk_phy_power_off(struct phy *phy) |
| 674 | { |
| 675 | struct mtk_tphy *tphy = dev_get_priv(phy->dev); |
| 676 | struct mtk_phy_instance *instance = tphy->phys[phy->id]; |
| 677 | |
developer | 8a17d5f | 2020-05-02 11:35:15 +0200 | [diff] [blame] | 678 | if (instance->type == PHY_TYPE_USB2) |
| 679 | u2_phy_instance_power_off(tphy, instance); |
| 680 | else if (instance->type == PHY_TYPE_PCIE) |
| 681 | pcie_phy_instance_power_off(tphy, instance); |
developer | 7b27b8d | 2019-08-22 12:26:50 +0200 | [diff] [blame] | 682 | |
| 683 | return 0; |
| 684 | } |
| 685 | |
| 686 | static int mtk_phy_exit(struct phy *phy) |
| 687 | { |
| 688 | struct mtk_tphy *tphy = dev_get_priv(phy->dev); |
| 689 | struct mtk_phy_instance *instance = tphy->phys[phy->id]; |
| 690 | |
developer | 54acbc3 | 2020-05-02 11:35:17 +0200 | [diff] [blame] | 691 | clk_disable(&instance->da_ref_clk); |
developer | 7b27b8d | 2019-08-22 12:26:50 +0200 | [diff] [blame] | 692 | clk_disable(&instance->ref_clk); |
| 693 | |
| 694 | return 0; |
| 695 | } |
| 696 | |
| 697 | static int mtk_phy_xlate(struct phy *phy, |
| 698 | struct ofnode_phandle_args *args) |
| 699 | { |
| 700 | struct mtk_tphy *tphy = dev_get_priv(phy->dev); |
| 701 | struct mtk_phy_instance *instance = NULL; |
| 702 | const struct device_node *phy_np = ofnode_to_np(args->node); |
| 703 | u32 index; |
| 704 | |
| 705 | if (!phy_np) { |
| 706 | dev_err(phy->dev, "null pointer phy node\n"); |
| 707 | return -EINVAL; |
| 708 | } |
| 709 | |
| 710 | if (args->args_count < 1) { |
| 711 | dev_err(phy->dev, "invalid number of cells in 'phy' property\n"); |
| 712 | return -EINVAL; |
| 713 | } |
| 714 | |
| 715 | for (index = 0; index < tphy->nphys; index++) |
| 716 | if (phy_np == tphy->phys[index]->np) { |
| 717 | instance = tphy->phys[index]; |
| 718 | break; |
| 719 | } |
| 720 | |
| 721 | if (!instance) { |
| 722 | dev_err(phy->dev, "failed to find appropriate phy\n"); |
| 723 | return -EINVAL; |
| 724 | } |
| 725 | |
| 726 | phy->id = index; |
| 727 | instance->type = args->args[1]; |
| 728 | if (!(instance->type == PHY_TYPE_USB2 || |
| 729 | instance->type == PHY_TYPE_USB3 || |
Frank Wunderlich | e84a29f | 2020-08-13 10:20:45 +0200 | [diff] [blame] | 730 | instance->type == PHY_TYPE_SATA || |
developer | 8a17d5f | 2020-05-02 11:35:15 +0200 | [diff] [blame] | 731 | instance->type == PHY_TYPE_PCIE)) { |
developer | 7b27b8d | 2019-08-22 12:26:50 +0200 | [diff] [blame] | 732 | dev_err(phy->dev, "unsupported device type\n"); |
| 733 | return -EINVAL; |
| 734 | } |
| 735 | |
developer | 53cecc0 | 2023-02-17 17:04:09 +0800 | [diff] [blame] | 736 | switch (tphy->pdata->version) { |
| 737 | case MTK_TPHY_V1: |
developer | 8b30260 | 2020-05-02 11:35:16 +0200 | [diff] [blame] | 738 | phy_v1_banks_init(tphy, instance); |
developer | 53cecc0 | 2023-02-17 17:04:09 +0800 | [diff] [blame] | 739 | break; |
| 740 | case MTK_TPHY_V2: |
developer | 8b30260 | 2020-05-02 11:35:16 +0200 | [diff] [blame] | 741 | phy_v2_banks_init(tphy, instance); |
developer | 53cecc0 | 2023-02-17 17:04:09 +0800 | [diff] [blame] | 742 | break; |
| 743 | default: |
developer | 8b30260 | 2020-05-02 11:35:16 +0200 | [diff] [blame] | 744 | dev_err(phy->dev, "phy version is not supported\n"); |
| 745 | return -EINVAL; |
| 746 | } |
developer | 7b27b8d | 2019-08-22 12:26:50 +0200 | [diff] [blame] | 747 | |
developer | 9a9c334 | 2023-12-13 14:41:34 +0800 | [diff] [blame] | 748 | phy_parse_property(tphy, instance); |
| 749 | |
developer | 7b27b8d | 2019-08-22 12:26:50 +0200 | [diff] [blame] | 750 | return 0; |
| 751 | } |
| 752 | |
| 753 | static const struct phy_ops mtk_tphy_ops = { |
| 754 | .init = mtk_phy_init, |
| 755 | .exit = mtk_phy_exit, |
| 756 | .power_on = mtk_phy_power_on, |
| 757 | .power_off = mtk_phy_power_off, |
| 758 | .of_xlate = mtk_phy_xlate, |
| 759 | }; |
| 760 | |
| 761 | static int mtk_tphy_probe(struct udevice *dev) |
| 762 | { |
| 763 | struct mtk_tphy *tphy = dev_get_priv(dev); |
| 764 | ofnode subnode; |
| 765 | int index = 0; |
| 766 | |
developer | 8a17d5f | 2020-05-02 11:35:15 +0200 | [diff] [blame] | 767 | tphy->nphys = dev_get_child_count(dev); |
developer | 7b27b8d | 2019-08-22 12:26:50 +0200 | [diff] [blame] | 768 | |
| 769 | tphy->phys = devm_kcalloc(dev, tphy->nphys, sizeof(*tphy->phys), |
| 770 | GFP_KERNEL); |
| 771 | if (!tphy->phys) |
| 772 | return -ENOMEM; |
| 773 | |
developer | 8a17d5f | 2020-05-02 11:35:15 +0200 | [diff] [blame] | 774 | tphy->dev = dev; |
developer | 53cecc0 | 2023-02-17 17:04:09 +0800 | [diff] [blame] | 775 | tphy->pdata = (void *)dev_get_driver_data(dev); |
developer | 8b30260 | 2020-05-02 11:35:16 +0200 | [diff] [blame] | 776 | |
Frank Wunderlich | 6acdc95 | 2020-08-20 16:37:52 +0200 | [diff] [blame] | 777 | /* v1 has shared banks for usb/pcie mode, */ |
| 778 | /* but not for sata mode */ |
developer | 53cecc0 | 2023-02-17 17:04:09 +0800 | [diff] [blame] | 779 | if (tphy->pdata->version == MTK_TPHY_V1) |
developer | 8b30260 | 2020-05-02 11:35:16 +0200 | [diff] [blame] | 780 | tphy->sif_base = dev_read_addr_ptr(dev); |
developer | 7b27b8d | 2019-08-22 12:26:50 +0200 | [diff] [blame] | 781 | |
| 782 | dev_for_each_subnode(subnode, dev) { |
| 783 | struct mtk_phy_instance *instance; |
| 784 | fdt_addr_t addr; |
| 785 | int err; |
| 786 | |
| 787 | instance = devm_kzalloc(dev, sizeof(*instance), GFP_KERNEL); |
| 788 | if (!instance) |
| 789 | return -ENOMEM; |
| 790 | |
| 791 | addr = ofnode_get_addr(subnode); |
| 792 | if (addr == FDT_ADDR_T_NONE) |
| 793 | return -ENOMEM; |
| 794 | |
| 795 | instance->port_base = map_sysmem(addr, 0); |
| 796 | instance->index = index; |
| 797 | instance->np = ofnode_to_np(subnode); |
| 798 | tphy->phys[index] = instance; |
| 799 | index++; |
| 800 | |
Sean Anderson | d7e85d5 | 2021-12-22 12:11:10 -0500 | [diff] [blame] | 801 | err = clk_get_by_name_nodev_optional(subnode, "ref", |
| 802 | &instance->ref_clk); |
developer | 7b27b8d | 2019-08-22 12:26:50 +0200 | [diff] [blame] | 803 | if (err) |
| 804 | return err; |
developer | 54acbc3 | 2020-05-02 11:35:17 +0200 | [diff] [blame] | 805 | |
Sean Anderson | d7e85d5 | 2021-12-22 12:11:10 -0500 | [diff] [blame] | 806 | err = clk_get_by_name_nodev_optional(subnode, "da_ref", |
| 807 | &instance->da_ref_clk); |
developer | 54acbc3 | 2020-05-02 11:35:17 +0200 | [diff] [blame] | 808 | if (err) |
| 809 | return err; |
developer | 7b27b8d | 2019-08-22 12:26:50 +0200 | [diff] [blame] | 810 | } |
| 811 | |
| 812 | return 0; |
| 813 | } |
| 814 | |
developer | 53cecc0 | 2023-02-17 17:04:09 +0800 | [diff] [blame] | 815 | static struct tphy_pdata tphy_v1_pdata = { |
| 816 | .version = MTK_TPHY_V1, |
| 817 | }; |
| 818 | |
| 819 | static struct tphy_pdata tphy_v2_pdata = { |
| 820 | .version = MTK_TPHY_V2, |
| 821 | }; |
| 822 | |
| 823 | static struct tphy_pdata mt8195_pdata = { |
| 824 | .version = MTK_TPHY_V2, |
| 825 | .sw_pll_48m_to_26m = true, |
| 826 | }; |
| 827 | |
developer | 7b27b8d | 2019-08-22 12:26:50 +0200 | [diff] [blame] | 828 | static const struct udevice_id mtk_tphy_id_table[] = { |
developer | 53cecc0 | 2023-02-17 17:04:09 +0800 | [diff] [blame] | 829 | { |
| 830 | .compatible = "mediatek,generic-tphy-v1", |
| 831 | .data = (ulong)&tphy_v1_pdata, |
| 832 | }, |
| 833 | { |
| 834 | .compatible = "mediatek,generic-tphy-v2", |
| 835 | .data = (ulong)&tphy_v2_pdata, |
| 836 | }, |
| 837 | { |
| 838 | .compatible = "mediatek,mt8195-tphy", |
| 839 | .data = (ulong)&mt8195_pdata, |
| 840 | }, |
developer | 7b27b8d | 2019-08-22 12:26:50 +0200 | [diff] [blame] | 841 | { } |
| 842 | }; |
| 843 | |
| 844 | U_BOOT_DRIVER(mtk_tphy) = { |
| 845 | .name = "mtk-tphy", |
| 846 | .id = UCLASS_PHY, |
| 847 | .of_match = mtk_tphy_id_table, |
| 848 | .ops = &mtk_tphy_ops, |
| 849 | .probe = mtk_tphy_probe, |
Simon Glass | 8a2b47f | 2020-12-03 16:55:17 -0700 | [diff] [blame] | 850 | .priv_auto = sizeof(struct mtk_tphy), |
developer | 7b27b8d | 2019-08-22 12:26:50 +0200 | [diff] [blame] | 851 | }; |