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git01.mediatek.com / filogic / uboot / 324cb4d73d2883138305686b6f013e9e84de580d / . / board / renesas / koelsch / qos.c
blob: ee893510060af3732a6377dfa40a1496ed14b71b [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]2/*
3 * board/renesas/koelsch/qos.c
4 *
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]5 * Copyright (C) 2013,2014 Renesas Electronics Corporation
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]6 *
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]7 */
8
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]9#include <asm/processor.h>
10#include <asm/mach-types.h>
11#include <asm/io.h>
Marek Vasut97a070b2024-02-27 17:05:54 +0100[diff] [blame]12#include <asm/arch/renesas.h>
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]13
Nobuhiro Iwamatsuc0db8962015-03-05 08:30:38 +0900[diff] [blame]14/* QoS version 0.240 for ES1 and version 0.411 for ES2 */
Marek Vasutd26aa8c2024-02-27 17:05:53 +0100[diff] [blame]15#if defined(CONFIG_RENESAS_EXTRAM_BOOT)
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]16enum {
17 DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04,
18 DBSC3_05, DBSC3_06, DBSC3_07, DBSC3_08, DBSC3_09,
19 DBSC3_10, DBSC3_11, DBSC3_12, DBSC3_13, DBSC3_14,
20 DBSC3_15,
21 DBSC3_NR,
22};
23
24static u32 dbsc3_0_r_qos_addr[DBSC3_NR] = {
25 [DBSC3_00] = DBSC3_0_QOS_R0_BASE,
26 [DBSC3_01] = DBSC3_0_QOS_R1_BASE,
27 [DBSC3_02] = DBSC3_0_QOS_R2_BASE,
28 [DBSC3_03] = DBSC3_0_QOS_R3_BASE,
29 [DBSC3_04] = DBSC3_0_QOS_R4_BASE,
30 [DBSC3_05] = DBSC3_0_QOS_R5_BASE,
31 [DBSC3_06] = DBSC3_0_QOS_R6_BASE,
32 [DBSC3_07] = DBSC3_0_QOS_R7_BASE,
33 [DBSC3_08] = DBSC3_0_QOS_R8_BASE,
34 [DBSC3_09] = DBSC3_0_QOS_R9_BASE,
35 [DBSC3_10] = DBSC3_0_QOS_R10_BASE,
36 [DBSC3_11] = DBSC3_0_QOS_R11_BASE,
37 [DBSC3_12] = DBSC3_0_QOS_R12_BASE,
38 [DBSC3_13] = DBSC3_0_QOS_R13_BASE,
39 [DBSC3_14] = DBSC3_0_QOS_R14_BASE,
40 [DBSC3_15] = DBSC3_0_QOS_R15_BASE,
41};
42
43static u32 dbsc3_0_w_qos_addr[DBSC3_NR] = {
44 [DBSC3_00] = DBSC3_0_QOS_W0_BASE,
45 [DBSC3_01] = DBSC3_0_QOS_W1_BASE,
46 [DBSC3_02] = DBSC3_0_QOS_W2_BASE,
47 [DBSC3_03] = DBSC3_0_QOS_W3_BASE,
48 [DBSC3_04] = DBSC3_0_QOS_W4_BASE,
49 [DBSC3_05] = DBSC3_0_QOS_W5_BASE,
50 [DBSC3_06] = DBSC3_0_QOS_W6_BASE,
51 [DBSC3_07] = DBSC3_0_QOS_W7_BASE,
52 [DBSC3_08] = DBSC3_0_QOS_W8_BASE,
53 [DBSC3_09] = DBSC3_0_QOS_W9_BASE,
54 [DBSC3_10] = DBSC3_0_QOS_W10_BASE,
55 [DBSC3_11] = DBSC3_0_QOS_W11_BASE,
56 [DBSC3_12] = DBSC3_0_QOS_W12_BASE,
57 [DBSC3_13] = DBSC3_0_QOS_W13_BASE,
58 [DBSC3_14] = DBSC3_0_QOS_W14_BASE,
59 [DBSC3_15] = DBSC3_0_QOS_W15_BASE,
60};
61
62static u32 dbsc3_1_r_qos_addr[DBSC3_NR] = {
63 [DBSC3_00] = DBSC3_1_QOS_R0_BASE,
64 [DBSC3_01] = DBSC3_1_QOS_R1_BASE,
65 [DBSC3_02] = DBSC3_1_QOS_R2_BASE,
66 [DBSC3_03] = DBSC3_1_QOS_R3_BASE,
67 [DBSC3_04] = DBSC3_1_QOS_R4_BASE,
68 [DBSC3_05] = DBSC3_1_QOS_R5_BASE,
69 [DBSC3_06] = DBSC3_1_QOS_R6_BASE,
70 [DBSC3_07] = DBSC3_1_QOS_R7_BASE,
71 [DBSC3_08] = DBSC3_1_QOS_R8_BASE,
72 [DBSC3_09] = DBSC3_1_QOS_R9_BASE,
73 [DBSC3_10] = DBSC3_1_QOS_R10_BASE,
74 [DBSC3_11] = DBSC3_1_QOS_R11_BASE,
75 [DBSC3_12] = DBSC3_1_QOS_R12_BASE,
76 [DBSC3_13] = DBSC3_1_QOS_R13_BASE,
77 [DBSC3_14] = DBSC3_1_QOS_R14_BASE,
78 [DBSC3_15] = DBSC3_1_QOS_R15_BASE,
79};
80
81static u32 dbsc3_1_w_qos_addr[DBSC3_NR] = {
82 [DBSC3_00] = DBSC3_1_QOS_W0_BASE,
83 [DBSC3_01] = DBSC3_1_QOS_W1_BASE,
84 [DBSC3_02] = DBSC3_1_QOS_W2_BASE,
85 [DBSC3_03] = DBSC3_1_QOS_W3_BASE,
86 [DBSC3_04] = DBSC3_1_QOS_W4_BASE,
87 [DBSC3_05] = DBSC3_1_QOS_W5_BASE,
88 [DBSC3_06] = DBSC3_1_QOS_W6_BASE,
89 [DBSC3_07] = DBSC3_1_QOS_W7_BASE,
90 [DBSC3_08] = DBSC3_1_QOS_W8_BASE,
91 [DBSC3_09] = DBSC3_1_QOS_W9_BASE,
92 [DBSC3_10] = DBSC3_1_QOS_W10_BASE,
93 [DBSC3_11] = DBSC3_1_QOS_W11_BASE,
94 [DBSC3_12] = DBSC3_1_QOS_W12_BASE,
95 [DBSC3_13] = DBSC3_1_QOS_W13_BASE,
96 [DBSC3_14] = DBSC3_1_QOS_W14_BASE,
97 [DBSC3_15] = DBSC3_1_QOS_W15_BASE,
98};
99
Nobuhiro Iwamatsuc0db8962015-03-05 08:30:38 +0900[diff] [blame]100#if defined(CONFIG_QOS_PRI_MEDIA)
101#define is_qos_pri_media() 1
102#else
103#define is_qos_pri_media() 0
104#endif
105
106#if defined(CONFIG_QOS_PRI_NORMAL)
107#define is_qos_pri_normal() 1
108#else
109#define is_qos_pri_normal() 0
110#endif
111
112#if defined(CONFIG_QOS_PRI_GFX)
113#define is_qos_pri_gfx() 1
114#else
115#define is_qos_pri_gfx() 0
116#endif
117
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]118void qos_init(void)
119{
120 int i;
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]121 struct rcar_s3c *s3c;
122 struct rcar_s3c_qos *s3c_qos;
123 struct rcar_dbsc3_qos *qos_addr;
124 struct rcar_mxi *mxi;
125 struct rcar_mxi_qos *mxi_qos;
126 struct rcar_axi_qos *axi_qos;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]127
128 /* DBSC DBADJ2 */
129 writel(0x20042004, DBSC3_0_DBADJ2);
Nobuhiro Iwamatsu747a3ad2014-05-19 12:23:35 +0900[diff] [blame]130 writel(0x20042004, DBSC3_1_DBADJ2);
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]131
132 /* S3C -QoS */
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]133 s3c = (struct rcar_s3c *)S3C_BASE;
Nobuhiro Iwamatsuf70251a2014-04-02 11:50:37 +0900[diff] [blame]134 if (IS_R8A7791_ES2()) {
Nobuhiro Iwamatsuf0508aa2014-07-24 15:28:04 +0900[diff] [blame]135 /* Linear All mode */
136 /* writel(0x00000000, &s3c->s3cadsplcr); */
137 /* Linear Linear 0x7000 to 0x7800 mode */
138 writel(0x00BF1B0C, &s3c->s3cadsplcr);
139 /* Split Linear 0x6800 t 0x7000 mode */
140 /* writel(0x00DF1B0C, &s3c->s3cadsplcr); */
141 /* Ssplit All mode */
142 /* writel(0x00FF1B0C, &s3c->s3cadsplcr); */
Nobuhiro Iwamatsuc0db8962015-03-05 08:30:38 +0900[diff] [blame]143
144 if (is_qos_pri_media()) {
145 writel(0x1F0B0604, &s3c->s3crorr);
146 writel(0x1F0E0705, &s3c->s3cworr);
147 } else if (is_qos_pri_normal()) {
148 writel(0x1F0B0908, &s3c->s3crorr);
149 writel(0x1F0E0A08, &s3c->s3cworr);
150 } else if (is_qos_pri_gfx()) {
151 writel(0x1F0B0B0B, &s3c->s3crorr);
152 writel(0x1F0E0C0C, &s3c->s3cworr);
153 }
Nobuhiro Iwamatsuf70251a2014-04-02 11:50:37 +0900[diff] [blame]154 } else {
155 writel(0x00FF1B1D, &s3c->s3cadsplcr);
156 writel(0x1F0D0C0C, &s3c->s3crorr);
157 writel(0x1F0D0C0A, &s3c->s3cworr);
158 }
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]159 /* QoS Control Registers */
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]160 s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI0_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]161 writel(0x00890089, &s3c_qos->s3cqos0);
162 writel(0x20960010, &s3c_qos->s3cqos1);
163 writel(0x20302030, &s3c_qos->s3cqos2);
Nobuhiro Iwamatsuc0db8962015-03-05 08:30:38 +0900[diff] [blame]164
165 if (IS_R8A7791_ES2()) {
166 if (is_qos_pri_media())
167 writel(0x20AA2300, &s3c_qos->s3cqos3);
168 else if (is_qos_pri_normal())
169 writel(0x20AA2200, &s3c_qos->s3cqos3);
170 else if (is_qos_pri_gfx())
171 writel(0x20AA2100, &s3c_qos->s3cqos3);
172 } else {
173 writel(0x20AA2200, &s3c_qos->s3cqos3);
174 }
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]175 writel(0x00002032, &s3c_qos->s3cqos4);
176 writel(0x20960010, &s3c_qos->s3cqos5);
177 writel(0x20302030, &s3c_qos->s3cqos6);
Nobuhiro Iwamatsuc0db8962015-03-05 08:30:38 +0900[diff] [blame]178
179 if (IS_R8A7791_ES2()) {
180 if (is_qos_pri_media())
181 writel(0x20AA2300, &s3c_qos->s3cqos7);
182 else if (is_qos_pri_normal())
183 writel(0x20AA2200, &s3c_qos->s3cqos7);
184 else if (is_qos_pri_gfx())
185 writel(0x20AA2100, &s3c_qos->s3cqos7);
186 } else {
187 writel(0x20AA2200, &s3c_qos->s3cqos7);
188 }
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]189 writel(0x00002032, &s3c_qos->s3cqos8);
190
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]191 s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI1_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]192 writel(0x00890089, &s3c_qos->s3cqos0);
193 writel(0x20960010, &s3c_qos->s3cqos1);
194 writel(0x20302030, &s3c_qos->s3cqos2);
Nobuhiro Iwamatsuc0db8962015-03-05 08:30:38 +0900[diff] [blame]195 if (IS_R8A7791_ES2()) {
196 if (is_qos_pri_media())
197 writel(0x20AA2300, &s3c_qos->s3cqos3);
198 else if (is_qos_pri_normal())
199 writel(0x20AA2200, &s3c_qos->s3cqos3);
200 else if (is_qos_pri_gfx())
201 writel(0x20AA2100, &s3c_qos->s3cqos3);
202 } else {
203 writel(0x20AA2200, &s3c_qos->s3cqos3);
204 }
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]205 writel(0x00002032, &s3c_qos->s3cqos4);
206 writel(0x20960010, &s3c_qos->s3cqos5);
207 writel(0x20302030, &s3c_qos->s3cqos6);
Nobuhiro Iwamatsuc0db8962015-03-05 08:30:38 +0900[diff] [blame]208 if (IS_R8A7791_ES2()) {
209 if (is_qos_pri_media())
210 writel(0x20AA2300, &s3c_qos->s3cqos7);
211 else if (is_qos_pri_normal())
212 writel(0x20AA2200, &s3c_qos->s3cqos7);
213 else if (is_qos_pri_gfx())
214 writel(0x20AA2100, &s3c_qos->s3cqos7);
215 } else {
216 writel(0x20AA2200, &s3c_qos->s3cqos7);
217 }
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]218 writel(0x00002032, &s3c_qos->s3cqos8);
219
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]220 s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_MXI_BASE;
Nobuhiro Iwamatsuc0db8962015-03-05 08:30:38 +0900[diff] [blame]221 if (IS_R8A7791_ES2())
222 writel(0x80928092, &s3c_qos->s3cqos0);
223 else
224 writel(0x00820082, &s3c_qos->s3cqos0);
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]225 writel(0x20960020, &s3c_qos->s3cqos1);
226 writel(0x20302030, &s3c_qos->s3cqos2);
227 writel(0x20AA20DC, &s3c_qos->s3cqos3);
228 writel(0x00002032, &s3c_qos->s3cqos4);
229 writel(0x20960020, &s3c_qos->s3cqos5);
230 writel(0x20302030, &s3c_qos->s3cqos6);
231 writel(0x20AA20DC, &s3c_qos->s3cqos7);
232 writel(0x00002032, &s3c_qos->s3cqos8);
233
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]234 s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_AXI_BASE;
Nobuhiro Iwamatsuc0db8962015-03-05 08:30:38 +0900[diff] [blame]235 if (IS_R8A7791_ES2())
236 writel(0x80928092, &s3c_qos->s3cqos0);
237 else
238 writel(0x00820082, &s3c_qos->s3cqos0);
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]239 writel(0x20960020, &s3c_qos->s3cqos1);
240 writel(0x20302030, &s3c_qos->s3cqos2);
241 writel(0x20AA20FA, &s3c_qos->s3cqos3);
242 writel(0x00002032, &s3c_qos->s3cqos4);
243 writel(0x20960020, &s3c_qos->s3cqos5);
244 writel(0x20302030, &s3c_qos->s3cqos6);
245 writel(0x20AA20FA, &s3c_qos->s3cqos7);
246 writel(0x00002032, &s3c_qos->s3cqos8);
247
248 /* DBSC -QoS */
249 /* DBSC0 - Read */
250 for (i = DBSC3_00; i < DBSC3_NR; i++) {
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]251 qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_r_qos_addr[i];
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]252 writel(0x00000002, &qos_addr->dblgcnt);
253 writel(0x00002096, &qos_addr->dbtmval0);
254 writel(0x00002064, &qos_addr->dbtmval1);
255 writel(0x00002032, &qos_addr->dbtmval2);
256 writel(0x00001FB0, &qos_addr->dbtmval3);
257 writel(0x00000001, &qos_addr->dbrqctr);
258 writel(0x00002078, &qos_addr->dbthres0);
259 writel(0x0000204B, &qos_addr->dbthres1);
Nobuhiro Iwamatsuf0508aa2014-07-24 15:28:04 +0900[diff] [blame]260 writel(0x0000201E, &qos_addr->dbthres2);
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]261 writel(0x00000001, &qos_addr->dblgqon);
262 }
263
264 /* DBSC0 - Write */
265 for (i = DBSC3_00; i < DBSC3_NR; i++) {
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]266 qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_w_qos_addr[i];
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]267 writel(0x00000002, &qos_addr->dblgcnt);
Nobuhiro Iwamatsuf0508aa2014-07-24 15:28:04 +0900[diff] [blame]268 writel(0x00002096, &qos_addr->dbtmval0);
269 writel(0x00002064, &qos_addr->dbtmval1);
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]270 writel(0x00002050, &qos_addr->dbtmval2);
271 writel(0x0000203A, &qos_addr->dbtmval3);
272 writel(0x00000001, &qos_addr->dbrqctr);
273 writel(0x00002078, &qos_addr->dbthres0);
Nobuhiro Iwamatsuf0508aa2014-07-24 15:28:04 +0900[diff] [blame]274 writel(0x0000204B, &qos_addr->dbthres1);
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]275 writel(0x0000203C, &qos_addr->dbthres2);
276 writel(0x00000001, &qos_addr->dblgqon);
277 }
278
279 /* DBSC1 - Read */
280 for (i = DBSC3_00; i < DBSC3_NR; i++) {
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]281 qos_addr = (struct rcar_dbsc3_qos *)dbsc3_1_r_qos_addr[i];
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]282 writel(0x00000002, &qos_addr->dblgcnt);
283 writel(0x00002096, &qos_addr->dbtmval0);
284 writel(0x00002064, &qos_addr->dbtmval1);
285 writel(0x00002032, &qos_addr->dbtmval2);
286 writel(0x00001FB0, &qos_addr->dbtmval3);
287 writel(0x00000001, &qos_addr->dbrqctr);
288 writel(0x00002078, &qos_addr->dbthres0);
289 writel(0x0000204B, &qos_addr->dbthres1);
Nobuhiro Iwamatsuf0508aa2014-07-24 15:28:04 +0900[diff] [blame]290 writel(0x0000201E, &qos_addr->dbthres2);
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]291 writel(0x00000001, &qos_addr->dblgqon);
292 }
293
294 /* DBSC1 - Write */
295 for (i = DBSC3_00; i < DBSC3_NR; i++) {
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]296 qos_addr = (struct rcar_dbsc3_qos *)dbsc3_1_w_qos_addr[i];
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]297 writel(0x00000002, &qos_addr->dblgcnt);
Nobuhiro Iwamatsuf0508aa2014-07-24 15:28:04 +0900[diff] [blame]298 writel(0x00002096, &qos_addr->dbtmval0);
299 writel(0x00002064, &qos_addr->dbtmval1);
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]300 writel(0x00002050, &qos_addr->dbtmval2);
301 writel(0x0000203A, &qos_addr->dbtmval3);
302 writel(0x00000001, &qos_addr->dbrqctr);
303 writel(0x00002078, &qos_addr->dbthres0);
Nobuhiro Iwamatsuf0508aa2014-07-24 15:28:04 +0900[diff] [blame]304 writel(0x0000204B, &qos_addr->dbthres1);
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]305 writel(0x0000203C, &qos_addr->dbthres2);
306 writel(0x00000001, &qos_addr->dblgqon);
307 }
308
Nobuhiro Iwamatsuc5d5c7b2014-04-02 11:51:07 +0900[diff] [blame]309 /* CCI-400 -QoS */
310 writel(0x20001000, CCI_400_MAXOT_1);
311 writel(0x20001000, CCI_400_MAXOT_2);
312 writel(0x0000000C, CCI_400_QOSCNTL_1);
313 writel(0x0000000C, CCI_400_QOSCNTL_2);
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]314
315 /* MXI -QoS */
316 /* Transaction Control (MXI) */
Nobuhiro Iwamatsuc0db8962015-03-05 08:30:38 +0900[diff] [blame]317 mxi = (struct rcar_mxi *)XI_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]318 writel(0x00000013, &mxi->mxrtcr);
Nobuhiro Iwamatsuc0db8962015-03-05 08:30:38 +0900[diff] [blame]319 if (IS_R8A7791_ES2()) {
320 writel(0x00000016, &mxi->mxwtcr);
321 writel(0x00780080, &mxi->mxsaar0);
322 writel(0x02000800, &mxi->mxsaar1);
323 } else {
324 writel(0x00000013, &mxi->mxwtcr);
325 }
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]326
327 /* QoS Control (MXI) */
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]328 mxi_qos = (struct rcar_mxi_qos *)MXI_QOS_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]329 writel(0x0000000C, &mxi_qos->vspdu0);
330 writel(0x0000000C, &mxi_qos->vspdu1);
Nobuhiro Iwamatsuf0508aa2014-07-24 15:28:04 +0900[diff] [blame]331 writel(0x0000000E, &mxi_qos->du0);
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]332 writel(0x0000000D, &mxi_qos->du1);
333
334 /* AXI -QoS */
335 /* Transaction Control (MXI) */
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]336 axi_qos = (struct rcar_axi_qos *)SYS_AXI_SYX64TO128_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]337 writel(0x00000002, &axi_qos->qosconf);
338 writel(0x00002245, &axi_qos->qosctset0);
339 writel(0x00002096, &axi_qos->qosctset1);
340 writel(0x00002030, &axi_qos->qosctset2);
341 writel(0x00002030, &axi_qos->qosctset3);
342 writel(0x00000001, &axi_qos->qosreqctr);
343 writel(0x00002064, &axi_qos->qosthres0);
344 writel(0x00002004, &axi_qos->qosthres1);
345 writel(0x00000000, &axi_qos->qosthres2);
346 writel(0x00000001, &axi_qos->qosqon);
347
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]348 axi_qos = (struct rcar_axi_qos *)SYS_AXI_AVB_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]349 writel(0x00000000, &axi_qos->qosconf);
350 writel(0x000020A6, &axi_qos->qosctset0);
351 writel(0x00000001, &axi_qos->qosreqctr);
352 writel(0x00002064, &axi_qos->qosthres0);
353 writel(0x00002004, &axi_qos->qosthres1);
354 writel(0x00000000, &axi_qos->qosthres2);
355 writel(0x00000001, &axi_qos->qosqon);
356
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]357 axi_qos = (struct rcar_axi_qos *)SYS_AXI_G2D_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]358 writel(0x00000000, &axi_qos->qosconf);
359 writel(0x000020A6, &axi_qos->qosctset0);
360 writel(0x00000001, &axi_qos->qosreqctr);
361 writel(0x00002064, &axi_qos->qosthres0);
362 writel(0x00002004, &axi_qos->qosthres1);
363 writel(0x00000000, &axi_qos->qosthres2);
364 writel(0x00000001, &axi_qos->qosqon);
365
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]366 axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMP0_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]367 writel(0x00000000, &axi_qos->qosconf);
368 writel(0x00002021, &axi_qos->qosctset0);
369 writel(0x00000001, &axi_qos->qosreqctr);
370 writel(0x00002064, &axi_qos->qosthres0);
371 writel(0x00002004, &axi_qos->qosthres1);
372 writel(0x00000000, &axi_qos->qosthres2);
373 writel(0x00000001, &axi_qos->qosqon);
374
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]375 axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMP1_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]376 writel(0x00000000, &axi_qos->qosconf);
377 writel(0x00002037, &axi_qos->qosctset0);
378 writel(0x00000001, &axi_qos->qosreqctr);
379 writel(0x00002064, &axi_qos->qosthres0);
380 writel(0x00002004, &axi_qos->qosthres1);
381 writel(0x00000000, &axi_qos->qosthres2);
382 writel(0x00000001, &axi_qos->qosqon);
383
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]384 axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX0_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]385 writel(0x00000002, &axi_qos->qosconf);
386 writel(0x00002245, &axi_qos->qosctset0);
387 writel(0x00002096, &axi_qos->qosctset1);
388 writel(0x00002030, &axi_qos->qosctset2);
389 writel(0x00002030, &axi_qos->qosctset3);
390 writel(0x00000001, &axi_qos->qosreqctr);
391 writel(0x00002064, &axi_qos->qosthres0);
392 writel(0x00002004, &axi_qos->qosthres1);
393 writel(0x00000000, &axi_qos->qosthres2);
394 writel(0x00000001, &axi_qos->qosqon);
395
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]396 axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX1_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]397 writel(0x00000002, &axi_qos->qosconf);
398 writel(0x00002245, &axi_qos->qosctset0);
399 writel(0x00002096, &axi_qos->qosctset1);
400 writel(0x00002030, &axi_qos->qosctset2);
401 writel(0x00002030, &axi_qos->qosctset3);
402 writel(0x00000001, &axi_qos->qosreqctr);
403 writel(0x00002064, &axi_qos->qosthres0);
404 writel(0x00002004, &axi_qos->qosthres1);
405 writel(0x00000000, &axi_qos->qosthres2);
406 writel(0x00000001, &axi_qos->qosqon);
407
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]408 axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX2_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]409 writel(0x00000002, &axi_qos->qosconf);
410 writel(0x00002245, &axi_qos->qosctset0);
411 writel(0x00002096, &axi_qos->qosctset1);
412 writel(0x00002030, &axi_qos->qosctset2);
413 writel(0x00002030, &axi_qos->qosctset3);
414 writel(0x00000001, &axi_qos->qosreqctr);
415 writel(0x00002064, &axi_qos->qosthres0);
416 writel(0x00002004, &axi_qos->qosthres1);
417 writel(0x00000000, &axi_qos->qosthres2);
418 writel(0x00000001, &axi_qos->qosqon);
419
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]420 axi_qos = (struct rcar_axi_qos *)SYS_AXI_LBS_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]421 writel(0x00000000, &axi_qos->qosconf);
422 writel(0x0000214C, &axi_qos->qosctset0);
423 writel(0x00000001, &axi_qos->qosreqctr);
424 writel(0x00002064, &axi_qos->qosthres0);
425 writel(0x00002004, &axi_qos->qosthres1);
426 writel(0x00000000, &axi_qos->qosthres2);
427 writel(0x00000001, &axi_qos->qosqon);
428
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]429 axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUDS_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]430 writel(0x00000001, &axi_qos->qosconf);
431 writel(0x00002004, &axi_qos->qosctset0);
432 writel(0x00002096, &axi_qos->qosctset1);
433 writel(0x00002030, &axi_qos->qosctset2);
434 writel(0x00002030, &axi_qos->qosctset3);
435 writel(0x00000001, &axi_qos->qosreqctr);
436 writel(0x00002064, &axi_qos->qosthres0);
437 writel(0x00002004, &axi_qos->qosthres1);
438 writel(0x00000000, &axi_qos->qosthres2);
439 writel(0x00000001, &axi_qos->qosqon);
440
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]441 axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUM_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]442 writel(0x00000001, &axi_qos->qosconf);
443 writel(0x00002004, &axi_qos->qosctset0);
444 writel(0x00002096, &axi_qos->qosctset1);
445 writel(0x00002030, &axi_qos->qosctset2);
446 writel(0x00002030, &axi_qos->qosctset3);
447 writel(0x00000001, &axi_qos->qosreqctr);
448 writel(0x00002064, &axi_qos->qosthres0);
449 writel(0x00002004, &axi_qos->qosthres1);
450 writel(0x00000000, &axi_qos->qosthres2);
451 writel(0x00000001, &axi_qos->qosqon);
452
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]453 axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUR_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]454 writel(0x00000001, &axi_qos->qosconf);
455 writel(0x00002004, &axi_qos->qosctset0);
456 writel(0x00002096, &axi_qos->qosctset1);
457 writel(0x00002030, &axi_qos->qosctset2);
458 writel(0x00002030, &axi_qos->qosctset3);
459 writel(0x00000001, &axi_qos->qosreqctr);
460 writel(0x00002064, &axi_qos->qosthres0);
461 writel(0x00002004, &axi_qos->qosthres1);
462 writel(0x00000000, &axi_qos->qosthres2);
463 writel(0x00000001, &axi_qos->qosqon);
464
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]465 axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS0_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]466 writel(0x00000001, &axi_qos->qosconf);
467 writel(0x00002004, &axi_qos->qosctset0);
468 writel(0x00002096, &axi_qos->qosctset1);
469 writel(0x00002030, &axi_qos->qosctset2);
470 writel(0x00002030, &axi_qos->qosctset3);
471 writel(0x00000001, &axi_qos->qosreqctr);
472 writel(0x00002064, &axi_qos->qosthres0);
473 writel(0x00002004, &axi_qos->qosthres1);
474 writel(0x00000000, &axi_qos->qosthres2);
475 writel(0x00000001, &axi_qos->qosqon);
476
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]477 axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS1_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]478 writel(0x00000001, &axi_qos->qosconf);
479 writel(0x00002004, &axi_qos->qosctset0);
480 writel(0x00002096, &axi_qos->qosctset1);
481 writel(0x00002030, &axi_qos->qosctset2);
482 writel(0x00002030, &axi_qos->qosctset3);
483 writel(0x00000001, &axi_qos->qosreqctr);
484 writel(0x00002064, &axi_qos->qosthres0);
485 writel(0x00002004, &axi_qos->qosthres1);
486 writel(0x00000000, &axi_qos->qosthres2);
487 writel(0x00000001, &axi_qos->qosqon);
488
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]489 axi_qos = (struct rcar_axi_qos *)SYS_AXI_MTSB0_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]490 writel(0x00000000, &axi_qos->qosconf);
491 writel(0x00002021, &axi_qos->qosctset0);
492 writel(0x00000001, &axi_qos->qosreqctr);
493 writel(0x00002064, &axi_qos->qosthres0);
494 writel(0x00002004, &axi_qos->qosthres1);
495 writel(0x00000000, &axi_qos->qosthres2);
496 writel(0x00000001, &axi_qos->qosqon);
497
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]498 axi_qos = (struct rcar_axi_qos *)SYS_AXI_MTSB1_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]499 writel(0x00000000, &axi_qos->qosconf);
500 writel(0x00002021, &axi_qos->qosctset0);
501 writel(0x00000001, &axi_qos->qosreqctr);
502 writel(0x00002064, &axi_qos->qosthres0);
503 writel(0x00002004, &axi_qos->qosthres1);
504 writel(0x00000000, &axi_qos->qosthres2);
505 writel(0x00000001, &axi_qos->qosqon);
506
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]507 axi_qos = (struct rcar_axi_qos *)SYS_AXI_PCI_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]508 writel(0x00000000, &axi_qos->qosconf);
509 writel(0x0000214C, &axi_qos->qosctset0);
510 writel(0x00000001, &axi_qos->qosreqctr);
511 writel(0x00002064, &axi_qos->qosthres0);
512 writel(0x00002004, &axi_qos->qosthres1);
513 writel(0x00000000, &axi_qos->qosthres2);
514 writel(0x00000001, &axi_qos->qosqon);
515
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]516 axi_qos = (struct rcar_axi_qos *)SYS_AXI_RTX_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]517 writel(0x00000002, &axi_qos->qosconf);
518 writel(0x00002245, &axi_qos->qosctset0);
519 writel(0x00002096, &axi_qos->qosctset1);
520 writel(0x00002030, &axi_qos->qosctset2);
521 writel(0x00002030, &axi_qos->qosctset3);
522 writel(0x00000001, &axi_qos->qosreqctr);
523 writel(0x00002064, &axi_qos->qosthres0);
524 writel(0x00002004, &axi_qos->qosthres1);
525 writel(0x00000000, &axi_qos->qosthres2);
526 writel(0x00000001, &axi_qos->qosqon);
527
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]528 axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS0_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]529 writel(0x00000000, &axi_qos->qosconf);
530 writel(0x000020A6, &axi_qos->qosctset0);
531 writel(0x00000001, &axi_qos->qosreqctr);
532 writel(0x00002064, &axi_qos->qosthres0);
533 writel(0x00002004, &axi_qos->qosthres1);
534 writel(0x00000000, &axi_qos->qosthres2);
535 writel(0x00000001, &axi_qos->qosqon);
536
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]537 axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS1_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]538 writel(0x00000000, &axi_qos->qosconf);
539 writel(0x000020A6, &axi_qos->qosctset0);
540 writel(0x00000001, &axi_qos->qosreqctr);
541 writel(0x00002064, &axi_qos->qosthres0);
542 writel(0x00002004, &axi_qos->qosthres1);
543 writel(0x00000000, &axi_qos->qosthres2);
544 writel(0x00000001, &axi_qos->qosqon);
545
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]546 axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB20_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]547 writel(0x00000000, &axi_qos->qosconf);
548 writel(0x00002053, &axi_qos->qosctset0);
549 writel(0x00000001, &axi_qos->qosreqctr);
550 writel(0x00002064, &axi_qos->qosthres0);
551 writel(0x00002004, &axi_qos->qosthres1);
552 writel(0x00000000, &axi_qos->qosthres2);
553 writel(0x00000001, &axi_qos->qosqon);
554
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]555 axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB21_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]556 writel(0x00000000, &axi_qos->qosconf);
557 writel(0x00002053, &axi_qos->qosctset0);
558 writel(0x00000001, &axi_qos->qosreqctr);
559 writel(0x00002064, &axi_qos->qosthres0);
560 writel(0x00002004, &axi_qos->qosthres1);
561 writel(0x00000000, &axi_qos->qosthres2);
562 writel(0x00000001, &axi_qos->qosqon);
563
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]564 axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB22_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]565 writel(0x00000000, &axi_qos->qosconf);
566 writel(0x00002053, &axi_qos->qosctset0);
567 writel(0x00000001, &axi_qos->qosreqctr);
568 writel(0x00002064, &axi_qos->qosthres0);
569 writel(0x00002004, &axi_qos->qosthres1);
570 writel(0x00000000, &axi_qos->qosthres2);
571 writel(0x00000001, &axi_qos->qosqon);
572
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]573 axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB30_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]574 writel(0x00000000, &axi_qos->qosconf);
575 writel(0x0000214C, &axi_qos->qosctset0);
576 writel(0x00000001, &axi_qos->qosreqctr);
577 writel(0x00002064, &axi_qos->qosthres0);
578 writel(0x00002004, &axi_qos->qosthres1);
579 writel(0x00000000, &axi_qos->qosthres2);
580 writel(0x00000001, &axi_qos->qosqon);
581
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]582 axi_qos = (struct rcar_axi_qos *)SYS_AXI_AX2M_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]583 writel(0x00000002, &axi_qos->qosconf);
584 writel(0x00002245, &axi_qos->qosctset0);
585 writel(0x00000001, &axi_qos->qosreqctr);
586 writel(0x00002064, &axi_qos->qosthres0);
587 writel(0x00002004, &axi_qos->qosthres1);
588 writel(0x00000000, &axi_qos->qosthres2);
589 writel(0x00000001, &axi_qos->qosqon);
590
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]591 axi_qos = (struct rcar_axi_qos *)SYS_AXI_CC50_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]592 writel(0x00000000, &axi_qos->qosconf);
593 writel(0x00002029, &axi_qos->qosctset0);
594 writel(0x00000001, &axi_qos->qosreqctr);
595 writel(0x00002064, &axi_qos->qosthres0);
596 writel(0x00002004, &axi_qos->qosthres1);
597 writel(0x00000000, &axi_qos->qosthres2);
598 writel(0x00000001, &axi_qos->qosqon);
599
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]600 axi_qos = (struct rcar_axi_qos *)SYS_AXI_CCI_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]601 writel(0x00000002, &axi_qos->qosconf);
602 writel(0x00002245, &axi_qos->qosctset0);
603 writel(0x00000001, &axi_qos->qosreqctr);
604 writel(0x00002064, &axi_qos->qosthres0);
605 writel(0x00002004, &axi_qos->qosthres1);
606 writel(0x00000000, &axi_qos->qosthres2);
607 writel(0x00000001, &axi_qos->qosqon);
608
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]609 axi_qos = (struct rcar_axi_qos *)SYS_AXI_CS_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]610 writel(0x00000000, &axi_qos->qosconf);
611 writel(0x00002053, &axi_qos->qosctset0);
612 writel(0x00000001, &axi_qos->qosreqctr);
613 writel(0x00002064, &axi_qos->qosthres0);
614 writel(0x00002004, &axi_qos->qosthres1);
615 writel(0x00000000, &axi_qos->qosthres2);
616 writel(0x00000001, &axi_qos->qosqon);
617
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]618 axi_qos = (struct rcar_axi_qos *)SYS_AXI_DDM_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]619 writel(0x00000000, &axi_qos->qosconf);
620 writel(0x000020A6, &axi_qos->qosctset0);
621 writel(0x00000001, &axi_qos->qosreqctr);
622 writel(0x00002064, &axi_qos->qosthres0);
623 writel(0x00002004, &axi_qos->qosthres1);
624 writel(0x00000000, &axi_qos->qosthres2);
625 writel(0x00000001, &axi_qos->qosqon);
626
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]627 axi_qos = (struct rcar_axi_qos *)SYS_AXI_ETH_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]628 writel(0x00000000, &axi_qos->qosconf);
629 writel(0x00002053, &axi_qos->qosctset0);
630 writel(0x00000001, &axi_qos->qosreqctr);
631 writel(0x00002064, &axi_qos->qosthres0);
632 writel(0x00002004, &axi_qos->qosthres1);
633 writel(0x00000000, &axi_qos->qosthres2);
634 writel(0x00000001, &axi_qos->qosqon);
635
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]636 axi_qos = (struct rcar_axi_qos *)SYS_AXI_MPXM_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]637 writel(0x00000002, &axi_qos->qosconf);
638 writel(0x00002245, &axi_qos->qosctset0);
639 writel(0x00000001, &axi_qos->qosreqctr);
640 writel(0x00002064, &axi_qos->qosthres0);
641 writel(0x00002004, &axi_qos->qosthres1);
642 writel(0x00000000, &axi_qos->qosthres2);
643 writel(0x00000001, &axi_qos->qosqon);
644
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]645 axi_qos = (struct rcar_axi_qos *)SYS_AXI_SAT0_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]646 writel(0x00000000, &axi_qos->qosconf);
647 writel(0x00002053, &axi_qos->qosctset0);
648 writel(0x00000001, &axi_qos->qosreqctr);
649 writel(0x00002064, &axi_qos->qosthres0);
650 writel(0x00002004, &axi_qos->qosthres1);
651 writel(0x00000000, &axi_qos->qosthres2);
652 writel(0x00000001, &axi_qos->qosqon);
653
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]654 axi_qos = (struct rcar_axi_qos *)SYS_AXI_SAT1_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]655 writel(0x00000000, &axi_qos->qosconf);
656 writel(0x00002053, &axi_qos->qosctset0);
657 writel(0x00000001, &axi_qos->qosreqctr);
658 writel(0x00002064, &axi_qos->qosthres0);
659 writel(0x00002004, &axi_qos->qosthres1);
660 writel(0x00000000, &axi_qos->qosthres2);
661 writel(0x00000001, &axi_qos->qosqon);
662
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]663 axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM0_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]664 writel(0x00000000, &axi_qos->qosconf);
665 writel(0x0000214C, &axi_qos->qosctset0);
666 writel(0x00000001, &axi_qos->qosreqctr);
667 writel(0x00002064, &axi_qos->qosthres0);
668 writel(0x00002004, &axi_qos->qosthres1);
669 writel(0x00000000, &axi_qos->qosthres2);
670 writel(0x00000001, &axi_qos->qosqon);
671
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]672 axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM1_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]673 writel(0x00000000, &axi_qos->qosconf);
674 writel(0x0000214C, &axi_qos->qosctset0);
675 writel(0x00000001, &axi_qos->qosreqctr);
676 writel(0x00002064, &axi_qos->qosthres0);
677 writel(0x00002004, &axi_qos->qosthres1);
678 writel(0x00000000, &axi_qos->qosthres2);
679 writel(0x00000001, &axi_qos->qosqon);
680
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]681 axi_qos = (struct rcar_axi_qos *)SYS_AXI_TRAB_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]682 writel(0x00000000, &axi_qos->qosconf);
683 writel(0x000020A6, &axi_qos->qosctset0);
684 writel(0x00000001, &axi_qos->qosreqctr);
685 writel(0x00002064, &axi_qos->qosthres0);
686 writel(0x00002004, &axi_qos->qosthres1);
687 writel(0x00000000, &axi_qos->qosthres2);
688 writel(0x00000001, &axi_qos->qosqon);
689
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]690 axi_qos = (struct rcar_axi_qos *)SYS_AXI_UDM0_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]691 writel(0x00000000, &axi_qos->qosconf);
692 writel(0x00002053, &axi_qos->qosctset0);
693 writel(0x00000001, &axi_qos->qosreqctr);
694 writel(0x00002064, &axi_qos->qosthres0);
695 writel(0x00002004, &axi_qos->qosthres1);
696 writel(0x00000000, &axi_qos->qosthres2);
697 writel(0x00000001, &axi_qos->qosqon);
698
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]699 axi_qos = (struct rcar_axi_qos *)SYS_AXI_UDM1_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]700 writel(0x00000000, &axi_qos->qosconf);
701 writel(0x00002053, &axi_qos->qosctset0);
702 writel(0x00000001, &axi_qos->qosreqctr);
703 writel(0x00002064, &axi_qos->qosthres0);
704 writel(0x00002004, &axi_qos->qosthres1);
705 writel(0x00000000, &axi_qos->qosthres2);
706 writel(0x00000001, &axi_qos->qosqon);
707
708 /* QoS Register (RT-AXI) */
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]709 axi_qos = (struct rcar_axi_qos *)RT_AXI_SHX_BASE;
Nobuhiro Iwamatsuc0db8962015-03-05 08:30:38 +0900[diff] [blame]710 if (IS_R8A7791_ES2())
711 writel(0x00000001, &axi_qos->qosconf);
712 else
713 writel(0x00000000, &axi_qos->qosconf);
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]714 writel(0x00002053, &axi_qos->qosctset0);
715 writel(0x00002096, &axi_qos->qosctset1);
716 writel(0x00002030, &axi_qos->qosctset2);
717 writel(0x00002030, &axi_qos->qosctset3);
718 writel(0x00000001, &axi_qos->qosreqctr);
719 writel(0x00002064, &axi_qos->qosthres0);
720 writel(0x00002004, &axi_qos->qosthres1);
721 writel(0x00000000, &axi_qos->qosthres2);
722 writel(0x00000001, &axi_qos->qosqon);
723
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]724 axi_qos = (struct rcar_axi_qos *)RT_AXI_DBG_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]725 writel(0x00000000, &axi_qos->qosconf);
726 writel(0x00002053, &axi_qos->qosctset0);
727 writel(0x00002096, &axi_qos->qosctset1);
728 writel(0x00002030, &axi_qos->qosctset2);
729 writel(0x00002030, &axi_qos->qosctset3);
730 writel(0x00000001, &axi_qos->qosreqctr);
731 writel(0x00002064, &axi_qos->qosthres0);
732 writel(0x00002004, &axi_qos->qosthres1);
733 writel(0x00000000, &axi_qos->qosthres2);
734 writel(0x00000001, &axi_qos->qosqon);
735
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]736 axi_qos = (struct rcar_axi_qos *)RT_AXI_RDM_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]737 writel(0x00000000, &axi_qos->qosconf);
738 writel(0x00002299, &axi_qos->qosctset0);
739 writel(0x00000001, &axi_qos->qosreqctr);
740 writel(0x00002064, &axi_qos->qosthres0);
741 writel(0x00002004, &axi_qos->qosthres1);
742 writel(0x00000000, &axi_qos->qosthres2);
743 writel(0x00000001, &axi_qos->qosqon);
744
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]745 axi_qos = (struct rcar_axi_qos *)RT_AXI_RDS_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]746 writel(0x00000000, &axi_qos->qosconf);
747 writel(0x00002029, &axi_qos->qosctset0);
748 writel(0x00000001, &axi_qos->qosreqctr);
749 writel(0x00002064, &axi_qos->qosthres0);
750 writel(0x00002004, &axi_qos->qosthres1);
751 writel(0x00000000, &axi_qos->qosthres2);
752 writel(0x00000001, &axi_qos->qosqon);
753
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]754 axi_qos = (struct rcar_axi_qos *)RT_AXI_RTX64TO128_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]755 writel(0x00000002, &axi_qos->qosconf);
756 writel(0x00002245, &axi_qos->qosctset0);
757 writel(0x00002096, &axi_qos->qosctset1);
758 writel(0x00002030, &axi_qos->qosctset2);
759 writel(0x00002030, &axi_qos->qosctset3);
760 writel(0x00000001, &axi_qos->qosreqctr);
761 writel(0x00002064, &axi_qos->qosthres0);
762 writel(0x00002004, &axi_qos->qosthres1);
763 writel(0x00000000, &axi_qos->qosthres2);
764 writel(0x00000001, &axi_qos->qosqon);
765
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]766 axi_qos = (struct rcar_axi_qos *)RT_AXI_STPRO_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]767 writel(0x00000000, &axi_qos->qosconf);
768 writel(0x00002029, &axi_qos->qosctset0);
769 writel(0x00002096, &axi_qos->qosctset1);
770 writel(0x00002030, &axi_qos->qosctset2);
771 writel(0x00002030, &axi_qos->qosctset3);
772 writel(0x00000001, &axi_qos->qosreqctr);
773 writel(0x00002064, &axi_qos->qosthres0);
774 writel(0x00002004, &axi_qos->qosthres1);
775 writel(0x00000000, &axi_qos->qosthres2);
776 writel(0x00000001, &axi_qos->qosqon);
777
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]778 axi_qos = (struct rcar_axi_qos *)RT_AXI_SY2RT_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]779 writel(0x00000002, &axi_qos->qosconf);
780 writel(0x00002245, &axi_qos->qosctset0);
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]781 writel(0x00000001, &axi_qos->qosreqctr);
782 writel(0x00002064, &axi_qos->qosthres0);
783 writel(0x00002004, &axi_qos->qosthres1);
784 writel(0x00000000, &axi_qos->qosthres2);
785 writel(0x00000001, &axi_qos->qosqon);
786
787 /* QoS Register (MP-AXI) */
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]788 axi_qos = (struct rcar_axi_qos *)MP_AXI_ADSP_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]789 writel(0x00000000, &axi_qos->qosconf);
790 writel(0x00002037, &axi_qos->qosctset0);
791 writel(0x00000001, &axi_qos->qosreqctr);
792 writel(0x00002064, &axi_qos->qosthres0);
793 writel(0x00002004, &axi_qos->qosthres1);
794 writel(0x00000000, &axi_qos->qosthres2);
795 writel(0x00000001, &axi_qos->qosqon);
796
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]797 axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS0_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]798 writel(0x00000001, &axi_qos->qosconf);
799 writel(0x00002014, &axi_qos->qosctset0);
Nobuhiro Iwamatsuc5d5c7b2014-04-02 11:51:07 +0900[diff] [blame]800 writel(0x00000040, &axi_qos->qosreqctr);
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]801 writel(0x00002064, &axi_qos->qosthres0);
802 writel(0x00002004, &axi_qos->qosthres1);
803 writel(0x00000000, &axi_qos->qosthres2);
804 writel(0x00000001, &axi_qos->qosqon);
805
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]806 axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS1_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]807 writel(0x00000001, &axi_qos->qosconf);
808 writel(0x00002014, &axi_qos->qosctset0);
Nobuhiro Iwamatsuc5d5c7b2014-04-02 11:51:07 +0900[diff] [blame]809 writel(0x00000040, &axi_qos->qosreqctr);
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]810 writel(0x00002064, &axi_qos->qosthres0);
811 writel(0x00002004, &axi_qos->qosthres1);
812 writel(0x00000000, &axi_qos->qosthres2);
813 writel(0x00000001, &axi_qos->qosqon);
814
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]815 axi_qos = (struct rcar_axi_qos *)MP_AXI_MLP_BASE;
Nobuhiro Iwamatsuc5d5c7b2014-04-02 11:51:07 +0900[diff] [blame]816 writel(0x00000001, &axi_qos->qosconf);
817 writel(0x00001FF0, &axi_qos->qosctset0);
818 writel(0x00000020, &axi_qos->qosreqctr);
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]819 writel(0x00002064, &axi_qos->qosthres0);
820 writel(0x00002004, &axi_qos->qosthres1);
Nobuhiro Iwamatsuc5d5c7b2014-04-02 11:51:07 +0900[diff] [blame]821 writel(0x00002001, &axi_qos->qosthres2);
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]822 writel(0x00000001, &axi_qos->qosqon);
823
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]824 axi_qos = (struct rcar_axi_qos *)MP_AXI_MMUMP_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]825 writel(0x00000001, &axi_qos->qosconf);
826 writel(0x00002004, &axi_qos->qosctset0);
827 writel(0x00002096, &axi_qos->qosctset1);
828 writel(0x00002030, &axi_qos->qosctset2);
829 writel(0x00002030, &axi_qos->qosctset3);
830 writel(0x00000001, &axi_qos->qosreqctr);
831 writel(0x00002064, &axi_qos->qosthres0);
832 writel(0x00002004, &axi_qos->qosthres1);
833 writel(0x00000000, &axi_qos->qosthres2);
834 writel(0x00000001, &axi_qos->qosqon);
835
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]836 axi_qos = (struct rcar_axi_qos *)MP_AXI_SPU_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]837 writel(0x00000000, &axi_qos->qosconf);
838 writel(0x00002053, &axi_qos->qosctset0);
839 writel(0x00000001, &axi_qos->qosreqctr);
840 writel(0x00002064, &axi_qos->qosthres0);
841 writel(0x00002004, &axi_qos->qosthres1);
842 writel(0x00000000, &axi_qos->qosthres2);
843 writel(0x00000001, &axi_qos->qosqon);
844
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]845 axi_qos = (struct rcar_axi_qos *)MP_AXI_SPUC_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]846 writel(0x00000000, &axi_qos->qosconf);
847 writel(0x0000206E, &axi_qos->qosctset0);
848 writel(0x00000001, &axi_qos->qosreqctr);
849 writel(0x00002064, &axi_qos->qosthres0);
850 writel(0x00002004, &axi_qos->qosthres1);
851 writel(0x00000000, &axi_qos->qosthres2);
852 writel(0x00000001, &axi_qos->qosqon);
853
854 /* QoS Register (SYS-AXI256) */
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]855 axi_qos = (struct rcar_axi_qos *)SYS_AXI256_AXI128TO256_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]856 writel(0x00000002, &axi_qos->qosconf);
Nobuhiro Iwamatsuf70251a2014-04-02 11:50:37 +0900[diff] [blame]857 if (IS_R8A7791_ES2())
858 writel(0x000020EB, &axi_qos->qosctset0);
859 else
860 writel(0x00002245, &axi_qos->qosctset0);
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]861 writel(0x00002096, &axi_qos->qosctset1);
862 writel(0x00002030, &axi_qos->qosctset2);
863 writel(0x00002030, &axi_qos->qosctset3);
864 writel(0x00000001, &axi_qos->qosreqctr);
865 writel(0x00002064, &axi_qos->qosthres0);
866 writel(0x00002004, &axi_qos->qosthres1);
867 writel(0x00000000, &axi_qos->qosthres2);
868 writel(0x00000001, &axi_qos->qosqon);
869
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]870 axi_qos = (struct rcar_axi_qos *)SYS_AXI256_SYX_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]871 writel(0x00000002, &axi_qos->qosconf);
Nobuhiro Iwamatsuf70251a2014-04-02 11:50:37 +0900[diff] [blame]872 if (IS_R8A7791_ES2())
873 writel(0x000020EB, &axi_qos->qosctset0);
874 else
875 writel(0x00002245, &axi_qos->qosctset0);
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]876 writel(0x00002096, &axi_qos->qosctset1);
877 writel(0x00002030, &axi_qos->qosctset2);
878 writel(0x00002030, &axi_qos->qosctset3);
879 writel(0x00000001, &axi_qos->qosreqctr);
880 writel(0x00002064, &axi_qos->qosthres0);
881 writel(0x00002004, &axi_qos->qosthres1);
882 writel(0x00000000, &axi_qos->qosthres2);
883 writel(0x00000001, &axi_qos->qosqon);
884
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]885 axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MPX_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]886 writel(0x00000002, &axi_qos->qosconf);
Nobuhiro Iwamatsuf70251a2014-04-02 11:50:37 +0900[diff] [blame]887 if (IS_R8A7791_ES2())
888 writel(0x000020EB, &axi_qos->qosctset0);
889 else
890 writel(0x00002245, &axi_qos->qosctset0);
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]891 writel(0x00002096, &axi_qos->qosctset1);
892 writel(0x00002030, &axi_qos->qosctset2);
893 writel(0x00002030, &axi_qos->qosctset3);
894 writel(0x00000001, &axi_qos->qosreqctr);
895 writel(0x00002064, &axi_qos->qosthres0);
896 writel(0x00002004, &axi_qos->qosthres1);
897 writel(0x00000000, &axi_qos->qosthres2);
898 writel(0x00000001, &axi_qos->qosqon);
899
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]900 axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MXI_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]901 writel(0x00000002, &axi_qos->qosconf);
902 writel(0x00002245, &axi_qos->qosctset0);
903 writel(0x00002096, &axi_qos->qosctset1);
904 writel(0x00002030, &axi_qos->qosctset2);
905 writel(0x00002030, &axi_qos->qosctset3);
906 writel(0x00000001, &axi_qos->qosreqctr);
907 writel(0x00002064, &axi_qos->qosthres0);
908 writel(0x00002004, &axi_qos->qosthres1);
909 writel(0x00000000, &axi_qos->qosthres2);
910 writel(0x00000001, &axi_qos->qosqon);
911
912 /* QoS Register (CCI-AXI) */
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]913 axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS0_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]914 writel(0x00000001, &axi_qos->qosconf);
915 writel(0x00002004, &axi_qos->qosctset0);
916 writel(0x00002096, &axi_qos->qosctset1);
917 writel(0x00002030, &axi_qos->qosctset2);
918 writel(0x00002030, &axi_qos->qosctset3);
919 writel(0x00000001, &axi_qos->qosreqctr);
920 writel(0x00002064, &axi_qos->qosthres0);
921 writel(0x00002004, &axi_qos->qosthres1);
922 writel(0x00000000, &axi_qos->qosthres2);
923 writel(0x00000001, &axi_qos->qosqon);
924
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]925 axi_qos = (struct rcar_axi_qos *)CCI_AXI_SYX2_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]926 writel(0x00000002, &axi_qos->qosconf);
927 writel(0x00002245, &axi_qos->qosctset0);
928 writel(0x00002096, &axi_qos->qosctset1);
929 writel(0x00002030, &axi_qos->qosctset2);
930 writel(0x00002030, &axi_qos->qosctset3);
931 writel(0x00000001, &axi_qos->qosreqctr);
932 writel(0x00002064, &axi_qos->qosthres0);
933 writel(0x00002004, &axi_qos->qosthres1);
934 writel(0x00000000, &axi_qos->qosthres2);
935 writel(0x00000001, &axi_qos->qosqon);
936
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]937 axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUR_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]938 writel(0x00000001, &axi_qos->qosconf);
939 writel(0x00002004, &axi_qos->qosctset0);
940 writel(0x00002096, &axi_qos->qosctset1);
941 writel(0x00002030, &axi_qos->qosctset2);
942 writel(0x00002030, &axi_qos->qosctset3);
943 writel(0x00000001, &axi_qos->qosreqctr);
944 writel(0x00002064, &axi_qos->qosthres0);
945 writel(0x00002004, &axi_qos->qosthres1);
946 writel(0x00000000, &axi_qos->qosthres2);
947 writel(0x00000001, &axi_qos->qosqon);
948
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]949 axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUDS_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]950 writel(0x00000001, &axi_qos->qosconf);
951 writel(0x00002004, &axi_qos->qosctset0);
952 writel(0x00002096, &axi_qos->qosctset1);
953 writel(0x00002030, &axi_qos->qosctset2);
954 writel(0x00002030, &axi_qos->qosctset3);
955 writel(0x00000001, &axi_qos->qosreqctr);
956 writel(0x00002064, &axi_qos->qosthres0);
957 writel(0x00002004, &axi_qos->qosthres1);
958 writel(0x00000000, &axi_qos->qosthres2);
959 writel(0x00000001, &axi_qos->qosqon);
960
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]961 axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUM_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]962 writel(0x00000001, &axi_qos->qosconf);
963 writel(0x00002004, &axi_qos->qosctset0);
964 writel(0x00002096, &axi_qos->qosctset1);
965 writel(0x00002030, &axi_qos->qosctset2);
966 writel(0x00002030, &axi_qos->qosctset3);
967 writel(0x00000001, &axi_qos->qosreqctr);
968 writel(0x00002064, &axi_qos->qosthres0);
969 writel(0x00002004, &axi_qos->qosthres1);
970 writel(0x00000000, &axi_qos->qosthres2);
971 writel(0x00000001, &axi_qos->qosqon);
972
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]973 axi_qos = (struct rcar_axi_qos *)CCI_AXI_MXI_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]974 writel(0x00000002, &axi_qos->qosconf);
975 writel(0x00002245, &axi_qos->qosctset0);
976 writel(0x00002096, &axi_qos->qosctset1);
977 writel(0x00002030, &axi_qos->qosctset2);
978 writel(0x00002030, &axi_qos->qosctset3);
979 writel(0x00000001, &axi_qos->qosreqctr);
980 writel(0x00002064, &axi_qos->qosthres0);
981 writel(0x00002004, &axi_qos->qosthres1);
982 writel(0x00000000, &axi_qos->qosthres2);
983 writel(0x00000001, &axi_qos->qosqon);
984
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]985 axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS1_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]986 writel(0x00000001, &axi_qos->qosconf);
987 writel(0x00002004, &axi_qos->qosctset0);
988 writel(0x00002096, &axi_qos->qosctset1);
989 writel(0x00002030, &axi_qos->qosctset2);
990 writel(0x00002030, &axi_qos->qosctset3);
991 writel(0x00000001, &axi_qos->qosreqctr);
992 writel(0x00002064, &axi_qos->qosthres0);
993 writel(0x00002004, &axi_qos->qosthres1);
994 writel(0x00000000, &axi_qos->qosthres2);
995 writel(0x00000001, &axi_qos->qosqon);
996
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]997 axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUMP_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]998 writel(0x00000001, &axi_qos->qosconf);
999 writel(0x00002004, &axi_qos->qosctset0);
1000 writel(0x00002096, &axi_qos->qosctset1);
1001 writel(0x00002030, &axi_qos->qosctset2);
1002 writel(0x00002030, &axi_qos->qosctset3);
1003 writel(0x00000001, &axi_qos->qosreqctr);
1004 writel(0x00002064, &axi_qos->qosthres0);
1005 writel(0x00002004, &axi_qos->qosthres1);
1006 writel(0x00000000, &axi_qos->qosthres2);
1007 writel(0x00000001, &axi_qos->qosqon);
1008
1009 /* QoS Register (Media-AXI) */
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]1010 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXR_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]1011 writel(0x00000002, &axi_qos->qosconf);
1012 writel(0x000020DC, &axi_qos->qosctset0);
1013 writel(0x00002096, &axi_qos->qosctset1);
1014 writel(0x00002030, &axi_qos->qosctset2);
1015 writel(0x00002030, &axi_qos->qosctset3);
1016 writel(0x00000020, &axi_qos->qosreqctr);
1017 writel(0x000020AA, &axi_qos->qosthres0);
1018 writel(0x00002032, &axi_qos->qosthres1);
1019 writel(0x00000001, &axi_qos->qosthres2);
1020
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]1021 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXW_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]1022 writel(0x00000002, &axi_qos->qosconf);
1023 writel(0x000020DC, &axi_qos->qosctset0);
1024 writel(0x00002096, &axi_qos->qosctset1);
1025 writel(0x00002030, &axi_qos->qosctset2);
1026 writel(0x00002030, &axi_qos->qosctset3);
1027 writel(0x00000020, &axi_qos->qosreqctr);
1028 writel(0x000020AA, &axi_qos->qosthres0);
1029 writel(0x00002032, &axi_qos->qosthres1);
1030 writel(0x00000001, &axi_qos->qosthres2);
1031
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]1032 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_JPR_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]1033 writel(0x00000001, &axi_qos->qosconf);
1034 writel(0x00002190, &axi_qos->qosctset0);
1035 writel(0x00000020, &axi_qos->qosreqctr);
1036 writel(0x00002064, &axi_qos->qosthres0);
1037 writel(0x00002004, &axi_qos->qosthres1);
1038 writel(0x00000001, &axi_qos->qosthres2);
1039 writel(0x00000001, &axi_qos->qosqon);
1040
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]1041 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_JPW_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]1042 writel(0x00000001, &axi_qos->qosconf);
1043 writel(0x00002190, &axi_qos->qosctset0);
1044 writel(0x00000020, &axi_qos->qosreqctr);
Nobuhiro Iwamatsuf70251a2014-04-02 11:50:37 +0900[diff] [blame]1045 if (IS_R8A7791_ES2()) {
1046 writel(0x00000001, &axi_qos->qosthres0);
1047 writel(0x00000001, &axi_qos->qosthres1);
1048 } else {
1049 writel(0x00002064, &axi_qos->qosthres0);
1050 writel(0x00002004, &axi_qos->qosthres1);
1051 }
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]1052 writel(0x00000001, &axi_qos->qosthres2);
1053 writel(0x00000001, &axi_qos->qosqon);
1054
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]1055 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMR_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]1056 writel(0x00000001, &axi_qos->qosconf);
1057 writel(0x00002190, &axi_qos->qosctset0);
1058 writel(0x00000020, &axi_qos->qosreqctr);
1059 writel(0x00002064, &axi_qos->qosthres0);
1060 writel(0x00002004, &axi_qos->qosthres1);
1061 writel(0x00000001, &axi_qos->qosthres2);
1062 writel(0x00000001, &axi_qos->qosqon);
1063
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]1064 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMW_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]1065 writel(0x00000001, &axi_qos->qosconf);
1066 writel(0x00002190, &axi_qos->qosctset0);
1067 writel(0x00000020, &axi_qos->qosreqctr);
1068 writel(0x00002064, &axi_qos->qosthres0);
1069 writel(0x00002004, &axi_qos->qosthres1);
1070 writel(0x00000001, &axi_qos->qosthres2);
1071 writel(0x00000001, &axi_qos->qosqon);
1072
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]1073 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CR_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]1074 writel(0x00000001, &axi_qos->qosconf);
1075 writel(0x00002190, &axi_qos->qosctset0);
1076 writel(0x00000020, &axi_qos->qosreqctr);
1077 writel(0x00002064, &axi_qos->qosthres0);
1078 writel(0x00002004, &axi_qos->qosthres1);
1079 writel(0x00000001, &axi_qos->qosthres2);
1080 writel(0x00000001, &axi_qos->qosqon);
1081
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]1082 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CW_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]1083 writel(0x00000001, &axi_qos->qosconf);
1084 writel(0x00002190, &axi_qos->qosctset0);
1085 writel(0x00000020, &axi_qos->qosreqctr);
Nobuhiro Iwamatsuf70251a2014-04-02 11:50:37 +0900[diff] [blame]1086 if (IS_R8A7791_ES2()) {
1087 writel(0x00000001, &axi_qos->qosthres0);
1088 writel(0x00000001, &axi_qos->qosthres1);
1089 } else {
1090 writel(0x00002064, &axi_qos->qosthres0);
1091 writel(0x00002004, &axi_qos->qosthres1);
1092 }
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]1093 writel(0x00000001, &axi_qos->qosthres2);
1094 writel(0x00000001, &axi_qos->qosqon);
1095
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]1096 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CR_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]1097 writel(0x00000001, &axi_qos->qosconf);
1098 writel(0x00002190, &axi_qos->qosctset0);
1099 writel(0x00000020, &axi_qos->qosreqctr);
1100 writel(0x00002064, &axi_qos->qosthres0);
1101 writel(0x00002004, &axi_qos->qosthres1);
1102 writel(0x00000001, &axi_qos->qosthres2);
1103 writel(0x00000001, &axi_qos->qosqon);
1104
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]1105 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CW_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]1106 writel(0x00000001, &axi_qos->qosconf);
1107 writel(0x00002190, &axi_qos->qosctset0);
1108 writel(0x00000020, &axi_qos->qosreqctr);
Nobuhiro Iwamatsuf70251a2014-04-02 11:50:37 +0900[diff] [blame]1109 if (IS_R8A7791_ES2()) {
1110 writel(0x00000001, &axi_qos->qosthres0);
1111 writel(0x00000001, &axi_qos->qosthres1);
1112 } else {
1113 writel(0x00002064, &axi_qos->qosthres0);
1114 writel(0x00002004, &axi_qos->qosthres1);
1115 }
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]1116 writel(0x00000001, &axi_qos->qosthres2);
1117 writel(0x00000001, &axi_qos->qosqon);
1118
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]1119 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU1CR_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]1120 writel(0x00000001, &axi_qos->qosconf);
1121 writel(0x00002190, &axi_qos->qosctset0);
1122 writel(0x00000020, &axi_qos->qosreqctr);
1123 writel(0x00002064, &axi_qos->qosthres0);
1124 writel(0x00002004, &axi_qos->qosthres1);
1125 writel(0x00000001, &axi_qos->qosthres2);
1126 writel(0x00000001, &axi_qos->qosqon);
1127
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]1128 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU1CW_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]1129 writel(0x00000001, &axi_qos->qosconf);
1130 writel(0x00002190, &axi_qos->qosctset0);
1131 writel(0x00000020, &axi_qos->qosreqctr);
Nobuhiro Iwamatsuf70251a2014-04-02 11:50:37 +0900[diff] [blame]1132 if (IS_R8A7791_ES2()) {
1133 writel(0x00000001, &axi_qos->qosthres0);
1134 writel(0x00000001, &axi_qos->qosthres1);
1135 } else {
1136 writel(0x00002064, &axi_qos->qosthres0);
1137 writel(0x00002004, &axi_qos->qosthres1);
1138 }
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]1139 writel(0x00000001, &axi_qos->qosthres2);
1140 writel(0x00000001, &axi_qos->qosqon);
1141
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]1142 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VIN0W_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]1143 writel(0x00000001, &axi_qos->qosconf);
Nobuhiro Iwamatsuf70251a2014-04-02 11:50:37 +0900[diff] [blame]1144 if (IS_R8A7791_ES2())
1145 writel(0x00001FF0, &axi_qos->qosctset0);
1146 else
1147 writel(0x000020C8, &axi_qos->qosctset0);
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]1148 writel(0x00000020, &axi_qos->qosreqctr);
1149 writel(0x00002064, &axi_qos->qosthres0);
1150 writel(0x00002004, &axi_qos->qosthres1);
Nobuhiro Iwamatsuf70251a2014-04-02 11:50:37 +0900[diff] [blame]1151 if (IS_R8A7791_ES2())
1152 writel(0x00002001, &axi_qos->qosthres2);
1153 else
1154 writel(0x00000001, &axi_qos->qosthres2);
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]1155 writel(0x00000001, &axi_qos->qosqon);
1156
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]1157 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0R_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]1158 writel(0x00000001, &axi_qos->qosconf);
1159 writel(0x000020C8, &axi_qos->qosctset0);
1160 writel(0x00000020, &axi_qos->qosreqctr);
1161 writel(0x00002064, &axi_qos->qosthres0);
1162 writel(0x00002004, &axi_qos->qosthres1);
1163 writel(0x00000001, &axi_qos->qosthres2);
1164 writel(0x00000001, &axi_qos->qosqon);
1165
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]1166 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0W_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]1167 writel(0x00000001, &axi_qos->qosconf);
1168 writel(0x000020C8, &axi_qos->qosctset0);
1169 writel(0x00000020, &axi_qos->qosreqctr);
Nobuhiro Iwamatsuf70251a2014-04-02 11:50:37 +0900[diff] [blame]1170 if (IS_R8A7791_ES2()) {
1171 writel(0x00000001, &axi_qos->qosthres0);
1172 writel(0x00000001, &axi_qos->qosthres1);
1173 } else {
1174 writel(0x00002064, &axi_qos->qosthres0);
1175 writel(0x00002004, &axi_qos->qosthres1);
1176 }
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]1177 writel(0x00000001, &axi_qos->qosthres2);
1178 writel(0x00000001, &axi_qos->qosqon);
1179
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]1180 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSR_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]1181 writel(0x00000001, &axi_qos->qosconf);
1182 writel(0x000020C8, &axi_qos->qosctset0);
1183 writel(0x00000020, &axi_qos->qosreqctr);
1184 writel(0x00002064, &axi_qos->qosthres0);
1185 writel(0x00002004, &axi_qos->qosthres1);
1186 writel(0x00000001, &axi_qos->qosthres2);
1187 writel(0x00000001, &axi_qos->qosqon);
1188
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]1189 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSW_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]1190 writel(0x00000001, &axi_qos->qosconf);
1191 writel(0x000020C8, &axi_qos->qosctset0);
1192 writel(0x00000020, &axi_qos->qosreqctr);
1193 writel(0x00002064, &axi_qos->qosthres0);
1194 writel(0x00002004, &axi_qos->qosthres1);
1195 writel(0x00000001, &axi_qos->qosthres2);
1196 writel(0x00000001, &axi_qos->qosqon);
1197
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]1198 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1R_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]1199 writel(0x00000001, &axi_qos->qosconf);
1200 writel(0x000020C8, &axi_qos->qosctset0);
1201 writel(0x00000020, &axi_qos->qosreqctr);
1202 writel(0x00002064, &axi_qos->qosthres0);
1203 writel(0x00002004, &axi_qos->qosthres1);
1204 writel(0x00000001, &axi_qos->qosthres2);
1205 writel(0x00000001, &axi_qos->qosqon);
1206
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]1207 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1W_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]1208 writel(0x00000001, &axi_qos->qosconf);
1209 writel(0x000020C8, &axi_qos->qosctset0);
1210 writel(0x00000020, &axi_qos->qosreqctr);
Nobuhiro Iwamatsuf70251a2014-04-02 11:50:37 +0900[diff] [blame]1211 if (IS_R8A7791_ES2()) {
1212 writel(0x00000001, &axi_qos->qosthres0);
1213 writel(0x00000001, &axi_qos->qosthres1);
1214 } else {
1215 writel(0x00002064, &axi_qos->qosthres0);
1216 writel(0x00002004, &axi_qos->qosthres1);
1217 }
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]1218 writel(0x00000001, &axi_qos->qosthres2);
1219 writel(0x00000001, &axi_qos->qosqon);
1220
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]1221 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP1R_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]1222 writel(0x00000001, &axi_qos->qosconf);
1223 writel(0x000020C8, &axi_qos->qosctset0);
1224 writel(0x00000020, &axi_qos->qosreqctr);
1225 writel(0x00002064, &axi_qos->qosthres0);
1226 writel(0x00002004, &axi_qos->qosthres1);
1227 writel(0x00000001, &axi_qos->qosthres2);
1228 writel(0x00000001, &axi_qos->qosqon);
1229
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]1230 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP1W_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]1231 writel(0x00000001, &axi_qos->qosconf);
1232 writel(0x000020C8, &axi_qos->qosctset0);
1233 writel(0x00000020, &axi_qos->qosreqctr);
Nobuhiro Iwamatsuf70251a2014-04-02 11:50:37 +0900[diff] [blame]1234 if (IS_R8A7791_ES2()) {
1235 writel(0x00000001, &axi_qos->qosthres0);
1236 writel(0x00000001, &axi_qos->qosthres1);
1237 } else {
1238 writel(0x00002064, &axi_qos->qosthres0);
1239 writel(0x00002004, &axi_qos->qosthres1);
1240 }
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]1241 writel(0x00000001, &axi_qos->qosthres2);
1242 writel(0x00000001, &axi_qos->qosqon);
1243
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]1244 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRR_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]1245 writel(0x00000001, &axi_qos->qosconf);
1246 writel(0x000020C8, &axi_qos->qosctset0);
1247 writel(0x00000020, &axi_qos->qosreqctr);
1248 writel(0x00002064, &axi_qos->qosthres0);
1249 writel(0x00002004, &axi_qos->qosthres1);
1250 writel(0x00000001, &axi_qos->qosthres2);
1251 writel(0x00000001, &axi_qos->qosqon);
1252
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]1253 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRW_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]1254 writel(0x00000001, &axi_qos->qosconf);
1255 writel(0x000020C8, &axi_qos->qosctset0);
1256 writel(0x00000020, &axi_qos->qosreqctr);
1257 writel(0x00002064, &axi_qos->qosthres0);
1258 writel(0x00002004, &axi_qos->qosthres1);
1259 writel(0x00000001, &axi_qos->qosthres2);
1260 writel(0x00000001, &axi_qos->qosqon);
1261
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]1262 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0R_BASE;
Nobuhiro Iwamatsuf70251a2014-04-02 11:50:37 +0900[diff] [blame]1263 if (IS_R8A7791_ES2())
1264 writel(0x00000003, &axi_qos->qosconf);
1265 else
1266 writel(0x00000000, &axi_qos->qosconf);
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]1267 writel(0x000020C8, &axi_qos->qosctset0);
1268 writel(0x00002064, &axi_qos->qosthres0);
1269 writel(0x00002004, &axi_qos->qosthres1);
1270 writel(0x00000001, &axi_qos->qosthres2);
1271 writel(0x00000001, &axi_qos->qosqon);
1272
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]1273 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0W_BASE;
Nobuhiro Iwamatsuf70251a2014-04-02 11:50:37 +0900[diff] [blame]1274 if (IS_R8A7791_ES2())
1275 writel(0x00000003, &axi_qos->qosconf);
1276 else
1277 writel(0x00000000, &axi_qos->qosconf);
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]1278 writel(0x000020C8, &axi_qos->qosctset0);
1279 writel(0x00002064, &axi_qos->qosthres0);
1280 writel(0x00002004, &axi_qos->qosthres1);
1281 writel(0x00000001, &axi_qos->qosthres2);
1282 writel(0x00000001, &axi_qos->qosqon);
1283
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]1284 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD1R_BASE;
Nobuhiro Iwamatsuf70251a2014-04-02 11:50:37 +0900[diff] [blame]1285 if (IS_R8A7791_ES2())
1286 writel(0x00000003, &axi_qos->qosconf);
1287 else
1288 writel(0x00000000, &axi_qos->qosconf);
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]1289 writel(0x000020C8, &axi_qos->qosctset0);
1290 writel(0x00002064, &axi_qos->qosthres0);
1291 writel(0x00002004, &axi_qos->qosthres1);
1292 writel(0x00000001, &axi_qos->qosthres2);
1293 writel(0x00000001, &axi_qos->qosqon);
1294
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]1295 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD1W_BASE;
Nobuhiro Iwamatsuf70251a2014-04-02 11:50:37 +0900[diff] [blame]1296 if (IS_R8A7791_ES2())
1297 writel(0x00000003, &axi_qos->qosconf);
1298 else
1299 writel(0x00000000, &axi_qos->qosconf);
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]1300 writel(0x000020C8, &axi_qos->qosctset0);
1301 writel(0x00002064, &axi_qos->qosthres0);
1302 writel(0x00002004, &axi_qos->qosthres1);
1303 writel(0x00000001, &axi_qos->qosthres2);
1304 writel(0x00000001, &axi_qos->qosqon);
1305
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]1306 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0R_BASE;
Nobuhiro Iwamatsuf70251a2014-04-02 11:50:37 +0900[diff] [blame]1307 if (IS_R8A7791_ES2())
1308 writel(0x00000003, &axi_qos->qosconf);
1309 else
1310 writel(0x00000000, &axi_qos->qosconf);
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]1311 writel(0x00002063, &axi_qos->qosctset0);
1312 writel(0x00000001, &axi_qos->qosreqctr);
1313 writel(0x00002064, &axi_qos->qosthres0);
1314 writel(0x00002004, &axi_qos->qosthres1);
1315 writel(0x00000001, &axi_qos->qosthres2);
1316 writel(0x00000001, &axi_qos->qosqon);
1317
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]1318 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0W_BASE;
Nobuhiro Iwamatsuf70251a2014-04-02 11:50:37 +0900[diff] [blame]1319 if (IS_R8A7791_ES2())
1320 writel(0x00000000, &axi_qos->qosconf);
1321 else
1322 writel(0x00000000, &axi_qos->qosconf);
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]1323 writel(0x00002063, &axi_qos->qosctset0);
1324 writel(0x00000001, &axi_qos->qosreqctr);
1325 writel(0x00002064, &axi_qos->qosthres0);
1326 writel(0x00002004, &axi_qos->qosthres1);
1327 writel(0x00000001, &axi_qos->qosthres2);
1328 writel(0x00000001, &axi_qos->qosqon);
1329
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]1330 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CR_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]1331 writel(0x00000001, &axi_qos->qosconf);
1332 writel(0x00002073, &axi_qos->qosctset0);
1333 writel(0x00000020, &axi_qos->qosreqctr);
1334 writel(0x00002064, &axi_qos->qosthres0);
1335 writel(0x00002004, &axi_qos->qosthres1);
1336 writel(0x00000001, &axi_qos->qosthres2);
1337 writel(0x00000001, &axi_qos->qosqon);
1338
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]1339 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CW_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]1340 writel(0x00000001, &axi_qos->qosconf);
1341 writel(0x00002073, &axi_qos->qosctset0);
1342 writel(0x00000020, &axi_qos->qosreqctr);
Nobuhiro Iwamatsuf70251a2014-04-02 11:50:37 +0900[diff] [blame]1343 if (IS_R8A7791_ES2()) {
1344 writel(0x00000001, &axi_qos->qosthres0);
1345 writel(0x00000001, &axi_qos->qosthres1);
1346 } else {
1347 writel(0x00002064, &axi_qos->qosthres0);
1348 writel(0x00002004, &axi_qos->qosthres1);
1349 }
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]1350 writel(0x00000001, &axi_qos->qosthres2);
1351 writel(0x00000001, &axi_qos->qosqon);
1352
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]1353 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VR_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]1354 writel(0x00000001, &axi_qos->qosconf);
1355 writel(0x00002073, &axi_qos->qosctset0);
1356 writel(0x00000020, &axi_qos->qosreqctr);
1357 writel(0x00002064, &axi_qos->qosthres0);
1358 writel(0x00002004, &axi_qos->qosthres1);
1359 writel(0x00000001, &axi_qos->qosthres2);
1360 writel(0x00000001, &axi_qos->qosqon);
1361
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]1362 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VW_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]1363 writel(0x00000001, &axi_qos->qosconf);
1364 writel(0x00002073, &axi_qos->qosctset0);
1365 writel(0x00000020, &axi_qos->qosreqctr);
Nobuhiro Iwamatsuf70251a2014-04-02 11:50:37 +0900[diff] [blame]1366 if (IS_R8A7791_ES2()) {
1367 writel(0x00000001, &axi_qos->qosthres0);
1368 writel(0x00000001, &axi_qos->qosthres1);
1369 } else {
1370 writel(0x00002064, &axi_qos->qosthres0);
1371 writel(0x00002004, &axi_qos->qosthres1);
1372 }
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]1373 writel(0x00000001, &axi_qos->qosthres2);
1374 writel(0x00000001, &axi_qos->qosqon);
1375
Nobuhiro Iwamatsu0a6c5102014-03-27 16:18:08 +0900[diff] [blame]1376 axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VPC0R_BASE;
Nobuhiro Iwamatsu7fbb92b2013-11-21 17:07:46 +0900[diff] [blame]1377 writel(0x00000001, &axi_qos->qosconf);
1378 writel(0x00002073, &axi_qos->qosctset0);
1379 writel(0x00000020, &axi_qos->qosreqctr);
1380 writel(0x00002064, &axi_qos->qosthres0);
1381 writel(0x00002004, &axi_qos->qosthres1);
1382 writel(0x00000001, &axi_qos->qosthres2);
1383 writel(0x00000001, &axi_qos->qosqon);
1384}
Marek Vasutd26aa8c2024-02-27 17:05:53 +0100[diff] [blame]1385#else /* CONFIG_RENESAS_EXTRAM_BOOT */
Nobuhiro Iwamatsu25c0dca2014-10-31 16:16:27 +0900[diff] [blame]1386void qos_init(void)
1387{
1388}
Marek Vasutd26aa8c2024-02-27 17:05:53 +0100[diff] [blame]1389#endif /* CONFIG_RENESAS_EXTRAM_BOOT */