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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Shengzhou Liu49912402014-11-24 17:11:56 +08002/*
3 * Copyright 2014 Freescale Semiconductor, Inc.
4 *
Shengzhou Liu00d7e5b2015-03-27 15:48:34 +08005 * Shengzhou Liu <Shengzhou.Liu@freescale.com>
Shengzhou Liu49912402014-11-24 17:11:56 +08006 */
7
Tom Rinidec7ea02024-05-20 13:35:03 -06008#include <config.h>
Shengzhou Liu49912402014-11-24 17:11:56 +08009#include <command.h>
Simon Glass2dc9c342020-05-10 11:40:01 -060010#include <fdt_support.h>
Simon Glass274e0b02020-05-10 11:39:56 -060011#include <net.h>
Shengzhou Liu49912402014-11-24 17:11:56 +080012#include <netdev.h>
13#include <asm/mmu.h>
14#include <asm/processor.h>
15#include <asm/immap_85xx.h>
16#include <asm/fsl_law.h>
17#include <asm/fsl_serdes.h>
18#include <asm/fsl_portals.h>
19#include <asm/fsl_liodn.h>
20#include <malloc.h>
21#include <fm_eth.h>
22#include <fsl_mdio.h>
23#include <miiphy.h>
24#include <phy.h>
Shaohui Xie513eaf22015-10-26 19:47:47 +080025#include <fsl_dtsec.h>
Shengzhou Liu49912402014-11-24 17:11:56 +080026#include <asm/fsl_serdes.h>
Shengzhou Liuccc57ef2014-12-17 16:51:08 +080027#include "../common/fman.h"
Shengzhou Liu49912402014-11-24 17:11:56 +080028
Masahiro Yamadaf7ed78b2020-06-26 15:13:33 +090029int board_eth_init(struct bd_info *bis)
Shengzhou Liu49912402014-11-24 17:11:56 +080030{
31#if defined(CONFIG_FMAN_ENET)
32 int i, interface;
33 struct memac_mdio_info dtsec_mdio_info;
34 struct memac_mdio_info tgec_mdio_info;
35 struct mii_dev *dev;
Tom Rinid5c3bf22022-10-28 20:27:12 -040036 ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
Shengzhou Liu49912402014-11-24 17:11:56 +080037 u32 srds_s1;
38
39 srds_s1 = in_be32(&gur->rcwsr[4]) &
40 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
41 srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
42
43 dtsec_mdio_info.regs =
Tom Rini364d0022023-01-10 11:19:45 -050044 (struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR;
Shengzhou Liu49912402014-11-24 17:11:56 +080045
46 dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
47
48 /* Register the 1G MDIO bus */
49 fm_memac_mdio_init(bis, &dtsec_mdio_info);
50
51 tgec_mdio_info.regs =
Tom Rini364d0022023-01-10 11:19:45 -050052 (struct memac_mdio_controller *)CFG_SYS_FM1_TGEC_MDIO_ADDR;
Shengzhou Liu49912402014-11-24 17:11:56 +080053 tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
54
55 /* Register the 10G MDIO bus */
56 fm_memac_mdio_init(bis, &tgec_mdio_info);
57
Shengzhou Liuccc57ef2014-12-17 16:51:08 +080058 /* Set the on-board RGMII PHY address */
Shengzhou Liu49912402014-11-24 17:11:56 +080059 fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY1_ADDR);
60
61 switch (srds_s1) {
York Sunf9a03632016-12-28 08:43:34 -080062#ifdef CONFIG_TARGET_T1024RDB
Shengzhou Liu49912402014-11-24 17:11:56 +080063 case 0x95:
Shengzhou Liuccc57ef2014-12-17 16:51:08 +080064 /* set the on-board RGMII2 PHY */
65 fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR);
66
Vladimir Oltean6a6e4022021-09-18 15:32:34 +030067 /* set 10GBase-R with Aquantia AQR105 PHY */
Shengzhou Liu49912402014-11-24 17:11:56 +080068 fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
69 break;
Shengzhou Liu00d7e5b2015-03-27 15:48:34 +080070#endif
71 case 0x6a:
72 case 0x6b:
Shengzhou Liuccc57ef2014-12-17 16:51:08 +080073 case 0x77:
74 case 0x135:
75 /* set the on-board 2.5G SGMII AQR105 PHY */
Shengzhou Liu00d7e5b2015-03-27 15:48:34 +080076 fm_info_set_phy_address(FM1_DTSEC3, SGMII_AQR_PHY_ADDR);
York Sun940ee4a2016-12-28 08:43:33 -080077#ifdef CONFIG_TARGET_T1023RDB
Shengzhou Liu00d7e5b2015-03-27 15:48:34 +080078 /* set the on-board 1G SGMII RTL8211F PHY */
79 fm_info_set_phy_address(FM1_DTSEC1, SGMII_RTK_PHY_ADDR);
80#endif
Shengzhou Liuccc57ef2014-12-17 16:51:08 +080081 break;
Shengzhou Liu49912402014-11-24 17:11:56 +080082 default:
83 printf("SerDes protocol 0x%x is not supported on T102xRDB\n",
84 srds_s1);
85 break;
86 }
87
Tom Rini0a2bac72022-11-16 13:10:29 -050088 for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) {
Shengzhou Liu49912402014-11-24 17:11:56 +080089 interface = fm_info_get_enet_if(i);
90 switch (interface) {
91 case PHY_INTERFACE_MODE_RGMII:
Madalin Bucur03b80152020-11-04 15:09:17 +020092 case PHY_INTERFACE_MODE_RGMII_TXID:
93 case PHY_INTERFACE_MODE_RGMII_RXID:
94 case PHY_INTERFACE_MODE_RGMII_ID:
Shengzhou Liu49912402014-11-24 17:11:56 +080095 dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
96 fm_info_set_mdio(i, dev);
97 break;
Shengzhou Liu00d7e5b2015-03-27 15:48:34 +080098 case PHY_INTERFACE_MODE_SGMII:
York Sun940ee4a2016-12-28 08:43:33 -080099#if defined(CONFIG_TARGET_T1023RDB)
Shengzhou Liu00d7e5b2015-03-27 15:48:34 +0800100 dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
York Sunf9a03632016-12-28 08:43:34 -0800101#elif defined(CONFIG_TARGET_T1024RDB)
Shengzhou Liu00d7e5b2015-03-27 15:48:34 +0800102 dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
103#endif
104 fm_info_set_mdio(i, dev);
105 break;
Vladimir Oltean6caef972021-09-18 15:32:35 +0300106 case PHY_INTERFACE_MODE_2500BASEX:
Shengzhou Liuccc57ef2014-12-17 16:51:08 +0800107 dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
108 fm_info_set_mdio(i, dev);
109 break;
Shengzhou Liu49912402014-11-24 17:11:56 +0800110 default:
111 break;
112 }
113 }
114
Tom Rini0a2bac72022-11-16 13:10:29 -0500115 for (i = FM1_10GEC1; i < FM1_10GEC1 + CFG_SYS_NUM_FM1_10GEC; i++) {
Shengzhou Liu49912402014-11-24 17:11:56 +0800116 switch (fm_info_get_enet_if(i)) {
117 case PHY_INTERFACE_MODE_XGMII:
118 dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
119 fm_info_set_mdio(i, dev);
120 break;
121 default:
122 break;
123 }
124 }
125
126 cpu_eth_init(bis);
127#endif /* CONFIG_FMAN_ENET */
128
129 return pci_eth_init(bis);
130}
131
Shengzhou Liuccc57ef2014-12-17 16:51:08 +0800132void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
133 enum fm_port port, int offset)
134{
York Sunf9a03632016-12-28 08:43:34 -0800135#if defined(CONFIG_TARGET_T1024RDB)
Vladimir Oltean6caef972021-09-18 15:32:35 +0300136 if (((fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_2500BASEX) ||
Shengzhou Liu00d7e5b2015-03-27 15:48:34 +0800137 (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII)) &&
138 (port == FM1_DTSEC3)) {
Shengzhou Liuccc57ef2014-12-17 16:51:08 +0800139 fdt_set_phy_handle(fdt, compat, addr, "sg_2500_aqr105_phy4");
Shengzhou Liu032df622015-04-14 17:56:50 +0800140 fdt_setprop_string(fdt, offset, "phy-connection-type",
Vladimir Oltean6caef972021-09-18 15:32:35 +0300141 "2500base-x");
Shengzhou Liuccc57ef2014-12-17 16:51:08 +0800142 fdt_status_disabled_by_alias(fdt, "xg_aqr105_phy3");
143 }
Shengzhou Liu00d7e5b2015-03-27 15:48:34 +0800144#endif
Shengzhou Liuccc57ef2014-12-17 16:51:08 +0800145}
146
Shengzhou Liu49912402014-11-24 17:11:56 +0800147void fdt_fixup_board_enet(void *fdt)
148{
149}