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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Mingkai Hud2396512016-09-07 18:47:28 +08002/*
3 * Copyright 2016 Freescale Semiconductor, Inc.
Gaurav Jain476c6392022-03-24 11:50:35 +05304 * Copyright 2021 NXP
Mingkai Hud2396512016-09-07 18:47:28 +08005 */
6
Tom Rinidec7ea02024-05-20 13:35:03 -06007#include <config.h>
Mingkai Hud2396512016-09-07 18:47:28 +08008#include <i2c.h>
9#include <fdt_support.h>
Simon Glass97589732020-05-10 11:40:02 -060010#include <init.h>
Sean Anderson99e12862022-03-22 17:16:05 -040011#include <semihosting.h>
12#include <serial.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060013#include <asm/global_data.h>
Mingkai Hud2396512016-09-07 18:47:28 +080014#include <asm/io.h>
15#include <asm/arch/clock.h>
16#include <asm/arch/fsl_serdes.h>
Mingkai Hud2396512016-09-07 18:47:28 +080017#include <asm/arch/soc.h>
Laurentiu Tudor512d13e2018-08-09 15:19:46 +030018#include <asm/arch-fsl-layerscape/fsl_icid.h>
Mingkai Hud2396512016-09-07 18:47:28 +080019#include <hwconfig.h>
20#include <ahci.h>
21#include <mmc.h>
22#include <scsi.h>
23#include <fm_eth.h>
24#include <fsl_csu.h>
25#include <fsl_esdhc.h>
Hou Zhiqiang67b6d0a2016-12-09 16:09:01 +080026#include <power/mc34vr500_pmic.h>
Mingkai Hud2396512016-09-07 18:47:28 +080027#include "cpld.h"
28
29DECLARE_GLOBAL_DATA_PTR;
30
Sean Anderson99e12862022-03-22 17:16:05 -040031struct serial_device *default_serial_console(void)
32{
33#if IS_ENABLED(CONFIG_SEMIHOSTING_SERIAL)
Sean Anderson409024e2022-03-22 16:59:33 -040034 if (semihosting_enabled())
35 return &serial_smh_device;
Sean Anderson99e12862022-03-22 17:16:05 -040036#endif
37 return &eserial1_device;
38}
39
Sumit Gargc064fc72017-03-30 09:53:13 +053040int board_early_init_f(void)
41{
42 fsl_lsch2_early_init_f();
43
44 return 0;
45}
46
47#ifndef CONFIG_SPL_BUILD
Mingkai Hud2396512016-09-07 18:47:28 +080048int checkboard(void)
49{
50 static const char *freq[2] = {"100.00MHZ", "156.25MHZ"};
51 u8 cfg_rcw_src1, cfg_rcw_src2;
52 u16 cfg_rcw_src;
53 u8 sd1refclk_sel;
54
55 puts("Board: LS1046ARDB, boot from ");
56
57 cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1);
58 cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2);
59 cpld_rev_bit(&cfg_rcw_src1);
60 cfg_rcw_src = cfg_rcw_src1;
61 cfg_rcw_src = (cfg_rcw_src << 1) | cfg_rcw_src2;
62
63 if (cfg_rcw_src == 0x44)
64 printf("QSPI vBank %d\n", CPLD_READ(vbank));
65 else if (cfg_rcw_src == 0x40)
66 puts("SD\n");
67 else
68 puts("Invalid setting of SW5\n");
69
70 printf("CPLD: V%x.%x\nPCBA: V%x.0\n", CPLD_READ(cpld_ver),
71 CPLD_READ(cpld_ver_sub), CPLD_READ(pcba_ver));
72
73 puts("SERDES Reference Clocks:\n");
74 sd1refclk_sel = CPLD_READ(sd1refclk_sel);
75 printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq[sd1refclk_sel], freq[0]);
76
77 return 0;
78}
79
Mingkai Hud2396512016-09-07 18:47:28 +080080int board_init(void)
81{
Tom Rini376b88a2022-10-28 20:27:13 -040082 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
Mingkai Hud2396512016-09-07 18:47:28 +080083
Udit Agarwal22ec2382019-11-07 16:11:32 +000084#ifdef CONFIG_NXP_ESBC
Vinitha Pillai-B57223a47072e2017-03-23 13:48:18 +053085 /*
86 * In case of Secure Boot, the IBR configures the SMMU
87 * to allow only Secure transactions.
88 * SMMU must be reset in bypass mode.
89 * Set the ClientPD bit and Clear the USFCFG Bit
90 */
91 u32 val;
92 val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
93 out_le32(SMMU_SCR0, val);
94 val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
95 out_le32(SMMU_NSCR0, val);
96#endif
97
Martin Schillerfb425ee2021-11-17 12:59:20 +010098#if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH)
99 pci_init();
100#endif
101
Mingkai Hud2396512016-09-07 18:47:28 +0800102 /* invert AQR105 IRQ pins polarity */
103 out_be32(&scfg->intpcr, AQR105_IRQ_MASK);
104
105 return 0;
106}
107
Hou Zhiqiang67b6d0a2016-12-09 16:09:01 +0800108int board_setup_core_volt(u32 vdd)
109{
110 bool en_0v9;
111
112 en_0v9 = (vdd == 900) ? true : false;
113 cpld_select_core_volt(en_0v9);
114
115 return 0;
116}
117
118int get_serdes_volt(void)
119{
120 return mc34vr500_get_sw_volt(SW4);
121}
122
123int set_serdes_volt(int svdd)
124{
125 return mc34vr500_set_sw_volt(SW4, svdd);
126}
127
128int power_init_board(void)
129{
130 int ret;
131
132 ret = power_mc34vr500_init(0);
133 if (ret)
134 return ret;
135
136 setup_chip_volt();
137
138 return 0;
139}
140
Mingkai Hud2396512016-09-07 18:47:28 +0800141void config_board_mux(void)
142{
143#ifdef CONFIG_HAS_FSL_XHCI_USB
Tom Rini376b88a2022-10-28 20:27:13 -0400144 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
Mingkai Hud2396512016-09-07 18:47:28 +0800145 u32 usb_pwrfault;
146
147 /* USB3 is not used, configure mux to IIC4_SCL/IIC4_SDA */
148 out_be32(&scfg->rcwpmuxcr0, 0x3300);
149 out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
150 usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED <<
151 SCFG_USBPWRFAULT_USB3_SHIFT) |
152 (SCFG_USBPWRFAULT_DEDICATED <<
153 SCFG_USBPWRFAULT_USB2_SHIFT) |
154 (SCFG_USBPWRFAULT_SHARED <<
155 SCFG_USBPWRFAULT_USB1_SHIFT);
156 out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
157#endif
158}
159
160#ifdef CONFIG_MISC_INIT_R
161int misc_init_r(void)
162{
163 config_board_mux();
164 return 0;
165}
166#endif
167
Masahiro Yamadaf7ed78b2020-06-26 15:13:33 +0900168int ft_board_setup(void *blob, struct bd_info *bd)
Mingkai Hud2396512016-09-07 18:47:28 +0800169{
170 u64 base[CONFIG_NR_DRAM_BANKS];
171 u64 size[CONFIG_NR_DRAM_BANKS];
172
173 /* fixup DT for the two DDR banks */
174 base[0] = gd->bd->bi_dram[0].start;
175 size[0] = gd->bd->bi_dram[0].size;
176 base[1] = gd->bd->bi_dram[1].start;
177 size[1] = gd->bd->bi_dram[1].size;
178
179 fdt_fixup_memory_banks(blob, base, size, 2);
180 ft_cpu_setup(blob, bd);
181
182#ifdef CONFIG_SYS_DPAA_FMAN
Madalin Bucurb76b0a62020-04-23 16:25:19 +0300183#ifndef CONFIG_DM_ETH
Mingkai Hud2396512016-09-07 18:47:28 +0800184 fdt_fixup_fman_ethernet(blob);
185#endif
Madalin Bucurb76b0a62020-04-23 16:25:19 +0300186#endif
Mingkai Hud2396512016-09-07 18:47:28 +0800187
Laurentiu Tudor512d13e2018-08-09 15:19:46 +0300188 fdt_fixup_icid(blob);
189
Mingkai Hud2396512016-09-07 18:47:28 +0800190 return 0;
191}
Sumit Gargc064fc72017-03-30 09:53:13 +0530192#endif