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git01.mediatek.com / filogic / uboot / 324cb4d73d2883138305686b6f013e9e84de580d / . / arch / arm / mach-versal / mp.c
blob: 921ca49c3596e83371a636d7be3f7797f109b621 [file] [log] [blame]
Siva Durga Prasad Paladugu775aa952019-01-08 21:47:26 +0530[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * (C) Copyright 2019 Xilinx, Inc.
Michal Simek7359cc22023-09-22 12:35:35 +0200[diff] [blame]4 * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>
Siva Durga Prasad Paladugu775aa952019-01-08 21:47:26 +0530[diff] [blame]5 */
6
Tom Rinidec7ea02024-05-20 13:35:03 -0600[diff] [blame]7#include <config.h>
8#include <linux/string.h>
Siva Durga Prasad Paladugu775aa952019-01-08 21:47:26 +0530[diff] [blame]9#include <asm/io.h>
10#include <asm/arch/hardware.h>
11#include <asm/arch/sys_proto.h>
12
Siva Durga Prasad Paladugu775aa952019-01-08 21:47:26 +0530[diff] [blame]13#define HALT 0
14#define RELEASE 1
15
16#define VERSAL_RPU_CFG_CPU_HALT_MASK 0x01
17#define VERSAL_RPU_GLBL_CTRL_SPLIT_LOCK_MASK 0x08
18#define VERSAL_RPU_GLBL_CTRL_TCM_COMB_MASK 0x40
19#define VERSAL_RPU_GLBL_CTRL_SLCLAMP_MASK 0x10
20
21#define VERSAL_CRLAPB_RST_LPD_AMBA_RST_MASK 0x04
22#define VERSAL_CRLAPB_RST_LPD_R50_RST_MASK 0x01
23#define VERSAL_CRLAPB_RST_LPD_R51_RST_MASK 0x02
24#define VERSAL_CRL_RST_CPU_R5_RESET_PGE_MASK 0x10
25#define VERSAL_CRLAPB_CPU_R5_CTRL_CLKACT_MASK 0x1000000
26
Algapally Santosh Sagarb0142c12023-06-09 03:05:31 -0600[diff] [blame]27static void set_r5_halt_mode(u8 halt, u8 mode)
Siva Durga Prasad Paladugu775aa952019-01-08 21:47:26 +0530[diff] [blame]28{
29 u32 tmp;
30
31 tmp = readl(&rpu_base->rpu0_cfg);
32 if (halt == HALT)
33 tmp &= ~VERSAL_RPU_CFG_CPU_HALT_MASK;
34 else
35 tmp |= VERSAL_RPU_CFG_CPU_HALT_MASK;
36 writel(tmp, &rpu_base->rpu0_cfg);
37
38 if (mode == TCM_LOCK) {
39 tmp = readl(&rpu_base->rpu1_cfg);
40 if (halt == HALT)
41 tmp &= ~VERSAL_RPU_CFG_CPU_HALT_MASK;
42 else
43 tmp |= VERSAL_RPU_CFG_CPU_HALT_MASK;
44 writel(tmp, &rpu_base->rpu1_cfg);
45 }
46}
47
Algapally Santosh Sagarb0142c12023-06-09 03:05:31 -0600[diff] [blame]48static void set_r5_tcm_mode(u8 mode)
Siva Durga Prasad Paladugu775aa952019-01-08 21:47:26 +0530[diff] [blame]49{
50 u32 tmp;
51
52 tmp = readl(&rpu_base->rpu_glbl_ctrl);
53 if (mode == TCM_LOCK) {
54 tmp &= ~VERSAL_RPU_GLBL_CTRL_SPLIT_LOCK_MASK;
55 tmp |= VERSAL_RPU_GLBL_CTRL_TCM_COMB_MASK |
56 VERSAL_RPU_GLBL_CTRL_SLCLAMP_MASK;
57 } else {
58 tmp |= VERSAL_RPU_GLBL_CTRL_SPLIT_LOCK_MASK;
59 tmp &= ~(VERSAL_RPU_GLBL_CTRL_TCM_COMB_MASK |
60 VERSAL_RPU_GLBL_CTRL_SLCLAMP_MASK);
61 }
62
63 writel(tmp, &rpu_base->rpu_glbl_ctrl);
64}
65
Algapally Santosh Sagarb0142c12023-06-09 03:05:31 -0600[diff] [blame]66static void release_r5_reset(u8 mode)
Siva Durga Prasad Paladugu775aa952019-01-08 21:47:26 +0530[diff] [blame]67{
68 u32 tmp;
69
70 tmp = readl(&crlapb_base->rst_cpu_r5);
71 tmp &= ~(VERSAL_CRLAPB_RST_LPD_AMBA_RST_MASK |
72 VERSAL_CRLAPB_RST_LPD_R50_RST_MASK |
73 VERSAL_CRL_RST_CPU_R5_RESET_PGE_MASK);
74
75 if (mode == TCM_LOCK)
76 tmp &= ~VERSAL_CRLAPB_RST_LPD_R51_RST_MASK;
77
78 writel(tmp, &crlapb_base->rst_cpu_r5);
79}
80
Algapally Santosh Sagarb0142c12023-06-09 03:05:31 -0600[diff] [blame]81static void enable_clock_r5(void)
Siva Durga Prasad Paladugu775aa952019-01-08 21:47:26 +0530[diff] [blame]82{
83 u32 tmp;
84
85 tmp = readl(&crlapb_base->cpu_r5_ctrl);
86 tmp |= VERSAL_CRLAPB_CPU_R5_CTRL_CLKACT_MASK;
87 writel(tmp, &crlapb_base->cpu_r5_ctrl);
88}
89
90void initialize_tcm(bool mode)
91{
92 if (!mode) {
93 set_r5_tcm_mode(TCM_LOCK);
94 set_r5_halt_mode(HALT, TCM_LOCK);
95 enable_clock_r5();
96 release_r5_reset(TCM_LOCK);
97 } else {
98 set_r5_tcm_mode(TCM_SPLIT);
99 set_r5_halt_mode(HALT, TCM_SPLIT);
100 enable_clock_r5();
101 release_r5_reset(TCM_SPLIT);
102 }
103}
104
105void tcm_init(u8 mode)
106{
107 puts("WARNING: Initializing TCM overwrites TCM content\n");
108 initialize_tcm(mode);
109 memset((void *)VERSAL_TCM_BASE_ADDR, 0, VERSAL_TCM_SIZE);
110}