| Tom Rini | dec7ea0 | 2024-05-20 13:35:03 -0600 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
| 2 | /* |
| 3 | * (C) Copyright 2024 - Analog Devices, Inc. |
| 4 | * |
| 5 | * Written and/or maintained by Timesys Corporation |
| 6 | * |
| 7 | * Contact: Nathan Barrett-Morrison <nathan.morrison@timesys.com> |
| 8 | * Contact: Greg Malysa <greg.malysa@timesys.com> |
| 9 | */ |
| 10 | |
| 11 | #include <asm/io.h> |
| 12 | #include <asm/arch-adi/sc5xx/sc5xx.h> |
| 13 | #include <asm/arch-adi/sc5xx/spl.h> |
| 14 | |
| 15 | #define REG_TSGENWR0_CNTCR 0x310AE000 |
| 16 | #define REG_PADS0_PCFG0 0x31004604 |
| 17 | #define REG_RCU0_BCODE 0x3108C028 |
| 18 | |
| 19 | #define REG_SPU0_SECUREP_START 0x3108BA00 |
| 20 | #define REG_SPU0_WP_START 0x3108B400 |
| 21 | #define REG_SPU0_SECUREC0 0x3108B980 |
| 22 | |
| 23 | #define REG_SCB5_SPI2_OSPI_REMAP 0x30400000 |
| 24 | #define BITM_SCB5_SPI2_OSPI_REMAP_REMAP 0x00000003 |
| 25 | #define ENUM_SCB5_SPI2_OSPI_REMAP_OSPI0 0x00000001 |
| 26 | |
| 27 | adi_rom_boot_fn adi_rom_boot = (adi_rom_boot_fn)0x000000e4; |
| 28 | |
| 29 | void sc5xx_enable_rgmii(void) |
| 30 | { |
| 31 | writel((readl(REG_PADS0_PCFG0) | 0xc), REG_PADS0_PCFG0); |
| 32 | |
| 33 | // Set dw for little endian operation as well |
| 34 | writel(readl(REG_PADS0_PCFG0) & ~(1 << 19), REG_PADS0_PCFG0); |
| 35 | writel(readl(REG_PADS0_PCFG0) & ~(1 << 20), REG_PADS0_PCFG0); |
| 36 | } |
| 37 | |
| 38 | void sc59x_remap_ospi(void) |
| 39 | { |
| 40 | clrsetbits_le32(REG_SCB5_SPI2_OSPI_REMAP, |
| 41 | BITM_SCB5_SPI2_OSPI_REMAP_REMAP, |
| 42 | ENUM_SCB5_SPI2_OSPI_REMAP_OSPI0); |
| 43 | } |
| 44 | |
| 45 | /** |
| 46 | * SPU/SMPU configuration is the default for permissive access from non-secure |
| 47 | * EL1. If TFA and OPTEE are configured, they run *after* this code, as the |
| 48 | * current boot flow is SPL -> TFA -> OPTEE -> Proper -> Linux, and will |
| 49 | * be expected to configure peripheral security correctly. If they are not |
| 50 | * configured, then this permissive setting will allow Linux (which always |
| 51 | * runs in NS EL1) to control all access to these peripherals. Without it, |
| 52 | * the peripherals would simply be unavailable in a non-security build, |
| 53 | * which is not OK. |
| 54 | */ |
| 55 | void sc5xx_soc_init(void) |
| 56 | { |
| 57 | phys_addr_t smpus[] = { |
| 58 | 0x31007800, //SMPU0 |
| 59 | 0x31083800, //SMPU2 |
| 60 | 0x31084800, //SMPU3 |
| 61 | 0x31085800, //SMPU4 |
| 62 | 0x31086800, //SMPU5 |
| 63 | 0x31087800, //SMPU6 |
| 64 | 0x310A0800, //SMPU9 |
| 65 | 0x310A1800, //SMPU11 |
| 66 | 0x31012800, //SMPU12 |
| 67 | }; |
| 68 | size_t i; |
| 69 | |
| 70 | // Enable coresight timer |
| 71 | writel(1, REG_TSGENWR0_CNTCR); |
| 72 | |
| 73 | //Do not rerun preboot routine -- |
| 74 | // Without this, hardware resets triggered by RCU0_CTL:SYSRST |
| 75 | // lead to a deadlock somewhere in the boot ROM |
| 76 | writel(0x200, REG_RCU0_BCODE); |
| 77 | |
| 78 | /* Alter outstanding transactions property of A55*/ |
| 79 | writel(0x1, 0x30643108); /* SCB6 A55 M0 Ib.fn Mod */ |
| 80 | isb(); |
| 81 | |
| 82 | /* configure DDR prefetch behavior, per ADI */ |
| 83 | writel(0x1, 0x31076000); |
| 84 | |
| 85 | /* configure smart mode, per ADI */ |
| 86 | writel(0x1307, 0x31076004); |
| 87 | |
| 88 | // Disable SPU and SPU WP registers |
| 89 | sc5xx_disable_spu0(REG_SPU0_SECUREP_START, REG_SPU0_SECUREP_START + 4*213); |
| 90 | sc5xx_disable_spu0(REG_SPU0_WP_START, REG_SPU0_WP_START + 4*213); |
| 91 | |
| 92 | /* configure smpus permissively */ |
| 93 | for (i = 0; i < ARRAY_SIZE(smpus); ++i) |
| 94 | writel(0x500, smpus[i]); |
| 95 | |
| 96 | sc5xx_enable_ns_sharc_access(REG_SPU0_SECUREC0); |
| 97 | } |