Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Steve Sakoman | 9b8ea4e | 2010-07-15 16:19:16 -0400 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2010 |
| 4 | * Texas Instruments, <www.ti.com> |
| 5 | * |
pekon gupta | 48e1e15 | 2014-05-08 21:43:47 +0530 | [diff] [blame] | 6 | * Author : |
| 7 | * Mansoor Ahamed <mansoor.ahamed@ti.com> |
| 8 | * |
| 9 | * Initial Code from: |
| 10 | * Manikandan Pillai <mani.pillai@ti.com> |
| 11 | * Richard Woodruff <r-woodruff2@ti.com> |
| 12 | * Syed Mohammed Khasim <khasim@ti.com> |
Steve Sakoman | 9b8ea4e | 2010-07-15 16:19:16 -0400 | [diff] [blame] | 13 | */ |
| 14 | |
Tom Rini | dec7ea0 | 2024-05-20 13:35:03 -0600 | [diff] [blame] | 15 | #include <config.h> |
pekon gupta | 48e1e15 | 2014-05-08 21:43:47 +0530 | [diff] [blame] | 16 | #include <asm/io.h> |
Steve Sakoman | 9b8ea4e | 2010-07-15 16:19:16 -0400 | [diff] [blame] | 17 | #include <asm/arch/cpu.h> |
Moses Christopher | a7038d1 | 2021-06-11 16:13:34 +0000 | [diff] [blame] | 18 | #if IS_ENABLED(CONFIG_TARGET_AM335X_GUARDIAN) |
| 19 | #include <asm/arch/mem-guardian.h> |
| 20 | #else |
pekon gupta | 48e1e15 | 2014-05-08 21:43:47 +0530 | [diff] [blame] | 21 | #include <asm/arch/mem.h> |
Moses Christopher | a7038d1 | 2021-06-11 16:13:34 +0000 | [diff] [blame] | 22 | #endif |
Steve Sakoman | 9b8ea4e | 2010-07-15 16:19:16 -0400 | [diff] [blame] | 23 | #include <asm/arch/sys_proto.h> |
pekon gupta | 48e1e15 | 2014-05-08 21:43:47 +0530 | [diff] [blame] | 24 | #include <command.h> |
| 25 | #include <linux/mtd/omap_gpmc.h> |
Ladislav Michl | 446e94a | 2016-07-12 20:28:17 +0200 | [diff] [blame] | 26 | #include <jffs2/load_kernel.h> |
Steve Sakoman | 9b8ea4e | 2010-07-15 16:19:16 -0400 | [diff] [blame] | 27 | |
Ladislav Michl | d5b1c27 | 2016-07-12 20:28:16 +0200 | [diff] [blame] | 28 | const struct gpmc *gpmc_cfg = (struct gpmc *)GPMC_BASE; |
Steve Sakoman | 9b8ea4e | 2010-07-15 16:19:16 -0400 | [diff] [blame] | 29 | |
Ladislav Michl | 446e94a | 2016-07-12 20:28:17 +0200 | [diff] [blame] | 30 | #if defined(CONFIG_NOR) |
| 31 | char gpmc_cs0_flash = MTD_DEV_TYPE_NOR; |
Miquel Raynal | d093536 | 2019-10-03 19:50:03 +0200 | [diff] [blame] | 32 | #elif defined(CONFIG_MTD_RAW_NAND) || defined(CONFIG_CMD_NAND) |
Ladislav Michl | 446e94a | 2016-07-12 20:28:17 +0200 | [diff] [blame] | 33 | char gpmc_cs0_flash = MTD_DEV_TYPE_NAND; |
| 34 | #elif defined(CONFIG_CMD_ONENAND) |
| 35 | char gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND; |
| 36 | #else |
| 37 | char gpmc_cs0_flash = -1; |
| 38 | #endif |
| 39 | |
pekon gupta | 48e1e15 | 2014-05-08 21:43:47 +0530 | [diff] [blame] | 40 | #if defined(CONFIG_OMAP34XX) |
| 41 | /******************************************************** |
| 42 | * mem_ok() - test used to see if timings are correct |
| 43 | * for a part. Helps in guessing which part |
| 44 | * we are currently using. |
| 45 | *******************************************************/ |
| 46 | u32 mem_ok(u32 cs) |
| 47 | { |
| 48 | u32 val1, val2, addr; |
| 49 | u32 pattern = 0x12345678; |
| 50 | |
| 51 | addr = OMAP34XX_SDRC_CS0 + get_sdr_cs_offset(cs); |
| 52 | |
| 53 | writel(0x0, addr + 0x400); /* clear pos A */ |
| 54 | writel(pattern, addr); /* pattern to pos B */ |
| 55 | writel(0x0, addr + 4); /* remove pattern off the bus */ |
| 56 | val1 = readl(addr + 0x400); /* get pos A value */ |
| 57 | val2 = readl(addr); /* get val2 */ |
| 58 | writel(0x0, addr + 0x400); /* clear pos A */ |
| 59 | |
| 60 | if ((val1 != 0) || (val2 != pattern)) /* see if pos A val changed */ |
| 61 | return 0; |
| 62 | else |
| 63 | return 1; |
| 64 | } |
| 65 | #endif |
| 66 | |
Ladislav Michl | d5b1c27 | 2016-07-12 20:28:16 +0200 | [diff] [blame] | 67 | void enable_gpmc_cs_config(const u32 *gpmc_config, const struct gpmc_cs *cs, |
| 68 | u32 base, u32 size) |
pekon gupta | 48e1e15 | 2014-05-08 21:43:47 +0530 | [diff] [blame] | 69 | { |
| 70 | writel(0, &cs->config7); |
| 71 | sdelay(1000); |
| 72 | /* Delay for settling */ |
| 73 | writel(gpmc_config[0], &cs->config1); |
| 74 | writel(gpmc_config[1], &cs->config2); |
| 75 | writel(gpmc_config[2], &cs->config3); |
| 76 | writel(gpmc_config[3], &cs->config4); |
| 77 | writel(gpmc_config[4], &cs->config5); |
| 78 | writel(gpmc_config[5], &cs->config6); |
| 79 | /* Enable the config */ |
| 80 | writel((((size & 0xF) << 8) | ((base >> 24) & 0x3F) | |
| 81 | (1 << 6)), &cs->config7); |
| 82 | sdelay(2000); |
| 83 | } |
| 84 | |
Ladislav Michl | 446e94a | 2016-07-12 20:28:17 +0200 | [diff] [blame] | 85 | void set_gpmc_cs0(int flash_type) |
| 86 | { |
| 87 | const u32 *gpmc_regs; |
| 88 | u32 base, size; |
| 89 | #if defined(CONFIG_NOR) |
| 90 | const u32 gpmc_regs_nor[GPMC_MAX_REG] = { |
| 91 | STNOR_GPMC_CONFIG1, |
| 92 | STNOR_GPMC_CONFIG2, |
| 93 | STNOR_GPMC_CONFIG3, |
| 94 | STNOR_GPMC_CONFIG4, |
| 95 | STNOR_GPMC_CONFIG5, |
| 96 | STNOR_GPMC_CONFIG6, |
| 97 | STNOR_GPMC_CONFIG7 |
| 98 | }; |
| 99 | #endif |
Miquel Raynal | d093536 | 2019-10-03 19:50:03 +0200 | [diff] [blame] | 100 | #if defined(CONFIG_MTD_RAW_NAND) || defined(CONFIG_CMD_NAND) |
Ladislav Michl | 446e94a | 2016-07-12 20:28:17 +0200 | [diff] [blame] | 101 | const u32 gpmc_regs_nand[GPMC_MAX_REG] = { |
| 102 | M_NAND_GPMC_CONFIG1, |
| 103 | M_NAND_GPMC_CONFIG2, |
| 104 | M_NAND_GPMC_CONFIG3, |
| 105 | M_NAND_GPMC_CONFIG4, |
| 106 | M_NAND_GPMC_CONFIG5, |
| 107 | M_NAND_GPMC_CONFIG6, |
| 108 | 0 |
| 109 | }; |
| 110 | #endif |
| 111 | #if defined(CONFIG_CMD_ONENAND) |
| 112 | const u32 gpmc_regs_onenand[GPMC_MAX_REG] = { |
| 113 | ONENAND_GPMC_CONFIG1, |
| 114 | ONENAND_GPMC_CONFIG2, |
| 115 | ONENAND_GPMC_CONFIG3, |
| 116 | ONENAND_GPMC_CONFIG4, |
| 117 | ONENAND_GPMC_CONFIG5, |
| 118 | ONENAND_GPMC_CONFIG6, |
| 119 | 0 |
| 120 | }; |
| 121 | #endif |
| 122 | |
| 123 | switch (flash_type) { |
| 124 | #if defined(CONFIG_NOR) |
| 125 | case MTD_DEV_TYPE_NOR: |
| 126 | gpmc_regs = gpmc_regs_nor; |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 127 | base = CFG_SYS_FLASH_BASE; |
| 128 | size = (CFG_SYS_FLASH_SIZE > 0x08000000) ? GPMC_SIZE_256M : |
| 129 | ((CFG_SYS_FLASH_SIZE > 0x04000000) ? GPMC_SIZE_128M : |
| 130 | ((CFG_SYS_FLASH_SIZE > 0x02000000) ? GPMC_SIZE_64M : |
| 131 | ((CFG_SYS_FLASH_SIZE > 0x01000000) ? GPMC_SIZE_32M : |
Ladislav Michl | 446e94a | 2016-07-12 20:28:17 +0200 | [diff] [blame] | 132 | GPMC_SIZE_16M))); |
| 133 | break; |
| 134 | #endif |
Miquel Raynal | d093536 | 2019-10-03 19:50:03 +0200 | [diff] [blame] | 135 | #if defined(CONFIG_MTD_RAW_NAND) || defined(CONFIG_CMD_NAND) |
Ladislav Michl | 446e94a | 2016-07-12 20:28:17 +0200 | [diff] [blame] | 136 | case MTD_DEV_TYPE_NAND: |
| 137 | gpmc_regs = gpmc_regs_nand; |
Tom Rini | b421349 | 2022-11-12 17:36:51 -0500 | [diff] [blame] | 138 | base = CFG_SYS_NAND_BASE; |
Ladislav Michl | 446e94a | 2016-07-12 20:28:17 +0200 | [diff] [blame] | 139 | size = GPMC_SIZE_16M; |
| 140 | break; |
| 141 | #endif |
| 142 | #if defined(CONFIG_CMD_ONENAND) |
| 143 | case MTD_DEV_TYPE_ONENAND: |
| 144 | gpmc_regs = gpmc_regs_onenand; |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 145 | base = CFG_SYS_ONENAND_BASE; |
Ladislav Michl | 446e94a | 2016-07-12 20:28:17 +0200 | [diff] [blame] | 146 | size = GPMC_SIZE_128M; |
| 147 | break; |
| 148 | #endif |
| 149 | default: |
| 150 | /* disable the GPMC0 config set by ROM code */ |
| 151 | writel(0, &gpmc_cfg->cs[0].config7); |
| 152 | sdelay(1000); |
| 153 | return; |
| 154 | } |
| 155 | |
| 156 | /* enable chip-select specific configurations */ |
| 157 | enable_gpmc_cs_config(gpmc_regs, &gpmc_cfg->cs[0], base, size); |
| 158 | } |
| 159 | |
Steve Sakoman | 9b8ea4e | 2010-07-15 16:19:16 -0400 | [diff] [blame] | 160 | /***************************************************** |
| 161 | * gpmc_init(): init gpmc bus |
pekon gupta | 48e1e15 | 2014-05-08 21:43:47 +0530 | [diff] [blame] | 162 | * Init GPMC for x16, MuxMode (SDRAM in x32). |
Steve Sakoman | 9b8ea4e | 2010-07-15 16:19:16 -0400 | [diff] [blame] | 163 | * This code can only be executed from SRAM or SDRAM. |
| 164 | *****************************************************/ |
| 165 | void gpmc_init(void) |
| 166 | { |
Steve Sakoman | 9b8ea4e | 2010-07-15 16:19:16 -0400 | [diff] [blame] | 167 | /* global settings */ |
pekon gupta | 48e1e15 | 2014-05-08 21:43:47 +0530 | [diff] [blame] | 168 | writel(0x00000008, &gpmc_cfg->sysconfig); |
| 169 | writel(0x00000000, &gpmc_cfg->irqstatus); |
| 170 | writel(0x00000000, &gpmc_cfg->irqenable); |
Stefano Babic | 18db567 | 2014-06-17 16:47:40 +0200 | [diff] [blame] | 171 | /* disable timeout, set a safe reset value */ |
| 172 | writel(0x00001ff0, &gpmc_cfg->timeout_control); |
Ladislav Michl | 446e94a | 2016-07-12 20:28:17 +0200 | [diff] [blame] | 173 | writel(gpmc_cs0_flash == MTD_DEV_TYPE_NOR ? |
| 174 | 0x00000200 : 0x00000012, &gpmc_cfg->config); |
| 175 | |
| 176 | set_gpmc_cs0(gpmc_cs0_flash); |
Steve Sakoman | 9b8ea4e | 2010-07-15 16:19:16 -0400 | [diff] [blame] | 177 | } |