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Yanhong Wange28ec342023-03-29 11:42:08 +08001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2022 StarFive Technology Co., Ltd.
4 * Author: Yanhong Wang<yanhong.wang@starfivetech.com>
5 */
Yanhong Wangf69a5122023-06-15 17:36:51 +08006#include <common.h>
7#include <asm/arch/eeprom.h>
Yanhong Wange28ec342023-03-29 11:42:08 +08008#include <asm/csr.h>
9#include <asm/sections.h>
10#include <dm.h>
Yanhong Wangf69a5122023-06-15 17:36:51 +080011#include <linux/sizes.h>
Yanhong Wange28ec342023-03-29 11:42:08 +080012#include <log.h>
Yanhong Wangf69a5122023-06-15 17:36:51 +080013#include <init.h>
Yanhong Wange28ec342023-03-29 11:42:08 +080014
15#define CSR_U74_FEATURE_DISABLE 0x7c1
Yanhong Wange28ec342023-03-29 11:42:08 +080016
Yanhong Wangf69a5122023-06-15 17:36:51 +080017DECLARE_GLOBAL_DATA_PTR;
18
19static bool check_ddr_size(phys_size_t size)
20{
21 switch (size) {
22 case SZ_2:
23 case SZ_4:
24 case SZ_8:
25 case SZ_16:
26 return true;
27 default:
28 return false;
29 }
30}
31
Yanhong Wange28ec342023-03-29 11:42:08 +080032int spl_soc_init(void)
33{
34 int ret;
35 struct udevice *dev;
Yanhong Wangf69a5122023-06-15 17:36:51 +080036 phys_size_t size;
37
38 ret = fdtdec_setup_mem_size_base();
39 if (ret)
40 return ret;
41
42 /* Read the definition of the DDR size from eeprom, and if not,
43 * use the definition in DT
44 */
45 size = (get_ddr_size_from_eeprom() >> 16) & 0xFF;
46 if (check_ddr_size(size))
47 gd->ram_size = size << 30;
Yanhong Wange28ec342023-03-29 11:42:08 +080048
49 /* DDR init */
50 ret = uclass_get_device(UCLASS_RAM, 0, &dev);
51 if (ret) {
52 debug("DRAM init failed: %d\n", ret);
53 return ret;
54 }
55
56 return 0;
57}
58
59void harts_early_init(void)
60{
Yanhong Wange28ec342023-03-29 11:42:08 +080061 /*
62 * Feature Disable CSR
63 *
64 * Clear feature disable CSR to '0' to turn on all features for
65 * each core. This operation must be in M-mode.
66 */
67 if (CONFIG_IS_ENABLED(RISCV_MMODE))
68 csr_write(CSR_U74_FEATURE_DISABLE, 0);
Yanhong Wange28ec342023-03-29 11:42:08 +080069}