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git01.mediatek.com / filogic / uboot / 322b57b60b18803bfd8d3aa323d03df56674cc2d / . / board / xilinx / zynq / zynq-zybo / ps7_init_gpl.c
blob: 84625f07462e182c61e6934efdc7a51cc2e35400 [file] [log] [blame]
Nathan Rossi4eeed0e2015-11-24 19:34:09 +1000[diff] [blame]1/*
2 * Copyright (c) Xilinx, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
Michal Simek322b57b2017-11-10 11:00:42 +0100[diff] [blame^]7#include <asm/arch/ps7_init_gpl.h>
Nathan Rossi4eeed0e2015-11-24 19:34:09 +1000[diff] [blame]8
9unsigned long ps7_pll_init_data_3_0[] = {
10 /* START: top */
11 /* .. START: SLCR SETTINGS */
12 /* .. UNLOCK_KEY = 0XDF0D */
13 /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
14 /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */
15 /* .. */
16 EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
17 /* .. FINISH: SLCR SETTINGS */
18 /* .. START: PLL SLCR REGISTERS */
19 /* .. .. START: ARM PLL INIT */
20 /* .. .. PLL_RES = 0xc */
21 /* .. .. ==> 0XF8000110[7:4] = 0x0000000CU */
22 /* .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U */
23 /* .. .. PLL_CP = 0x2 */
24 /* .. .. ==> 0XF8000110[11:8] = 0x00000002U */
25 /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */
26 /* .. .. LOCK_CNT = 0x177 */
27 /* .. .. ==> 0XF8000110[21:12] = 0x00000177U */
28 /* .. .. ==> MASK : 0x003FF000U VAL : 0x00177000U */
29 /* .. .. */
30 EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x001772C0U),
31 /* .. .. .. START: UPDATE FB_DIV */
32 /* .. .. .. PLL_FDIV = 0x1a */
33 /* .. .. .. ==> 0XF8000100[18:12] = 0x0000001AU */
34 /* .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001A000U */
35 /* .. .. .. */
36 EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x0001A000U),
37 /* .. .. .. FINISH: UPDATE FB_DIV */
38 /* .. .. .. START: BY PASS PLL */
39 /* .. .. .. PLL_BYPASS_FORCE = 1 */
40 /* .. .. .. ==> 0XF8000100[4:4] = 0x00000001U */
41 /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U */
42 /* .. .. .. */
43 EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U),
44 /* .. .. .. FINISH: BY PASS PLL */
45 /* .. .. .. START: ASSERT RESET */
46 /* .. .. .. PLL_RESET = 1 */
47 /* .. .. .. ==> 0XF8000100[0:0] = 0x00000001U */
48 /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
49 /* .. .. .. */
50 EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U),
51 /* .. .. .. FINISH: ASSERT RESET */
52 /* .. .. .. START: DEASSERT RESET */
53 /* .. .. .. PLL_RESET = 0 */
54 /* .. .. .. ==> 0XF8000100[0:0] = 0x00000000U */
55 /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
56 /* .. .. .. */
57 EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U),
58 /* .. .. .. FINISH: DEASSERT RESET */
59 /* .. .. .. START: CHECK PLL STATUS */
60 /* .. .. .. ARM_PLL_LOCK = 1 */
61 /* .. .. .. ==> 0XF800010C[0:0] = 0x00000001U */
62 /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
63 /* .. .. .. */
64 EMIT_MASKPOLL(0XF800010C, 0x00000001U),
65 /* .. .. .. FINISH: CHECK PLL STATUS */
66 /* .. .. .. START: REMOVE PLL BY PASS */
67 /* .. .. .. PLL_BYPASS_FORCE = 0 */
68 /* .. .. .. ==> 0XF8000100[4:4] = 0x00000000U */
69 /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
70 /* .. .. .. */
71 EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U),
72 /* .. .. .. FINISH: REMOVE PLL BY PASS */
73 /* .. .. .. SRCSEL = 0x0 */
74 /* .. .. .. ==> 0XF8000120[5:4] = 0x00000000U */
75 /* .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
76 /* .. .. .. DIVISOR = 0x2 */
77 /* .. .. .. ==> 0XF8000120[13:8] = 0x00000002U */
78 /* .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U */
79 /* .. .. .. CPU_6OR4XCLKACT = 0x1 */
80 /* .. .. .. ==> 0XF8000120[24:24] = 0x00000001U */
81 /* .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U */
82 /* .. .. .. CPU_3OR2XCLKACT = 0x1 */
83 /* .. .. .. ==> 0XF8000120[25:25] = 0x00000001U */
84 /* .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U */
85 /* .. .. .. CPU_2XCLKACT = 0x1 */
86 /* .. .. .. ==> 0XF8000120[26:26] = 0x00000001U */
87 /* .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U */
88 /* .. .. .. CPU_1XCLKACT = 0x1 */
89 /* .. .. .. ==> 0XF8000120[27:27] = 0x00000001U */
90 /* .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U */
91 /* .. .. .. CPU_PERI_CLKACT = 0x1 */
92 /* .. .. .. ==> 0XF8000120[28:28] = 0x00000001U */
93 /* .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U */
94 /* .. .. .. */
95 EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U),
96 /* .. .. FINISH: ARM PLL INIT */
97 /* .. .. START: DDR PLL INIT */
98 /* .. .. PLL_RES = 0xc */
99 /* .. .. ==> 0XF8000114[7:4] = 0x0000000CU */
100 /* .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U */
101 /* .. .. PLL_CP = 0x2 */
102 /* .. .. ==> 0XF8000114[11:8] = 0x00000002U */
103 /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */
104 /* .. .. LOCK_CNT = 0x1db */
105 /* .. .. ==> 0XF8000114[21:12] = 0x000001DBU */
106 /* .. .. ==> MASK : 0x003FF000U VAL : 0x001DB000U */
107 /* .. .. */
108 EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x001DB2C0U),
109 /* .. .. .. START: UPDATE FB_DIV */
110 /* .. .. .. PLL_FDIV = 0x15 */
111 /* .. .. .. ==> 0XF8000104[18:12] = 0x00000015U */
112 /* .. .. .. ==> MASK : 0x0007F000U VAL : 0x00015000U */
113 /* .. .. .. */
114 EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00015000U),
115 /* .. .. .. FINISH: UPDATE FB_DIV */
116 /* .. .. .. START: BY PASS PLL */
117 /* .. .. .. PLL_BYPASS_FORCE = 1 */
118 /* .. .. .. ==> 0XF8000104[4:4] = 0x00000001U */
119 /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U */
120 /* .. .. .. */
121 EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U),
122 /* .. .. .. FINISH: BY PASS PLL */
123 /* .. .. .. START: ASSERT RESET */
124 /* .. .. .. PLL_RESET = 1 */
125 /* .. .. .. ==> 0XF8000104[0:0] = 0x00000001U */
126 /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
127 /* .. .. .. */
128 EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U),
129 /* .. .. .. FINISH: ASSERT RESET */
130 /* .. .. .. START: DEASSERT RESET */
131 /* .. .. .. PLL_RESET = 0 */
132 /* .. .. .. ==> 0XF8000104[0:0] = 0x00000000U */
133 /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
134 /* .. .. .. */
135 EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U),
136 /* .. .. .. FINISH: DEASSERT RESET */
137 /* .. .. .. START: CHECK PLL STATUS */
138 /* .. .. .. DDR_PLL_LOCK = 1 */
139 /* .. .. .. ==> 0XF800010C[1:1] = 0x00000001U */
140 /* .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */
141 /* .. .. .. */
142 EMIT_MASKPOLL(0XF800010C, 0x00000002U),
143 /* .. .. .. FINISH: CHECK PLL STATUS */
144 /* .. .. .. START: REMOVE PLL BY PASS */
145 /* .. .. .. PLL_BYPASS_FORCE = 0 */
146 /* .. .. .. ==> 0XF8000104[4:4] = 0x00000000U */
147 /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
148 /* .. .. .. */
149 EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U),
150 /* .. .. .. FINISH: REMOVE PLL BY PASS */
151 /* .. .. .. DDR_3XCLKACT = 0x1 */
152 /* .. .. .. ==> 0XF8000124[0:0] = 0x00000001U */
153 /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
154 /* .. .. .. DDR_2XCLKACT = 0x1 */
155 /* .. .. .. ==> 0XF8000124[1:1] = 0x00000001U */
156 /* .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */
157 /* .. .. .. DDR_3XCLK_DIVISOR = 0x2 */
158 /* .. .. .. ==> 0XF8000124[25:20] = 0x00000002U */
159 /* .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U */
160 /* .. .. .. DDR_2XCLK_DIVISOR = 0x3 */
161 /* .. .. .. ==> 0XF8000124[31:26] = 0x00000003U */
162 /* .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U */
163 /* .. .. .. */
164 EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U),
165 /* .. .. FINISH: DDR PLL INIT */
166 /* .. .. START: IO PLL INIT */
167 /* .. .. PLL_RES = 0xc */
168 /* .. .. ==> 0XF8000118[7:4] = 0x0000000CU */
169 /* .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U */
170 /* .. .. PLL_CP = 0x2 */
171 /* .. .. ==> 0XF8000118[11:8] = 0x00000002U */
172 /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */
173 /* .. .. LOCK_CNT = 0x1f4 */
174 /* .. .. ==> 0XF8000118[21:12] = 0x000001F4U */
175 /* .. .. ==> MASK : 0x003FF000U VAL : 0x001F4000U */
176 /* .. .. */
177 EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x001F42C0U),
178 /* .. .. .. START: UPDATE FB_DIV */
179 /* .. .. .. PLL_FDIV = 0x14 */
180 /* .. .. .. ==> 0XF8000108[18:12] = 0x00000014U */
181 /* .. .. .. ==> MASK : 0x0007F000U VAL : 0x00014000U */
182 /* .. .. .. */
183 EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x00014000U),
184 /* .. .. .. FINISH: UPDATE FB_DIV */
185 /* .. .. .. START: BY PASS PLL */
186 /* .. .. .. PLL_BYPASS_FORCE = 1 */
187 /* .. .. .. ==> 0XF8000108[4:4] = 0x00000001U */
188 /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U */
189 /* .. .. .. */
190 EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U),
191 /* .. .. .. FINISH: BY PASS PLL */
192 /* .. .. .. START: ASSERT RESET */
193 /* .. .. .. PLL_RESET = 1 */
194 /* .. .. .. ==> 0XF8000108[0:0] = 0x00000001U */
195 /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
196 /* .. .. .. */
197 EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U),
198 /* .. .. .. FINISH: ASSERT RESET */
199 /* .. .. .. START: DEASSERT RESET */
200 /* .. .. .. PLL_RESET = 0 */
201 /* .. .. .. ==> 0XF8000108[0:0] = 0x00000000U */
202 /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
203 /* .. .. .. */
204 EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U),
205 /* .. .. .. FINISH: DEASSERT RESET */
206 /* .. .. .. START: CHECK PLL STATUS */
207 /* .. .. .. IO_PLL_LOCK = 1 */
208 /* .. .. .. ==> 0XF800010C[2:2] = 0x00000001U */
209 /* .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U */
210 /* .. .. .. */
211 EMIT_MASKPOLL(0XF800010C, 0x00000004U),
212 /* .. .. .. FINISH: CHECK PLL STATUS */
213 /* .. .. .. START: REMOVE PLL BY PASS */
214 /* .. .. .. PLL_BYPASS_FORCE = 0 */
215 /* .. .. .. ==> 0XF8000108[4:4] = 0x00000000U */
216 /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
217 /* .. .. .. */
218 EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U),
219 /* .. .. .. FINISH: REMOVE PLL BY PASS */
220 /* .. .. FINISH: IO PLL INIT */
221 /* .. FINISH: PLL SLCR REGISTERS */
222 /* .. START: LOCK IT BACK */
223 /* .. LOCK_KEY = 0X767B */
224 /* .. ==> 0XF8000004[15:0] = 0x0000767BU */
225 /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */
226 /* .. */
227 EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
228 /* .. FINISH: LOCK IT BACK */
229 /* FINISH: top */
230 /* */
231 EMIT_EXIT(),
232
233 /* */
234};
235
236unsigned long ps7_clock_init_data_3_0[] = {
237 /* START: top */
238 /* .. START: SLCR SETTINGS */
239 /* .. UNLOCK_KEY = 0XDF0D */
240 /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
241 /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */
242 /* .. */
243 EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
244 /* .. FINISH: SLCR SETTINGS */
245 /* .. START: CLOCK CONTROL SLCR REGISTERS */
246 /* .. CLKACT = 0x1 */
247 /* .. ==> 0XF8000128[0:0] = 0x00000001U */
248 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
249 /* .. DIVISOR0 = 0x34 */
250 /* .. ==> 0XF8000128[13:8] = 0x00000034U */
251 /* .. ==> MASK : 0x00003F00U VAL : 0x00003400U */
252 /* .. DIVISOR1 = 0x2 */
253 /* .. ==> 0XF8000128[25:20] = 0x00000002U */
254 /* .. ==> MASK : 0x03F00000U VAL : 0x00200000U */
255 /* .. */
256 EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00203401U),
257 /* .. CLKACT = 0x1 */
258 /* .. ==> 0XF8000138[0:0] = 0x00000001U */
259 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
260 /* .. SRCSEL = 0x0 */
261 /* .. ==> 0XF8000138[4:4] = 0x00000000U */
262 /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */
263 /* .. */
264 EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000001U),
265 /* .. CLKACT = 0x1 */
266 /* .. ==> 0XF8000140[0:0] = 0x00000001U */
267 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
268 /* .. SRCSEL = 0x0 */
269 /* .. ==> 0XF8000140[6:4] = 0x00000000U */
270 /* .. ==> MASK : 0x00000070U VAL : 0x00000000U */
271 /* .. DIVISOR = 0x8 */
272 /* .. ==> 0XF8000140[13:8] = 0x00000008U */
273 /* .. ==> MASK : 0x00003F00U VAL : 0x00000800U */
274 /* .. DIVISOR1 = 0x1 */
275 /* .. ==> 0XF8000140[25:20] = 0x00000001U */
276 /* .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
277 /* .. */
278 EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00100801U),
279 /* .. CLKACT = 0x1 */
280 /* .. ==> 0XF800014C[0:0] = 0x00000001U */
281 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
282 /* .. SRCSEL = 0x0 */
283 /* .. ==> 0XF800014C[5:4] = 0x00000000U */
284 /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */
285 /* .. DIVISOR = 0x5 */
286 /* .. ==> 0XF800014C[13:8] = 0x00000005U */
287 /* .. ==> MASK : 0x00003F00U VAL : 0x00000500U */
288 /* .. */
289 EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000501U),
290 /* .. CLKACT0 = 0x1 */
291 /* .. ==> 0XF8000150[0:0] = 0x00000001U */
292 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
293 /* .. CLKACT1 = 0x0 */
294 /* .. ==> 0XF8000150[1:1] = 0x00000000U */
295 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
296 /* .. SRCSEL = 0x0 */
297 /* .. ==> 0XF8000150[5:4] = 0x00000000U */
298 /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */
299 /* .. DIVISOR = 0x14 */
300 /* .. ==> 0XF8000150[13:8] = 0x00000014U */
301 /* .. ==> MASK : 0x00003F00U VAL : 0x00001400U */
302 /* .. */
303 EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00001401U),
304 /* .. CLKACT0 = 0x0 */
305 /* .. ==> 0XF8000154[0:0] = 0x00000000U */
306 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
307 /* .. CLKACT1 = 0x1 */
308 /* .. ==> 0XF8000154[1:1] = 0x00000001U */
309 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
310 /* .. SRCSEL = 0x0 */
311 /* .. ==> 0XF8000154[5:4] = 0x00000000U */
312 /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */
Michal Simek264065f2016-03-03 13:25:03 +0100[diff] [blame]313 /* .. DIVISOR = 0xa */
314 /* .. ==> 0XF8000154[13:8] = 0x0000000AU */
315 /* .. ==> MASK : 0x00003F00U VAL : 0x00000A00U */
Nathan Rossi4eeed0e2015-11-24 19:34:09 +1000[diff] [blame]316 /* .. */
Michal Simek264065f2016-03-03 13:25:03 +0100[diff] [blame]317 EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A02U),
Nathan Rossi4eeed0e2015-11-24 19:34:09 +1000[diff] [blame]318 /* .. .. START: TRACE CLOCK */
319 /* .. .. FINISH: TRACE CLOCK */
320 /* .. .. CLKACT = 0x1 */
321 /* .. .. ==> 0XF8000168[0:0] = 0x00000001U */
322 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
323 /* .. .. SRCSEL = 0x0 */
324 /* .. .. ==> 0XF8000168[5:4] = 0x00000000U */
325 /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
326 /* .. .. DIVISOR = 0x5 */
327 /* .. .. ==> 0XF8000168[13:8] = 0x00000005U */
328 /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U */
329 /* .. .. */
330 EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000501U),
331 /* .. .. SRCSEL = 0x0 */
332 /* .. .. ==> 0XF8000170[5:4] = 0x00000000U */
333 /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
334 /* .. .. DIVISOR0 = 0xa */
335 /* .. .. ==> 0XF8000170[13:8] = 0x0000000AU */
336 /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U */
337 /* .. .. DIVISOR1 = 0x1 */
338 /* .. .. ==> 0XF8000170[25:20] = 0x00000001U */
339 /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
340 /* .. .. */
341 EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00100A00U),
Michal Simek264065f2016-03-03 13:25:03 +0100[diff] [blame]342 /* .. .. SRCSEL = 0x0 */
343 /* .. .. ==> 0XF8000180[5:4] = 0x00000000U */
344 /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
345 /* .. .. DIVISOR0 = 0x7 */
346 /* .. .. ==> 0XF8000180[13:8] = 0x00000007U */
347 /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000700U */
Nathan Rossi4eeed0e2015-11-24 19:34:09 +1000[diff] [blame]348 /* .. .. DIVISOR1 = 0x1 */
349 /* .. .. ==> 0XF8000180[25:20] = 0x00000001U */
350 /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
351 /* .. .. */
Michal Simek264065f2016-03-03 13:25:03 +0100[diff] [blame]352 EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100700U),
353 /* .. .. SRCSEL = 0x0 */
354 /* .. .. ==> 0XF8000190[5:4] = 0x00000000U */
355 /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
356 /* .. .. DIVISOR0 = 0x5 */
357 /* .. .. ==> 0XF8000190[13:8] = 0x00000005U */
358 /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U */
359 /* .. .. DIVISOR1 = 0x1 */
360 /* .. .. ==> 0XF8000190[25:20] = 0x00000001U */
361 /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
Nathan Rossi4eeed0e2015-11-24 19:34:09 +1000[diff] [blame]362 /* .. .. */
Michal Simek264065f2016-03-03 13:25:03 +0100[diff] [blame]363 EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00100500U),
Nathan Rossi4eeed0e2015-11-24 19:34:09 +1000[diff] [blame]364 /* .. .. SRCSEL = 0x0 */
365 /* .. .. ==> 0XF80001A0[5:4] = 0x00000000U */
366 /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
Michal Simek264065f2016-03-03 13:25:03 +0100[diff] [blame]367 /* .. .. DIVISOR0 = 0x14 */
368 /* .. .. ==> 0XF80001A0[13:8] = 0x00000014U */
369 /* .. .. ==> MASK : 0x00003F00U VAL : 0x00001400U */
Nathan Rossi4eeed0e2015-11-24 19:34:09 +1000[diff] [blame]370 /* .. .. DIVISOR1 = 0x1 */
371 /* .. .. ==> 0XF80001A0[25:20] = 0x00000001U */
372 /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
373 /* .. .. */
Michal Simek264065f2016-03-03 13:25:03 +0100[diff] [blame]374 EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00101400U),
Nathan Rossi4eeed0e2015-11-24 19:34:09 +1000[diff] [blame]375 /* .. .. CLK_621_TRUE = 0x1 */
376 /* .. .. ==> 0XF80001C4[0:0] = 0x00000001U */
377 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
378 /* .. .. */
379 EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U),
380 /* .. .. DMA_CPU_2XCLKACT = 0x1 */
381 /* .. .. ==> 0XF800012C[0:0] = 0x00000001U */
382 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
383 /* .. .. USB0_CPU_1XCLKACT = 0x1 */
384 /* .. .. ==> 0XF800012C[2:2] = 0x00000001U */
385 /* .. .. ==> MASK : 0x00000004U VAL : 0x00000004U */
386 /* .. .. USB1_CPU_1XCLKACT = 0x1 */
387 /* .. .. ==> 0XF800012C[3:3] = 0x00000001U */
388 /* .. .. ==> MASK : 0x00000008U VAL : 0x00000008U */
389 /* .. .. GEM0_CPU_1XCLKACT = 0x1 */
390 /* .. .. ==> 0XF800012C[6:6] = 0x00000001U */
391 /* .. .. ==> MASK : 0x00000040U VAL : 0x00000040U */
392 /* .. .. GEM1_CPU_1XCLKACT = 0x0 */
393 /* .. .. ==> 0XF800012C[7:7] = 0x00000000U */
394 /* .. .. ==> MASK : 0x00000080U VAL : 0x00000000U */
395 /* .. .. SDI0_CPU_1XCLKACT = 0x1 */
396 /* .. .. ==> 0XF800012C[10:10] = 0x00000001U */
397 /* .. .. ==> MASK : 0x00000400U VAL : 0x00000400U */
398 /* .. .. SDI1_CPU_1XCLKACT = 0x0 */
399 /* .. .. ==> 0XF800012C[11:11] = 0x00000000U */
400 /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */
401 /* .. .. SPI0_CPU_1XCLKACT = 0x0 */
402 /* .. .. ==> 0XF800012C[14:14] = 0x00000000U */
403 /* .. .. ==> MASK : 0x00004000U VAL : 0x00000000U */
404 /* .. .. SPI1_CPU_1XCLKACT = 0x0 */
405 /* .. .. ==> 0XF800012C[15:15] = 0x00000000U */
406 /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */
407 /* .. .. CAN0_CPU_1XCLKACT = 0x0 */
408 /* .. .. ==> 0XF800012C[16:16] = 0x00000000U */
409 /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
410 /* .. .. CAN1_CPU_1XCLKACT = 0x0 */
411 /* .. .. ==> 0XF800012C[17:17] = 0x00000000U */
412 /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
413 /* .. .. I2C0_CPU_1XCLKACT = 0x1 */
414 /* .. .. ==> 0XF800012C[18:18] = 0x00000001U */
415 /* .. .. ==> MASK : 0x00040000U VAL : 0x00040000U */
416 /* .. .. I2C1_CPU_1XCLKACT = 0x1 */
417 /* .. .. ==> 0XF800012C[19:19] = 0x00000001U */
418 /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */
419 /* .. .. UART0_CPU_1XCLKACT = 0x0 */
420 /* .. .. ==> 0XF800012C[20:20] = 0x00000000U */
421 /* .. .. ==> MASK : 0x00100000U VAL : 0x00000000U */
422 /* .. .. UART1_CPU_1XCLKACT = 0x1 */
423 /* .. .. ==> 0XF800012C[21:21] = 0x00000001U */
424 /* .. .. ==> MASK : 0x00200000U VAL : 0x00200000U */
425 /* .. .. GPIO_CPU_1XCLKACT = 0x1 */
426 /* .. .. ==> 0XF800012C[22:22] = 0x00000001U */
427 /* .. .. ==> MASK : 0x00400000U VAL : 0x00400000U */
428 /* .. .. LQSPI_CPU_1XCLKACT = 0x1 */
429 /* .. .. ==> 0XF800012C[23:23] = 0x00000001U */
430 /* .. .. ==> MASK : 0x00800000U VAL : 0x00800000U */
431 /* .. .. SMC_CPU_1XCLKACT = 0x1 */
432 /* .. .. ==> 0XF800012C[24:24] = 0x00000001U */
433 /* .. .. ==> MASK : 0x01000000U VAL : 0x01000000U */
434 /* .. .. */
435 EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01EC044DU),
436 /* .. FINISH: CLOCK CONTROL SLCR REGISTERS */
437 /* .. START: THIS SHOULD BE BLANK */
438 /* .. FINISH: THIS SHOULD BE BLANK */
439 /* .. START: LOCK IT BACK */
440 /* .. LOCK_KEY = 0X767B */
441 /* .. ==> 0XF8000004[15:0] = 0x0000767BU */
442 /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */
443 /* .. */
444 EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
445 /* .. FINISH: LOCK IT BACK */
446 /* FINISH: top */
447 /* */
448 EMIT_EXIT(),
449
450 /* */
451};
452
453unsigned long ps7_ddr_init_data_3_0[] = {
454 /* START: top */
455 /* .. START: DDR INITIALIZATION */
456 /* .. .. START: LOCK DDR */
457 /* .. .. reg_ddrc_soft_rstb = 0 */
458 /* .. .. ==> 0XF8006000[0:0] = 0x00000000U */
459 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
460 /* .. .. reg_ddrc_powerdown_en = 0x0 */
461 /* .. .. ==> 0XF8006000[1:1] = 0x00000000U */
462 /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
463 /* .. .. reg_ddrc_data_bus_width = 0x0 */
464 /* .. .. ==> 0XF8006000[3:2] = 0x00000000U */
465 /* .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U */
466 /* .. .. reg_ddrc_burst8_refresh = 0x0 */
467 /* .. .. ==> 0XF8006000[6:4] = 0x00000000U */
468 /* .. .. ==> MASK : 0x00000070U VAL : 0x00000000U */
469 /* .. .. reg_ddrc_rdwr_idle_gap = 0x1 */
470 /* .. .. ==> 0XF8006000[13:7] = 0x00000001U */
471 /* .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U */
472 /* .. .. reg_ddrc_dis_rd_bypass = 0x0 */
473 /* .. .. ==> 0XF8006000[14:14] = 0x00000000U */
474 /* .. .. ==> MASK : 0x00004000U VAL : 0x00000000U */
475 /* .. .. reg_ddrc_dis_act_bypass = 0x0 */
476 /* .. .. ==> 0XF8006000[15:15] = 0x00000000U */
477 /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */
478 /* .. .. reg_ddrc_dis_auto_refresh = 0x0 */
479 /* .. .. ==> 0XF8006000[16:16] = 0x00000000U */
480 /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
481 /* .. .. */
482 EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U),
483 /* .. .. FINISH: LOCK DDR */
484 /* .. .. reg_ddrc_t_rfc_nom_x32 = 0x7f */
485 /* .. .. ==> 0XF8006004[11:0] = 0x0000007FU */
486 /* .. .. ==> MASK : 0x00000FFFU VAL : 0x0000007FU */
487 /* .. .. reserved_reg_ddrc_active_ranks = 0x1 */
488 /* .. .. ==> 0XF8006004[13:12] = 0x00000001U */
489 /* .. .. ==> MASK : 0x00003000U VAL : 0x00001000U */
490 /* .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 */
491 /* .. .. ==> 0XF8006004[18:14] = 0x00000000U */
492 /* .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U */
493 /* .. .. */
494 EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU, 0x0000107FU),
495 /* .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf */
496 /* .. .. ==> 0XF8006008[10:0] = 0x0000000FU */
497 /* .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU */
498 /* .. .. reg_ddrc_hpr_max_starve_x32 = 0xf */
499 /* .. .. ==> 0XF8006008[21:11] = 0x0000000FU */
500 /* .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U */
501 /* .. .. reg_ddrc_hpr_xact_run_length = 0xf */
502 /* .. .. ==> 0XF8006008[25:22] = 0x0000000FU */
503 /* .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U */
504 /* .. .. */
505 EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU),
506 /* .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 */
507 /* .. .. ==> 0XF800600C[10:0] = 0x00000001U */
508 /* .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U */
509 /* .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 */
510 /* .. .. ==> 0XF800600C[21:11] = 0x00000002U */
511 /* .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U */
512 /* .. .. reg_ddrc_lpr_xact_run_length = 0x8 */
513 /* .. .. ==> 0XF800600C[25:22] = 0x00000008U */
514 /* .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U */
515 /* .. .. */
516 EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U),
517 /* .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 */
518 /* .. .. ==> 0XF8006010[10:0] = 0x00000001U */
519 /* .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U */
520 /* .. .. reg_ddrc_w_xact_run_length = 0x8 */
521 /* .. .. ==> 0XF8006010[14:11] = 0x00000008U */
522 /* .. .. ==> MASK : 0x00007800U VAL : 0x00004000U */
523 /* .. .. reg_ddrc_w_max_starve_x32 = 0x2 */
524 /* .. .. ==> 0XF8006010[25:15] = 0x00000002U */
525 /* .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U */
526 /* .. .. */
527 EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U),
528 /* .. .. reg_ddrc_t_rc = 0x1a */
529 /* .. .. ==> 0XF8006014[5:0] = 0x0000001AU */
530 /* .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU */
531 /* .. .. reg_ddrc_t_rfc_min = 0x54 */
532 /* .. .. ==> 0XF8006014[13:6] = 0x00000054U */
533 /* .. .. ==> MASK : 0x00003FC0U VAL : 0x00001500U */
534 /* .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 */
535 /* .. .. ==> 0XF8006014[20:14] = 0x00000010U */
536 /* .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U */
537 /* .. .. */
538 EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x0004151AU),
539 /* .. .. reg_ddrc_wr2pre = 0x12 */
540 /* .. .. ==> 0XF8006018[4:0] = 0x00000012U */
541 /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U */
542 /* .. .. reg_ddrc_powerdown_to_x32 = 0x6 */
543 /* .. .. ==> 0XF8006018[9:5] = 0x00000006U */
544 /* .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U */
545 /* .. .. reg_ddrc_t_faw = 0x15 */
546 /* .. .. ==> 0XF8006018[15:10] = 0x00000015U */
547 /* .. .. ==> MASK : 0x0000FC00U VAL : 0x00005400U */
548 /* .. .. reg_ddrc_t_ras_max = 0x23 */
549 /* .. .. ==> 0XF8006018[21:16] = 0x00000023U */
550 /* .. .. ==> MASK : 0x003F0000U VAL : 0x00230000U */
551 /* .. .. reg_ddrc_t_ras_min = 0x13 */
552 /* .. .. ==> 0XF8006018[26:22] = 0x00000013U */
553 /* .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U */
554 /* .. .. reg_ddrc_t_cke = 0x4 */
555 /* .. .. ==> 0XF8006018[31:28] = 0x00000004U */
556 /* .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U */
557 /* .. .. */
558 EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x44E354D2U),
559 /* .. .. reg_ddrc_write_latency = 0x5 */
560 /* .. .. ==> 0XF800601C[4:0] = 0x00000005U */
561 /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U */
562 /* .. .. reg_ddrc_rd2wr = 0x7 */
563 /* .. .. ==> 0XF800601C[9:5] = 0x00000007U */
564 /* .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U */
565 /* .. .. reg_ddrc_wr2rd = 0xe */
566 /* .. .. ==> 0XF800601C[14:10] = 0x0000000EU */
567 /* .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U */
568 /* .. .. reg_ddrc_t_xp = 0x4 */
569 /* .. .. ==> 0XF800601C[19:15] = 0x00000004U */
570 /* .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U */
571 /* .. .. reg_ddrc_pad_pd = 0x0 */
572 /* .. .. ==> 0XF800601C[22:20] = 0x00000000U */
573 /* .. .. ==> MASK : 0x00700000U VAL : 0x00000000U */
574 /* .. .. reg_ddrc_rd2pre = 0x4 */
575 /* .. .. ==> 0XF800601C[27:23] = 0x00000004U */
576 /* .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U */
577 /* .. .. reg_ddrc_t_rcd = 0x7 */
578 /* .. .. ==> 0XF800601C[31:28] = 0x00000007U */
579 /* .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U */
580 /* .. .. */
581 EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0x720238E5U),
582 /* .. .. reg_ddrc_t_ccd = 0x4 */
583 /* .. .. ==> 0XF8006020[4:2] = 0x00000004U */
584 /* .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U */
585 /* .. .. reg_ddrc_t_rrd = 0x6 */
586 /* .. .. ==> 0XF8006020[7:5] = 0x00000006U */
587 /* .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U */
588 /* .. .. reg_ddrc_refresh_margin = 0x2 */
589 /* .. .. ==> 0XF8006020[11:8] = 0x00000002U */
590 /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */
591 /* .. .. reg_ddrc_t_rp = 0x7 */
592 /* .. .. ==> 0XF8006020[15:12] = 0x00000007U */
593 /* .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U */
594 /* .. .. reg_ddrc_refresh_to_x32 = 0x8 */
595 /* .. .. ==> 0XF8006020[20:16] = 0x00000008U */
596 /* .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U */
597 /* .. .. reg_ddrc_mobile = 0x0 */
598 /* .. .. ==> 0XF8006020[22:22] = 0x00000000U */
599 /* .. .. ==> MASK : 0x00400000U VAL : 0x00000000U */
600 /* .. .. reg_ddrc_en_dfi_dram_clk_disable = 0x0 */
601 /* .. .. ==> 0XF8006020[23:23] = 0x00000000U */
602 /* .. .. ==> MASK : 0x00800000U VAL : 0x00000000U */
603 /* .. .. reg_ddrc_read_latency = 0x7 */
604 /* .. .. ==> 0XF8006020[28:24] = 0x00000007U */
605 /* .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U */
606 /* .. .. reg_phy_mode_ddr1_ddr2 = 0x1 */
607 /* .. .. ==> 0XF8006020[29:29] = 0x00000001U */
608 /* .. .. ==> MASK : 0x20000000U VAL : 0x20000000U */
609 /* .. .. reg_ddrc_dis_pad_pd = 0x0 */
610 /* .. .. ==> 0XF8006020[30:30] = 0x00000000U */
611 /* .. .. ==> MASK : 0x40000000U VAL : 0x00000000U */
612 /* .. .. */
613 EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU, 0x270872D0U),
614 /* .. .. reg_ddrc_en_2t_timing_mode = 0x0 */
615 /* .. .. ==> 0XF8006024[0:0] = 0x00000000U */
616 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
617 /* .. .. reg_ddrc_prefer_write = 0x0 */
618 /* .. .. ==> 0XF8006024[1:1] = 0x00000000U */
619 /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
620 /* .. .. reg_ddrc_mr_wr = 0x0 */
621 /* .. .. ==> 0XF8006024[6:6] = 0x00000000U */
622 /* .. .. ==> MASK : 0x00000040U VAL : 0x00000000U */
623 /* .. .. reg_ddrc_mr_addr = 0x0 */
624 /* .. .. ==> 0XF8006024[8:7] = 0x00000000U */
625 /* .. .. ==> MASK : 0x00000180U VAL : 0x00000000U */
626 /* .. .. reg_ddrc_mr_data = 0x0 */
627 /* .. .. ==> 0XF8006024[24:9] = 0x00000000U */
628 /* .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U */
629 /* .. .. ddrc_reg_mr_wr_busy = 0x0 */
630 /* .. .. ==> 0XF8006024[25:25] = 0x00000000U */
631 /* .. .. ==> MASK : 0x02000000U VAL : 0x00000000U */
632 /* .. .. reg_ddrc_mr_type = 0x0 */
633 /* .. .. ==> 0XF8006024[26:26] = 0x00000000U */
634 /* .. .. ==> MASK : 0x04000000U VAL : 0x00000000U */
635 /* .. .. reg_ddrc_mr_rdata_valid = 0x0 */
636 /* .. .. ==> 0XF8006024[27:27] = 0x00000000U */
637 /* .. .. ==> MASK : 0x08000000U VAL : 0x00000000U */
638 /* .. .. */
639 EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U, 0x00000000U),
640 /* .. .. reg_ddrc_final_wait_x32 = 0x7 */
641 /* .. .. ==> 0XF8006028[6:0] = 0x00000007U */
642 /* .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U */
643 /* .. .. reg_ddrc_pre_ocd_x32 = 0x0 */
644 /* .. .. ==> 0XF8006028[10:7] = 0x00000000U */
645 /* .. .. ==> MASK : 0x00000780U VAL : 0x00000000U */
646 /* .. .. reg_ddrc_t_mrd = 0x4 */
647 /* .. .. ==> 0XF8006028[13:11] = 0x00000004U */
648 /* .. .. ==> MASK : 0x00003800U VAL : 0x00002000U */
649 /* .. .. */
650 EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U),
651 /* .. .. reg_ddrc_emr2 = 0x8 */
652 /* .. .. ==> 0XF800602C[15:0] = 0x00000008U */
653 /* .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U */
654 /* .. .. reg_ddrc_emr3 = 0x0 */
655 /* .. .. ==> 0XF800602C[31:16] = 0x00000000U */
656 /* .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U */
657 /* .. .. */
658 EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000008U),
659 /* .. .. reg_ddrc_mr = 0x930 */
660 /* .. .. ==> 0XF8006030[15:0] = 0x00000930U */
661 /* .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U */
662 /* .. .. reg_ddrc_emr = 0x4 */
663 /* .. .. ==> 0XF8006030[31:16] = 0x00000004U */
664 /* .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U */
665 /* .. .. */
666 EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040930U),
667 /* .. .. reg_ddrc_burst_rdwr = 0x4 */
668 /* .. .. ==> 0XF8006034[3:0] = 0x00000004U */
669 /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U */
Michal Simek264065f2016-03-03 13:25:03 +0100[diff] [blame]670 /* .. .. reg_ddrc_pre_cke_x1024 = 0x167 */
671 /* .. .. ==> 0XF8006034[13:4] = 0x00000167U */
672 /* .. .. ==> MASK : 0x00003FF0U VAL : 0x00001670U */
Nathan Rossi4eeed0e2015-11-24 19:34:09 +1000[diff] [blame]673 /* .. .. reg_ddrc_post_cke_x1024 = 0x1 */
674 /* .. .. ==> 0XF8006034[25:16] = 0x00000001U */
675 /* .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U */
676 /* .. .. reg_ddrc_burstchop = 0x0 */
677 /* .. .. ==> 0XF8006034[28:28] = 0x00000000U */
678 /* .. .. ==> MASK : 0x10000000U VAL : 0x00000000U */
679 /* .. .. */
Michal Simek264065f2016-03-03 13:25:03 +0100[diff] [blame]680 EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x00011674U),
Nathan Rossi4eeed0e2015-11-24 19:34:09 +1000[diff] [blame]681 /* .. .. reg_ddrc_force_low_pri_n = 0x0 */
682 /* .. .. ==> 0XF8006038[0:0] = 0x00000000U */
683 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
684 /* .. .. reg_ddrc_dis_dq = 0x0 */
685 /* .. .. ==> 0XF8006038[1:1] = 0x00000000U */
686 /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
687 /* .. .. */
688 EMIT_MASKWRITE(0XF8006038, 0x00000003U, 0x00000000U),
689 /* .. .. reg_ddrc_addrmap_bank_b0 = 0x7 */
690 /* .. .. ==> 0XF800603C[3:0] = 0x00000007U */
691 /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U */
692 /* .. .. reg_ddrc_addrmap_bank_b1 = 0x7 */
693 /* .. .. ==> 0XF800603C[7:4] = 0x00000007U */
694 /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U */
695 /* .. .. reg_ddrc_addrmap_bank_b2 = 0x7 */
696 /* .. .. ==> 0XF800603C[11:8] = 0x00000007U */
697 /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U */
698 /* .. .. reg_ddrc_addrmap_col_b5 = 0x0 */
699 /* .. .. ==> 0XF800603C[15:12] = 0x00000000U */
700 /* .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U */
701 /* .. .. reg_ddrc_addrmap_col_b6 = 0x0 */
702 /* .. .. ==> 0XF800603C[19:16] = 0x00000000U */
703 /* .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U */
704 /* .. .. */
705 EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U),
706 /* .. .. reg_ddrc_addrmap_col_b2 = 0x0 */
707 /* .. .. ==> 0XF8006040[3:0] = 0x00000000U */
708 /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U */
709 /* .. .. reg_ddrc_addrmap_col_b3 = 0x0 */
710 /* .. .. ==> 0XF8006040[7:4] = 0x00000000U */
711 /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */
712 /* .. .. reg_ddrc_addrmap_col_b4 = 0x0 */
713 /* .. .. ==> 0XF8006040[11:8] = 0x00000000U */
714 /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U */
715 /* .. .. reg_ddrc_addrmap_col_b7 = 0x0 */
716 /* .. .. ==> 0XF8006040[15:12] = 0x00000000U */
717 /* .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U */
718 /* .. .. reg_ddrc_addrmap_col_b8 = 0x0 */
719 /* .. .. ==> 0XF8006040[19:16] = 0x00000000U */
720 /* .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U */
721 /* .. .. reg_ddrc_addrmap_col_b9 = 0xf */
722 /* .. .. ==> 0XF8006040[23:20] = 0x0000000FU */
723 /* .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U */
724 /* .. .. reg_ddrc_addrmap_col_b10 = 0xf */
725 /* .. .. ==> 0XF8006040[27:24] = 0x0000000FU */
726 /* .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U */
727 /* .. .. reg_ddrc_addrmap_col_b11 = 0xf */
728 /* .. .. ==> 0XF8006040[31:28] = 0x0000000FU */
729 /* .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U */
730 /* .. .. */
731 EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U),
732 /* .. .. reg_ddrc_addrmap_row_b0 = 0x6 */
733 /* .. .. ==> 0XF8006044[3:0] = 0x00000006U */
734 /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U */
735 /* .. .. reg_ddrc_addrmap_row_b1 = 0x6 */
736 /* .. .. ==> 0XF8006044[7:4] = 0x00000006U */
737 /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U */
738 /* .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 */
739 /* .. .. ==> 0XF8006044[11:8] = 0x00000006U */
740 /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U */
741 /* .. .. reg_ddrc_addrmap_row_b12 = 0x6 */
742 /* .. .. ==> 0XF8006044[15:12] = 0x00000006U */
743 /* .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U */
744 /* .. .. reg_ddrc_addrmap_row_b13 = 0x6 */
745 /* .. .. ==> 0XF8006044[19:16] = 0x00000006U */
746 /* .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U */
747 /* .. .. reg_ddrc_addrmap_row_b14 = 0xf */
748 /* .. .. ==> 0XF8006044[23:20] = 0x0000000FU */
749 /* .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U */
750 /* .. .. reg_ddrc_addrmap_row_b15 = 0xf */
751 /* .. .. ==> 0XF8006044[27:24] = 0x0000000FU */
752 /* .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U */
753 /* .. .. */
754 EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0FF66666U),
755 /* .. .. reg_phy_rd_local_odt = 0x0 */
756 /* .. .. ==> 0XF8006048[13:12] = 0x00000000U */
757 /* .. .. ==> MASK : 0x00003000U VAL : 0x00000000U */
758 /* .. .. reg_phy_wr_local_odt = 0x3 */
759 /* .. .. ==> 0XF8006048[15:14] = 0x00000003U */
760 /* .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U */
761 /* .. .. reg_phy_idle_local_odt = 0x3 */
762 /* .. .. ==> 0XF8006048[17:16] = 0x00000003U */
763 /* .. .. ==> MASK : 0x00030000U VAL : 0x00030000U */
764 /* .. .. reserved_reg_ddrc_rank0_wr_odt = 0x1 */
765 /* .. .. ==> 0XF8006048[5:3] = 0x00000001U */
766 /* .. .. ==> MASK : 0x00000038U VAL : 0x00000008U */
767 /* .. .. reserved_reg_ddrc_rank0_rd_odt = 0x0 */
768 /* .. .. ==> 0XF8006048[2:0] = 0x00000000U */
769 /* .. .. ==> MASK : 0x00000007U VAL : 0x00000000U */
770 /* .. .. */
771 EMIT_MASKWRITE(0XF8006048, 0x0003F03FU, 0x0003C008U),
772 /* .. .. reg_phy_rd_cmd_to_data = 0x0 */
773 /* .. .. ==> 0XF8006050[3:0] = 0x00000000U */
774 /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U */
775 /* .. .. reg_phy_wr_cmd_to_data = 0x0 */
776 /* .. .. ==> 0XF8006050[7:4] = 0x00000000U */
777 /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */
778 /* .. .. reg_phy_rdc_we_to_re_delay = 0x8 */
779 /* .. .. ==> 0XF8006050[11:8] = 0x00000008U */
780 /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U */
781 /* .. .. reg_phy_rdc_fifo_rst_disable = 0x0 */
782 /* .. .. ==> 0XF8006050[15:15] = 0x00000000U */
783 /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */
784 /* .. .. reg_phy_use_fixed_re = 0x1 */
785 /* .. .. ==> 0XF8006050[16:16] = 0x00000001U */
786 /* .. .. ==> MASK : 0x00010000U VAL : 0x00010000U */
787 /* .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 */
788 /* .. .. ==> 0XF8006050[17:17] = 0x00000000U */
789 /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
790 /* .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 */
791 /* .. .. ==> 0XF8006050[18:18] = 0x00000000U */
792 /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
793 /* .. .. reg_phy_clk_stall_level = 0x0 */
794 /* .. .. ==> 0XF8006050[19:19] = 0x00000000U */
795 /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */
796 /* .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 */
797 /* .. .. ==> 0XF8006050[27:24] = 0x00000007U */
798 /* .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U */
799 /* .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 */
800 /* .. .. ==> 0XF8006050[31:28] = 0x00000007U */
801 /* .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U */
802 /* .. .. */
803 EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U),
804 /* .. .. reg_ddrc_dis_dll_calib = 0x0 */
805 /* .. .. ==> 0XF8006058[16:16] = 0x00000000U */
806 /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
807 /* .. .. */
808 EMIT_MASKWRITE(0XF8006058, 0x00010000U, 0x00000000U),
809 /* .. .. reg_ddrc_rd_odt_delay = 0x3 */
810 /* .. .. ==> 0XF800605C[3:0] = 0x00000003U */
811 /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U */
812 /* .. .. reg_ddrc_wr_odt_delay = 0x0 */
813 /* .. .. ==> 0XF800605C[7:4] = 0x00000000U */
814 /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */
815 /* .. .. reg_ddrc_rd_odt_hold = 0x0 */
816 /* .. .. ==> 0XF800605C[11:8] = 0x00000000U */
817 /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U */
818 /* .. .. reg_ddrc_wr_odt_hold = 0x5 */
819 /* .. .. ==> 0XF800605C[15:12] = 0x00000005U */
820 /* .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U */
821 /* .. .. */
822 EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U),
823 /* .. .. reg_ddrc_pageclose = 0x0 */
824 /* .. .. ==> 0XF8006060[0:0] = 0x00000000U */
825 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
826 /* .. .. reg_ddrc_lpr_num_entries = 0x1f */
827 /* .. .. ==> 0XF8006060[6:1] = 0x0000001FU */
828 /* .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU */
829 /* .. .. reg_ddrc_auto_pre_en = 0x0 */
830 /* .. .. ==> 0XF8006060[7:7] = 0x00000000U */
831 /* .. .. ==> MASK : 0x00000080U VAL : 0x00000000U */
832 /* .. .. reg_ddrc_refresh_update_level = 0x0 */
833 /* .. .. ==> 0XF8006060[8:8] = 0x00000000U */
834 /* .. .. ==> MASK : 0x00000100U VAL : 0x00000000U */
835 /* .. .. reg_ddrc_dis_wc = 0x0 */
836 /* .. .. ==> 0XF8006060[9:9] = 0x00000000U */
837 /* .. .. ==> MASK : 0x00000200U VAL : 0x00000000U */
838 /* .. .. reg_ddrc_dis_collision_page_opt = 0x0 */
839 /* .. .. ==> 0XF8006060[10:10] = 0x00000000U */
840 /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
841 /* .. .. reg_ddrc_selfref_en = 0x0 */
842 /* .. .. ==> 0XF8006060[12:12] = 0x00000000U */
843 /* .. .. ==> MASK : 0x00001000U VAL : 0x00000000U */
844 /* .. .. */
845 EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU),
846 /* .. .. reg_ddrc_go2critical_hysteresis = 0x0 */
847 /* .. .. ==> 0XF8006064[12:5] = 0x00000000U */
848 /* .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U */
849 /* .. .. reg_arb_go2critical_en = 0x1 */
850 /* .. .. ==> 0XF8006064[17:17] = 0x00000001U */
851 /* .. .. ==> MASK : 0x00020000U VAL : 0x00020000U */
852 /* .. .. */
853 EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U),
854 /* .. .. reg_ddrc_wrlvl_ww = 0x41 */
855 /* .. .. ==> 0XF8006068[7:0] = 0x00000041U */
856 /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U */
857 /* .. .. reg_ddrc_rdlvl_rr = 0x41 */
858 /* .. .. ==> 0XF8006068[15:8] = 0x00000041U */
859 /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U */
860 /* .. .. reg_ddrc_dfi_t_wlmrd = 0x28 */
861 /* .. .. ==> 0XF8006068[25:16] = 0x00000028U */
862 /* .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U */
863 /* .. .. */
864 EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284141U),
865 /* .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 */
866 /* .. .. ==> 0XF800606C[7:0] = 0x00000010U */
867 /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U */
868 /* .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 */
869 /* .. .. ==> 0XF800606C[15:8] = 0x00000016U */
870 /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U */
871 /* .. .. */
872 EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U),
873 /* .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1 */
874 /* .. .. ==> 0XF8006078[3:0] = 0x00000001U */
875 /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U */
876 /* .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1 */
877 /* .. .. ==> 0XF8006078[7:4] = 0x00000001U */
878 /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U */
879 /* .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 */
880 /* .. .. ==> 0XF8006078[11:8] = 0x00000001U */
881 /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U */
882 /* .. .. reg_ddrc_t_cksre = 0x6 */
883 /* .. .. ==> 0XF8006078[15:12] = 0x00000006U */
884 /* .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U */
885 /* .. .. reg_ddrc_t_cksrx = 0x6 */
886 /* .. .. ==> 0XF8006078[19:16] = 0x00000006U */
887 /* .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U */
888 /* .. .. reg_ddrc_t_ckesr = 0x4 */
889 /* .. .. ==> 0XF8006078[25:20] = 0x00000004U */
890 /* .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U */
891 /* .. .. */
892 EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU, 0x00466111U),
893 /* .. .. reg_ddrc_t_ckpde = 0x2 */
894 /* .. .. ==> 0XF800607C[3:0] = 0x00000002U */
895 /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U */
896 /* .. .. reg_ddrc_t_ckpdx = 0x2 */
897 /* .. .. ==> 0XF800607C[7:4] = 0x00000002U */
898 /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U */
899 /* .. .. reg_ddrc_t_ckdpde = 0x2 */
900 /* .. .. ==> 0XF800607C[11:8] = 0x00000002U */
901 /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */
902 /* .. .. reg_ddrc_t_ckdpdx = 0x2 */
903 /* .. .. ==> 0XF800607C[15:12] = 0x00000002U */
904 /* .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U */
905 /* .. .. reg_ddrc_t_ckcsx = 0x3 */
906 /* .. .. ==> 0XF800607C[19:16] = 0x00000003U */
907 /* .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U */
908 /* .. .. */
909 EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU, 0x00032222U),
910 /* .. .. reg_ddrc_dis_auto_zq = 0x0 */
911 /* .. .. ==> 0XF80060A4[0:0] = 0x00000000U */
912 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
913 /* .. .. reg_ddrc_ddr3 = 0x1 */
914 /* .. .. ==> 0XF80060A4[1:1] = 0x00000001U */
915 /* .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */
916 /* .. .. reg_ddrc_t_mod = 0x200 */
917 /* .. .. ==> 0XF80060A4[11:2] = 0x00000200U */
918 /* .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U */
919 /* .. .. reg_ddrc_t_zq_long_nop = 0x200 */
920 /* .. .. ==> 0XF80060A4[21:12] = 0x00000200U */
921 /* .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U */
922 /* .. .. reg_ddrc_t_zq_short_nop = 0x40 */
923 /* .. .. ==> 0XF80060A4[31:22] = 0x00000040U */
924 /* .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U */
925 /* .. .. */
926 EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U),
927 /* .. .. t_zq_short_interval_x1024 = 0xc845 */
928 /* .. .. ==> 0XF80060A8[19:0] = 0x0000C845U */
929 /* .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000C845U */
930 /* .. .. dram_rstn_x1024 = 0x67 */
931 /* .. .. ==> 0XF80060A8[27:20] = 0x00000067U */
932 /* .. .. ==> MASK : 0x0FF00000U VAL : 0x06700000U */
933 /* .. .. */
934 EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0670C845U),
935 /* .. .. deeppowerdown_en = 0x0 */
936 /* .. .. ==> 0XF80060AC[0:0] = 0x00000000U */
937 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
938 /* .. .. deeppowerdown_to_x1024 = 0xff */
939 /* .. .. ==> 0XF80060AC[8:1] = 0x000000FFU */
940 /* .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU */
941 /* .. .. */
942 EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU),
943 /* .. .. dfi_wrlvl_max_x1024 = 0xfff */
944 /* .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU */
945 /* .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU */
946 /* .. .. dfi_rdlvl_max_x1024 = 0xfff */
947 /* .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU */
948 /* .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U */
949 /* .. .. ddrc_reg_twrlvl_max_error = 0x0 */
950 /* .. .. ==> 0XF80060B0[24:24] = 0x00000000U */
951 /* .. .. ==> MASK : 0x01000000U VAL : 0x00000000U */
952 /* .. .. ddrc_reg_trdlvl_max_error = 0x0 */
953 /* .. .. ==> 0XF80060B0[25:25] = 0x00000000U */
954 /* .. .. ==> MASK : 0x02000000U VAL : 0x00000000U */
955 /* .. .. reg_ddrc_dfi_wr_level_en = 0x1 */
956 /* .. .. ==> 0XF80060B0[26:26] = 0x00000001U */
957 /* .. .. ==> MASK : 0x04000000U VAL : 0x04000000U */
958 /* .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 */
959 /* .. .. ==> 0XF80060B0[27:27] = 0x00000001U */
960 /* .. .. ==> MASK : 0x08000000U VAL : 0x08000000U */
961 /* .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 */
962 /* .. .. ==> 0XF80060B0[28:28] = 0x00000001U */
963 /* .. .. ==> MASK : 0x10000000U VAL : 0x10000000U */
964 /* .. .. */
965 EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
966 /* .. .. reg_ddrc_skip_ocd = 0x1 */
967 /* .. .. ==> 0XF80060B4[9:9] = 0x00000001U */
968 /* .. .. ==> MASK : 0x00000200U VAL : 0x00000200U */
969 /* .. .. */
970 EMIT_MASKWRITE(0XF80060B4, 0x00000200U, 0x00000200U),
971 /* .. .. reg_ddrc_dfi_t_rddata_en = 0x6 */
972 /* .. .. ==> 0XF80060B8[4:0] = 0x00000006U */
973 /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U */
974 /* .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 */
975 /* .. .. ==> 0XF80060B8[14:5] = 0x00000003U */
976 /* .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U */
977 /* .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 */
978 /* .. .. ==> 0XF80060B8[24:15] = 0x00000040U */
979 /* .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U */
980 /* .. .. */
981 EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x00200066U),
982 /* .. .. START: RESET ECC ERROR */
983 /* .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 */
984 /* .. .. ==> 0XF80060C4[0:0] = 0x00000001U */
985 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
986 /* .. .. Clear_Correctable_DRAM_ECC_error = 1 */
987 /* .. .. ==> 0XF80060C4[1:1] = 0x00000001U */
988 /* .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */
989 /* .. .. */
990 EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000003U),
991 /* .. .. FINISH: RESET ECC ERROR */
992 /* .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 */
993 /* .. .. ==> 0XF80060C4[0:0] = 0x00000000U */
994 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
995 /* .. .. Clear_Correctable_DRAM_ECC_error = 0x0 */
996 /* .. .. ==> 0XF80060C4[1:1] = 0x00000000U */
997 /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
998 /* .. .. */
999 EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U),
1000 /* .. .. CORR_ECC_LOG_VALID = 0x0 */
1001 /* .. .. ==> 0XF80060C8[0:0] = 0x00000000U */
1002 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
1003 /* .. .. ECC_CORRECTED_BIT_NUM = 0x0 */
1004 /* .. .. ==> 0XF80060C8[7:1] = 0x00000000U */
1005 /* .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U */
1006 /* .. .. */
1007 EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U),
1008 /* .. .. UNCORR_ECC_LOG_VALID = 0x0 */
1009 /* .. .. ==> 0XF80060DC[0:0] = 0x00000000U */
1010 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
1011 /* .. .. */
1012 EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U),
1013 /* .. .. STAT_NUM_CORR_ERR = 0x0 */
1014 /* .. .. ==> 0XF80060F0[15:8] = 0x00000000U */
1015 /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U */
1016 /* .. .. STAT_NUM_UNCORR_ERR = 0x0 */
1017 /* .. .. ==> 0XF80060F0[7:0] = 0x00000000U */
1018 /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U */
1019 /* .. .. */
1020 EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U),
1021 /* .. .. reg_ddrc_ecc_mode = 0x0 */
1022 /* .. .. ==> 0XF80060F4[2:0] = 0x00000000U */
1023 /* .. .. ==> MASK : 0x00000007U VAL : 0x00000000U */
1024 /* .. .. reg_ddrc_dis_scrub = 0x1 */
1025 /* .. .. ==> 0XF80060F4[3:3] = 0x00000001U */
1026 /* .. .. ==> MASK : 0x00000008U VAL : 0x00000008U */
1027 /* .. .. */
1028 EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U),
1029 /* .. .. reg_phy_dif_on = 0x0 */
1030 /* .. .. ==> 0XF8006114[3:0] = 0x00000000U */
1031 /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U */
1032 /* .. .. reg_phy_dif_off = 0x0 */
1033 /* .. .. ==> 0XF8006114[7:4] = 0x00000000U */
1034 /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */
1035 /* .. .. */
1036 EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U),
1037 /* .. .. reg_phy_data_slice_in_use = 0x1 */
1038 /* .. .. ==> 0XF8006118[0:0] = 0x00000001U */
1039 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
1040 /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
1041 /* .. .. ==> 0XF8006118[1:1] = 0x00000000U */
1042 /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
1043 /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
1044 /* .. .. ==> 0XF8006118[2:2] = 0x00000000U */
1045 /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
1046 /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
1047 /* .. .. ==> 0XF8006118[3:3] = 0x00000000U */
1048 /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
1049 /* .. .. reg_phy_bist_shift_dq = 0x0 */
1050 /* .. .. ==> 0XF8006118[14:6] = 0x00000000U */
1051 /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */
1052 /* .. .. reg_phy_bist_err_clr = 0x0 */
1053 /* .. .. ==> 0XF8006118[23:15] = 0x00000000U */
1054 /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */
1055 /* .. .. reg_phy_dq_offset = 0x40 */
1056 /* .. .. ==> 0XF8006118[30:24] = 0x00000040U */
1057 /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */
1058 /* .. .. */
1059 EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU, 0x40000001U),
1060 /* .. .. reg_phy_data_slice_in_use = 0x1 */
1061 /* .. .. ==> 0XF800611C[0:0] = 0x00000001U */
1062 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
1063 /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
1064 /* .. .. ==> 0XF800611C[1:1] = 0x00000000U */
1065 /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
1066 /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
1067 /* .. .. ==> 0XF800611C[2:2] = 0x00000000U */
1068 /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
1069 /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
1070 /* .. .. ==> 0XF800611C[3:3] = 0x00000000U */
1071 /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
1072 /* .. .. reg_phy_bist_shift_dq = 0x0 */
1073 /* .. .. ==> 0XF800611C[14:6] = 0x00000000U */
1074 /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */
1075 /* .. .. reg_phy_bist_err_clr = 0x0 */
1076 /* .. .. ==> 0XF800611C[23:15] = 0x00000000U */
1077 /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */
1078 /* .. .. reg_phy_dq_offset = 0x40 */
1079 /* .. .. ==> 0XF800611C[30:24] = 0x00000040U */
1080 /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */
1081 /* .. .. */
1082 EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU, 0x40000001U),
1083 /* .. .. reg_phy_data_slice_in_use = 0x1 */
1084 /* .. .. ==> 0XF8006120[0:0] = 0x00000001U */
1085 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
1086 /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
1087 /* .. .. ==> 0XF8006120[1:1] = 0x00000000U */
1088 /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
1089 /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
1090 /* .. .. ==> 0XF8006120[2:2] = 0x00000000U */
1091 /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
1092 /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
1093 /* .. .. ==> 0XF8006120[3:3] = 0x00000000U */
1094 /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
1095 /* .. .. reg_phy_bist_shift_dq = 0x0 */
1096 /* .. .. ==> 0XF8006120[14:6] = 0x00000000U */
1097 /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */
1098 /* .. .. reg_phy_bist_err_clr = 0x0 */
1099 /* .. .. ==> 0XF8006120[23:15] = 0x00000000U */
1100 /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */
1101 /* .. .. reg_phy_dq_offset = 0x40 */
1102 /* .. .. ==> 0XF8006120[30:24] = 0x00000040U */
1103 /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */
1104 /* .. .. */
1105 EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU, 0x40000001U),
1106 /* .. .. reg_phy_data_slice_in_use = 0x1 */
1107 /* .. .. ==> 0XF8006124[0:0] = 0x00000001U */
1108 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
1109 /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
1110 /* .. .. ==> 0XF8006124[1:1] = 0x00000000U */
1111 /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
1112 /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
1113 /* .. .. ==> 0XF8006124[2:2] = 0x00000000U */
1114 /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
1115 /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
1116 /* .. .. ==> 0XF8006124[3:3] = 0x00000000U */
1117 /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
1118 /* .. .. reg_phy_bist_shift_dq = 0x0 */
1119 /* .. .. ==> 0XF8006124[14:6] = 0x00000000U */
1120 /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */
1121 /* .. .. reg_phy_bist_err_clr = 0x0 */
1122 /* .. .. ==> 0XF8006124[23:15] = 0x00000000U */
1123 /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */
1124 /* .. .. reg_phy_dq_offset = 0x40 */
1125 /* .. .. ==> 0XF8006124[30:24] = 0x00000040U */
1126 /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */
1127 /* .. .. */
1128 EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU, 0x40000001U),
1129 /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
1130 /* .. .. ==> 0XF800612C[9:0] = 0x00000000U */
1131 /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */
1132 /* .. .. reg_phy_gatelvl_init_ratio = 0x8f */
1133 /* .. .. ==> 0XF800612C[19:10] = 0x0000008FU */
1134 /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00023C00U */
1135 /* .. .. */
1136 EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x00023C00U),
1137 /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
1138 /* .. .. ==> 0XF8006130[9:0] = 0x00000000U */
1139 /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */
1140 /* .. .. reg_phy_gatelvl_init_ratio = 0x8a */
1141 /* .. .. ==> 0XF8006130[19:10] = 0x0000008AU */
1142 /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00022800U */
1143 /* .. .. */
1144 EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x00022800U),
1145 /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
1146 /* .. .. ==> 0XF8006134[9:0] = 0x00000000U */
1147 /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */
1148 /* .. .. reg_phy_gatelvl_init_ratio = 0x8b */
1149 /* .. .. ==> 0XF8006134[19:10] = 0x0000008BU */
1150 /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00022C00U */
1151 /* .. .. */
1152 EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x00022C00U),
1153 /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
1154 /* .. .. ==> 0XF8006138[9:0] = 0x00000000U */
1155 /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */
1156 /* .. .. reg_phy_gatelvl_init_ratio = 0x92 */
1157 /* .. .. ==> 0XF8006138[19:10] = 0x00000092U */
1158 /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00024800U */
1159 /* .. .. */
1160 EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x00024800U),
1161 /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
1162 /* .. .. ==> 0XF8006140[9:0] = 0x00000035U */
1163 /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */
1164 /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
1165 /* .. .. ==> 0XF8006140[10:10] = 0x00000000U */
1166 /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
1167 /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
1168 /* .. .. ==> 0XF8006140[19:11] = 0x00000000U */
1169 /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
1170 /* .. .. */
1171 EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U),
1172 /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
1173 /* .. .. ==> 0XF8006144[9:0] = 0x00000035U */
1174 /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */
1175 /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
1176 /* .. .. ==> 0XF8006144[10:10] = 0x00000000U */
1177 /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
1178 /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
1179 /* .. .. ==> 0XF8006144[19:11] = 0x00000000U */
1180 /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
1181 /* .. .. */
1182 EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U),
1183 /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
1184 /* .. .. ==> 0XF8006148[9:0] = 0x00000035U */
1185 /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */
1186 /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
1187 /* .. .. ==> 0XF8006148[10:10] = 0x00000000U */
1188 /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
1189 /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
1190 /* .. .. ==> 0XF8006148[19:11] = 0x00000000U */
1191 /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
1192 /* .. .. */
1193 EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U),
1194 /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
1195 /* .. .. ==> 0XF800614C[9:0] = 0x00000035U */
1196 /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */
1197 /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
1198 /* .. .. ==> 0XF800614C[10:10] = 0x00000000U */
1199 /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
1200 /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
1201 /* .. .. ==> 0XF800614C[19:11] = 0x00000000U */
1202 /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
1203 /* .. .. */
1204 EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U),
1205 /* .. .. reg_phy_wr_dqs_slave_ratio = 0x77 */
1206 /* .. .. ==> 0XF8006154[9:0] = 0x00000077U */
1207 /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000077U */
1208 /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
1209 /* .. .. ==> 0XF8006154[10:10] = 0x00000000U */
1210 /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
1211 /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
1212 /* .. .. ==> 0XF8006154[19:11] = 0x00000000U */
1213 /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
1214 /* .. .. */
1215 EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x00000077U),
1216 /* .. .. reg_phy_wr_dqs_slave_ratio = 0x7c */
1217 /* .. .. ==> 0XF8006158[9:0] = 0x0000007CU */
1218 /* .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU */
1219 /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
1220 /* .. .. ==> 0XF8006158[10:10] = 0x00000000U */
1221 /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
1222 /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
1223 /* .. .. ==> 0XF8006158[19:11] = 0x00000000U */
1224 /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
1225 /* .. .. */
1226 EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x0000007CU),
1227 /* .. .. reg_phy_wr_dqs_slave_ratio = 0x7c */
1228 /* .. .. ==> 0XF800615C[9:0] = 0x0000007CU */
1229 /* .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU */
1230 /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
1231 /* .. .. ==> 0XF800615C[10:10] = 0x00000000U */
1232 /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
1233 /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
1234 /* .. .. ==> 0XF800615C[19:11] = 0x00000000U */
1235 /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
1236 /* .. .. */
1237 EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x0000007CU),
1238 /* .. .. reg_phy_wr_dqs_slave_ratio = 0x75 */
1239 /* .. .. ==> 0XF8006160[9:0] = 0x00000075U */
1240 /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000075U */
1241 /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
1242 /* .. .. ==> 0XF8006160[10:10] = 0x00000000U */
1243 /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
1244 /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
1245 /* .. .. ==> 0XF8006160[19:11] = 0x00000000U */
1246 /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
1247 /* .. .. */
1248 EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x00000075U),
1249 /* .. .. reg_phy_fifo_we_slave_ratio = 0xe4 */
1250 /* .. .. ==> 0XF8006168[10:0] = 0x000000E4U */
1251 /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000E4U */
1252 /* .. .. reg_phy_fifo_we_in_force = 0x0 */
1253 /* .. .. ==> 0XF8006168[11:11] = 0x00000000U */
1254 /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */
1255 /* .. .. reg_phy_fifo_we_in_delay = 0x0 */
1256 /* .. .. ==> 0XF8006168[20:12] = 0x00000000U */
1257 /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */
1258 /* .. .. */
1259 EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000E4U),
1260 /* .. .. reg_phy_fifo_we_slave_ratio = 0xdf */
1261 /* .. .. ==> 0XF800616C[10:0] = 0x000000DFU */
1262 /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000DFU */
1263 /* .. .. reg_phy_fifo_we_in_force = 0x0 */
1264 /* .. .. ==> 0XF800616C[11:11] = 0x00000000U */
1265 /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */
1266 /* .. .. reg_phy_fifo_we_in_delay = 0x0 */
1267 /* .. .. ==> 0XF800616C[20:12] = 0x00000000U */
1268 /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */
1269 /* .. .. */
1270 EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000DFU),
1271 /* .. .. reg_phy_fifo_we_slave_ratio = 0xe0 */
1272 /* .. .. ==> 0XF8006170[10:0] = 0x000000E0U */
1273 /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000E0U */
1274 /* .. .. reg_phy_fifo_we_in_force = 0x0 */
1275 /* .. .. ==> 0XF8006170[11:11] = 0x00000000U */
1276 /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */
1277 /* .. .. reg_phy_fifo_we_in_delay = 0x0 */
1278 /* .. .. ==> 0XF8006170[20:12] = 0x00000000U */
1279 /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */
1280 /* .. .. */
1281 EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000E0U),
1282 /* .. .. reg_phy_fifo_we_slave_ratio = 0xe7 */
1283 /* .. .. ==> 0XF8006174[10:0] = 0x000000E7U */
1284 /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000E7U */
1285 /* .. .. reg_phy_fifo_we_in_force = 0x0 */
1286 /* .. .. ==> 0XF8006174[11:11] = 0x00000000U */
1287 /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */
1288 /* .. .. reg_phy_fifo_we_in_delay = 0x0 */
1289 /* .. .. ==> 0XF8006174[20:12] = 0x00000000U */
1290 /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */
1291 /* .. .. */
1292 EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000E7U),
1293 /* .. .. reg_phy_wr_data_slave_ratio = 0xb7 */
1294 /* .. .. ==> 0XF800617C[9:0] = 0x000000B7U */
1295 /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000B7U */
1296 /* .. .. reg_phy_wr_data_slave_force = 0x0 */
1297 /* .. .. ==> 0XF800617C[10:10] = 0x00000000U */
1298 /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
1299 /* .. .. reg_phy_wr_data_slave_delay = 0x0 */
1300 /* .. .. ==> 0XF800617C[19:11] = 0x00000000U */
1301 /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
1302 /* .. .. */
1303 EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000B7U),
1304 /* .. .. reg_phy_wr_data_slave_ratio = 0xbc */
1305 /* .. .. ==> 0XF8006180[9:0] = 0x000000BCU */
1306 /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU */
1307 /* .. .. reg_phy_wr_data_slave_force = 0x0 */
1308 /* .. .. ==> 0XF8006180[10:10] = 0x00000000U */
1309 /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
1310 /* .. .. reg_phy_wr_data_slave_delay = 0x0 */
1311 /* .. .. ==> 0XF8006180[19:11] = 0x00000000U */
1312 /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
1313 /* .. .. */
1314 EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000BCU),
1315 /* .. .. reg_phy_wr_data_slave_ratio = 0xbc */
1316 /* .. .. ==> 0XF8006184[9:0] = 0x000000BCU */
1317 /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU */
1318 /* .. .. reg_phy_wr_data_slave_force = 0x0 */
1319 /* .. .. ==> 0XF8006184[10:10] = 0x00000000U */
1320 /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
1321 /* .. .. reg_phy_wr_data_slave_delay = 0x0 */
1322 /* .. .. ==> 0XF8006184[19:11] = 0x00000000U */
1323 /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
1324 /* .. .. */
1325 EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000BCU),
1326 /* .. .. reg_phy_wr_data_slave_ratio = 0xb5 */
1327 /* .. .. ==> 0XF8006188[9:0] = 0x000000B5U */
1328 /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000B5U */
1329 /* .. .. reg_phy_wr_data_slave_force = 0x0 */
1330 /* .. .. ==> 0XF8006188[10:10] = 0x00000000U */
1331 /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
1332 /* .. .. reg_phy_wr_data_slave_delay = 0x0 */
1333 /* .. .. ==> 0XF8006188[19:11] = 0x00000000U */
1334 /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
1335 /* .. .. */
1336 EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000B5U),
1337 /* .. .. reg_phy_bl2 = 0x0 */
1338 /* .. .. ==> 0XF8006190[1:1] = 0x00000000U */
1339 /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
1340 /* .. .. reg_phy_at_spd_atpg = 0x0 */
1341 /* .. .. ==> 0XF8006190[2:2] = 0x00000000U */
1342 /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
1343 /* .. .. reg_phy_bist_enable = 0x0 */
1344 /* .. .. ==> 0XF8006190[3:3] = 0x00000000U */
1345 /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
1346 /* .. .. reg_phy_bist_force_err = 0x0 */
1347 /* .. .. ==> 0XF8006190[4:4] = 0x00000000U */
1348 /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
1349 /* .. .. reg_phy_bist_mode = 0x0 */
1350 /* .. .. ==> 0XF8006190[6:5] = 0x00000000U */
1351 /* .. .. ==> MASK : 0x00000060U VAL : 0x00000000U */
1352 /* .. .. reg_phy_invert_clkout = 0x1 */
1353 /* .. .. ==> 0XF8006190[7:7] = 0x00000001U */
1354 /* .. .. ==> MASK : 0x00000080U VAL : 0x00000080U */
1355 /* .. .. reg_phy_sel_logic = 0x0 */
1356 /* .. .. ==> 0XF8006190[9:9] = 0x00000000U */
1357 /* .. .. ==> MASK : 0x00000200U VAL : 0x00000000U */
1358 /* .. .. reg_phy_ctrl_slave_ratio = 0x100 */
1359 /* .. .. ==> 0XF8006190[19:10] = 0x00000100U */
1360 /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U */
1361 /* .. .. reg_phy_ctrl_slave_force = 0x0 */
1362 /* .. .. ==> 0XF8006190[20:20] = 0x00000000U */
1363 /* .. .. ==> MASK : 0x00100000U VAL : 0x00000000U */
1364 /* .. .. reg_phy_ctrl_slave_delay = 0x0 */
1365 /* .. .. ==> 0XF8006190[27:21] = 0x00000000U */
1366 /* .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U */
1367 /* .. .. reg_phy_lpddr = 0x0 */
1368 /* .. .. ==> 0XF8006190[29:29] = 0x00000000U */
1369 /* .. .. ==> MASK : 0x20000000U VAL : 0x00000000U */
1370 /* .. .. reg_phy_cmd_latency = 0x0 */
1371 /* .. .. ==> 0XF8006190[30:30] = 0x00000000U */
1372 /* .. .. ==> MASK : 0x40000000U VAL : 0x00000000U */
1373 /* .. .. */
1374 EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU, 0x00040080U),
1375 /* .. .. reg_phy_wr_rl_delay = 0x2 */
1376 /* .. .. ==> 0XF8006194[4:0] = 0x00000002U */
1377 /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U */
1378 /* .. .. reg_phy_rd_rl_delay = 0x4 */
1379 /* .. .. ==> 0XF8006194[9:5] = 0x00000004U */
1380 /* .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U */
1381 /* .. .. reg_phy_dll_lock_diff = 0xf */
1382 /* .. .. ==> 0XF8006194[13:10] = 0x0000000FU */
1383 /* .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U */
1384 /* .. .. reg_phy_use_wr_level = 0x1 */
1385 /* .. .. ==> 0XF8006194[14:14] = 0x00000001U */
1386 /* .. .. ==> MASK : 0x00004000U VAL : 0x00004000U */
1387 /* .. .. reg_phy_use_rd_dqs_gate_level = 0x1 */
1388 /* .. .. ==> 0XF8006194[15:15] = 0x00000001U */
1389 /* .. .. ==> MASK : 0x00008000U VAL : 0x00008000U */
1390 /* .. .. reg_phy_use_rd_data_eye_level = 0x1 */
1391 /* .. .. ==> 0XF8006194[16:16] = 0x00000001U */
1392 /* .. .. ==> MASK : 0x00010000U VAL : 0x00010000U */
1393 /* .. .. reg_phy_dis_calib_rst = 0x0 */
1394 /* .. .. ==> 0XF8006194[17:17] = 0x00000000U */
1395 /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
1396 /* .. .. reg_phy_ctrl_slave_delay = 0x0 */
1397 /* .. .. ==> 0XF8006194[19:18] = 0x00000000U */
1398 /* .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U */
1399 /* .. .. */
1400 EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FC82U),
1401 /* .. .. reg_arb_page_addr_mask = 0x0 */
1402 /* .. .. ==> 0XF8006204[31:0] = 0x00000000U */
1403 /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */
1404 /* .. .. */
1405 EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U),
1406 /* .. .. reg_arb_pri_wr_portn = 0x3ff */
1407 /* .. .. ==> 0XF8006208[9:0] = 0x000003FFU */
1408 /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
1409 /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
1410 /* .. .. ==> 0XF8006208[16:16] = 0x00000000U */
1411 /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
1412 /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
1413 /* .. .. ==> 0XF8006208[17:17] = 0x00000000U */
1414 /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
1415 /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
1416 /* .. .. ==> 0XF8006208[18:18] = 0x00000000U */
1417 /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
1418 /* .. .. */
1419 EMIT_MASKWRITE(0XF8006208, 0x000703FFU, 0x000003FFU),
1420 /* .. .. reg_arb_pri_wr_portn = 0x3ff */
1421 /* .. .. ==> 0XF800620C[9:0] = 0x000003FFU */
1422 /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
1423 /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
1424 /* .. .. ==> 0XF800620C[16:16] = 0x00000000U */
1425 /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
1426 /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
1427 /* .. .. ==> 0XF800620C[17:17] = 0x00000000U */
1428 /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
1429 /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
1430 /* .. .. ==> 0XF800620C[18:18] = 0x00000000U */
1431 /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
1432 /* .. .. */
1433 EMIT_MASKWRITE(0XF800620C, 0x000703FFU, 0x000003FFU),
1434 /* .. .. reg_arb_pri_wr_portn = 0x3ff */
1435 /* .. .. ==> 0XF8006210[9:0] = 0x000003FFU */
1436 /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
1437 /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
1438 /* .. .. ==> 0XF8006210[16:16] = 0x00000000U */
1439 /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
1440 /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
1441 /* .. .. ==> 0XF8006210[17:17] = 0x00000000U */
1442 /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
1443 /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
1444 /* .. .. ==> 0XF8006210[18:18] = 0x00000000U */
1445 /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
1446 /* .. .. */
1447 EMIT_MASKWRITE(0XF8006210, 0x000703FFU, 0x000003FFU),
1448 /* .. .. reg_arb_pri_wr_portn = 0x3ff */
1449 /* .. .. ==> 0XF8006214[9:0] = 0x000003FFU */
1450 /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
1451 /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
1452 /* .. .. ==> 0XF8006214[16:16] = 0x00000000U */
1453 /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
1454 /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
1455 /* .. .. ==> 0XF8006214[17:17] = 0x00000000U */
1456 /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
1457 /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
1458 /* .. .. ==> 0XF8006214[18:18] = 0x00000000U */
1459 /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
1460 /* .. .. */
1461 EMIT_MASKWRITE(0XF8006214, 0x000703FFU, 0x000003FFU),
1462 /* .. .. reg_arb_pri_rd_portn = 0x3ff */
1463 /* .. .. ==> 0XF8006218[9:0] = 0x000003FFU */
1464 /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
1465 /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
1466 /* .. .. ==> 0XF8006218[16:16] = 0x00000000U */
1467 /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
1468 /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
1469 /* .. .. ==> 0XF8006218[17:17] = 0x00000000U */
1470 /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
1471 /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
1472 /* .. .. ==> 0XF8006218[18:18] = 0x00000000U */
1473 /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
1474 /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
1475 /* .. .. ==> 0XF8006218[19:19] = 0x00000000U */
1476 /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */
1477 /* .. .. */
1478 EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU),
1479 /* .. .. reg_arb_pri_rd_portn = 0x3ff */
1480 /* .. .. ==> 0XF800621C[9:0] = 0x000003FFU */
1481 /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
1482 /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
1483 /* .. .. ==> 0XF800621C[16:16] = 0x00000000U */
1484 /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
1485 /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
1486 /* .. .. ==> 0XF800621C[17:17] = 0x00000000U */
1487 /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
1488 /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
1489 /* .. .. ==> 0XF800621C[18:18] = 0x00000000U */
1490 /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
1491 /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
1492 /* .. .. ==> 0XF800621C[19:19] = 0x00000000U */
1493 /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */
1494 /* .. .. */
1495 EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU),
1496 /* .. .. reg_arb_pri_rd_portn = 0x3ff */
1497 /* .. .. ==> 0XF8006220[9:0] = 0x000003FFU */
1498 /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
1499 /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
1500 /* .. .. ==> 0XF8006220[16:16] = 0x00000000U */
1501 /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
1502 /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
1503 /* .. .. ==> 0XF8006220[17:17] = 0x00000000U */
1504 /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
1505 /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
1506 /* .. .. ==> 0XF8006220[18:18] = 0x00000000U */
1507 /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
1508 /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
1509 /* .. .. ==> 0XF8006220[19:19] = 0x00000000U */
1510 /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */
1511 /* .. .. */
1512 EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU),
1513 /* .. .. reg_arb_pri_rd_portn = 0x3ff */
1514 /* .. .. ==> 0XF8006224[9:0] = 0x000003FFU */
1515 /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
1516 /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
1517 /* .. .. ==> 0XF8006224[16:16] = 0x00000000U */
1518 /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
1519 /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
1520 /* .. .. ==> 0XF8006224[17:17] = 0x00000000U */
1521 /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
1522 /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
1523 /* .. .. ==> 0XF8006224[18:18] = 0x00000000U */
1524 /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
1525 /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
1526 /* .. .. ==> 0XF8006224[19:19] = 0x00000000U */
1527 /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */
1528 /* .. .. */
1529 EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU),
1530 /* .. .. reg_ddrc_lpddr2 = 0x0 */
1531 /* .. .. ==> 0XF80062A8[0:0] = 0x00000000U */
1532 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
1533 /* .. .. reg_ddrc_derate_enable = 0x0 */
1534 /* .. .. ==> 0XF80062A8[2:2] = 0x00000000U */
1535 /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
1536 /* .. .. reg_ddrc_mr4_margin = 0x0 */
1537 /* .. .. ==> 0XF80062A8[11:4] = 0x00000000U */
1538 /* .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U */
1539 /* .. .. */
1540 EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U, 0x00000000U),
1541 /* .. .. reg_ddrc_mr4_read_interval = 0x0 */
1542 /* .. .. ==> 0XF80062AC[31:0] = 0x00000000U */
1543 /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */
1544 /* .. .. */
1545 EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U),
1546 /* .. .. reg_ddrc_min_stable_clock_x1 = 0x5 */
1547 /* .. .. ==> 0XF80062B0[3:0] = 0x00000005U */
1548 /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U */
1549 /* .. .. reg_ddrc_idle_after_reset_x32 = 0x12 */
1550 /* .. .. ==> 0XF80062B0[11:4] = 0x00000012U */
1551 /* .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U */
1552 /* .. .. reg_ddrc_t_mrw = 0x5 */
1553 /* .. .. ==> 0XF80062B0[21:12] = 0x00000005U */
1554 /* .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U */
1555 /* .. .. */
1556 EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U),
1557 /* .. .. reg_ddrc_max_auto_init_x1024 = 0xa6 */
1558 /* .. .. ==> 0XF80062B4[7:0] = 0x000000A6U */
1559 /* .. .. ==> MASK : 0x000000FFU VAL : 0x000000A6U */
1560 /* .. .. reg_ddrc_dev_zqinit_x32 = 0x12 */
1561 /* .. .. ==> 0XF80062B4[17:8] = 0x00000012U */
1562 /* .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U */
1563 /* .. .. */
1564 EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A6U),
1565 /* .. .. START: POLL ON DCI STATUS */
1566 /* .. .. DONE = 1 */
1567 /* .. .. ==> 0XF8000B74[13:13] = 0x00000001U */
1568 /* .. .. ==> MASK : 0x00002000U VAL : 0x00002000U */
1569 /* .. .. */
1570 EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
1571 /* .. .. FINISH: POLL ON DCI STATUS */
1572 /* .. .. START: UNLOCK DDR */
1573 /* .. .. reg_ddrc_soft_rstb = 0x1 */
1574 /* .. .. ==> 0XF8006000[0:0] = 0x00000001U */
1575 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
1576 /* .. .. reg_ddrc_powerdown_en = 0x0 */
1577 /* .. .. ==> 0XF8006000[1:1] = 0x00000000U */
1578 /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
1579 /* .. .. reg_ddrc_data_bus_width = 0x0 */
1580 /* .. .. ==> 0XF8006000[3:2] = 0x00000000U */
1581 /* .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U */
1582 /* .. .. reg_ddrc_burst8_refresh = 0x0 */
1583 /* .. .. ==> 0XF8006000[6:4] = 0x00000000U */
1584 /* .. .. ==> MASK : 0x00000070U VAL : 0x00000000U */
1585 /* .. .. reg_ddrc_rdwr_idle_gap = 1 */
1586 /* .. .. ==> 0XF8006000[13:7] = 0x00000001U */
1587 /* .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U */
1588 /* .. .. reg_ddrc_dis_rd_bypass = 0x0 */
1589 /* .. .. ==> 0XF8006000[14:14] = 0x00000000U */
1590 /* .. .. ==> MASK : 0x00004000U VAL : 0x00000000U */
1591 /* .. .. reg_ddrc_dis_act_bypass = 0x0 */
1592 /* .. .. ==> 0XF8006000[15:15] = 0x00000000U */
1593 /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */
1594 /* .. .. reg_ddrc_dis_auto_refresh = 0x0 */
1595 /* .. .. ==> 0XF8006000[16:16] = 0x00000000U */
1596 /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
1597 /* .. .. */
1598 EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U),
1599 /* .. .. FINISH: UNLOCK DDR */
1600 /* .. .. START: CHECK DDR STATUS */
1601 /* .. .. ddrc_reg_operating_mode = 1 */
1602 /* .. .. ==> 0XF8006054[2:0] = 0x00000001U */
1603 /* .. .. ==> MASK : 0x00000007U VAL : 0x00000001U */
1604 /* .. .. */
1605 EMIT_MASKPOLL(0XF8006054, 0x00000007U),
1606 /* .. .. FINISH: CHECK DDR STATUS */
1607 /* .. FINISH: DDR INITIALIZATION */
1608 /* FINISH: top */
1609 /* */
1610 EMIT_EXIT(),
1611
1612 /* */
1613};
1614
1615unsigned long ps7_mio_init_data_3_0[] = {
1616 /* START: top */
1617 /* .. START: SLCR SETTINGS */
1618 /* .. UNLOCK_KEY = 0XDF0D */
1619 /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
1620 /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */
1621 /* .. */
1622 EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
1623 /* .. FINISH: SLCR SETTINGS */
1624 /* .. START: OCM REMAPPING */
1625 /* .. VREF_EN = 0x1 */
1626 /* .. ==> 0XF8000B00[0:0] = 0x00000001U */
1627 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
1628 /* .. VREF_SEL = 0x0 */
1629 /* .. ==> 0XF8000B00[6:4] = 0x00000000U */
1630 /* .. ==> MASK : 0x00000070U VAL : 0x00000000U */
1631 /* .. */
1632 EMIT_MASKWRITE(0XF8000B00, 0x00000071U, 0x00000001U),
1633 /* .. FINISH: OCM REMAPPING */
1634 /* .. START: DDRIOB SETTINGS */
1635 /* .. reserved_INP_POWER = 0x0 */
1636 /* .. ==> 0XF8000B40[0:0] = 0x00000000U */
1637 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
1638 /* .. INP_TYPE = 0x0 */
1639 /* .. ==> 0XF8000B40[2:1] = 0x00000000U */
1640 /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */
1641 /* .. DCI_UPDATE_B = 0x0 */
1642 /* .. ==> 0XF8000B40[3:3] = 0x00000000U */
1643 /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
1644 /* .. TERM_EN = 0x0 */
1645 /* .. ==> 0XF8000B40[4:4] = 0x00000000U */
1646 /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */
1647 /* .. DCI_TYPE = 0x0 */
1648 /* .. ==> 0XF8000B40[6:5] = 0x00000000U */
1649 /* .. ==> MASK : 0x00000060U VAL : 0x00000000U */
1650 /* .. IBUF_DISABLE_MODE = 0x0 */
1651 /* .. ==> 0XF8000B40[7:7] = 0x00000000U */
1652 /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
1653 /* .. TERM_DISABLE_MODE = 0x0 */
1654 /* .. ==> 0XF8000B40[8:8] = 0x00000000U */
1655 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
1656 /* .. OUTPUT_EN = 0x3 */
1657 /* .. ==> 0XF8000B40[10:9] = 0x00000003U */
1658 /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
1659 /* .. PULLUP_EN = 0x0 */
1660 /* .. ==> 0XF8000B40[11:11] = 0x00000000U */
1661 /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
1662 /* .. */
1663 EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U),
1664 /* .. reserved_INP_POWER = 0x0 */
1665 /* .. ==> 0XF8000B44[0:0] = 0x00000000U */
1666 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
1667 /* .. INP_TYPE = 0x0 */
1668 /* .. ==> 0XF8000B44[2:1] = 0x00000000U */
1669 /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */
1670 /* .. DCI_UPDATE_B = 0x0 */
1671 /* .. ==> 0XF8000B44[3:3] = 0x00000000U */
1672 /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
1673 /* .. TERM_EN = 0x0 */
1674 /* .. ==> 0XF8000B44[4:4] = 0x00000000U */
1675 /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */
1676 /* .. DCI_TYPE = 0x0 */
1677 /* .. ==> 0XF8000B44[6:5] = 0x00000000U */
1678 /* .. ==> MASK : 0x00000060U VAL : 0x00000000U */
1679 /* .. IBUF_DISABLE_MODE = 0x0 */
1680 /* .. ==> 0XF8000B44[7:7] = 0x00000000U */
1681 /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
1682 /* .. TERM_DISABLE_MODE = 0x0 */
1683 /* .. ==> 0XF8000B44[8:8] = 0x00000000U */
1684 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
1685 /* .. OUTPUT_EN = 0x3 */
1686 /* .. ==> 0XF8000B44[10:9] = 0x00000003U */
1687 /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
1688 /* .. PULLUP_EN = 0x0 */
1689 /* .. ==> 0XF8000B44[11:11] = 0x00000000U */
1690 /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
1691 /* .. */
1692 EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U),
1693 /* .. reserved_INP_POWER = 0x0 */
1694 /* .. ==> 0XF8000B48[0:0] = 0x00000000U */
1695 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
1696 /* .. INP_TYPE = 0x1 */
1697 /* .. ==> 0XF8000B48[2:1] = 0x00000001U */
1698 /* .. ==> MASK : 0x00000006U VAL : 0x00000002U */
1699 /* .. DCI_UPDATE_B = 0x0 */
1700 /* .. ==> 0XF8000B48[3:3] = 0x00000000U */
1701 /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
1702 /* .. TERM_EN = 0x1 */
1703 /* .. ==> 0XF8000B48[4:4] = 0x00000001U */
1704 /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */
1705 /* .. DCI_TYPE = 0x3 */
1706 /* .. ==> 0XF8000B48[6:5] = 0x00000003U */
1707 /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */
1708 /* .. IBUF_DISABLE_MODE = 0 */
1709 /* .. ==> 0XF8000B48[7:7] = 0x00000000U */
1710 /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
1711 /* .. TERM_DISABLE_MODE = 0 */
1712 /* .. ==> 0XF8000B48[8:8] = 0x00000000U */
1713 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
1714 /* .. OUTPUT_EN = 0x3 */
1715 /* .. ==> 0XF8000B48[10:9] = 0x00000003U */
1716 /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
1717 /* .. PULLUP_EN = 0x0 */
1718 /* .. ==> 0XF8000B48[11:11] = 0x00000000U */
1719 /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
1720 /* .. */
1721 EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U),
1722 /* .. reserved_INP_POWER = 0x0 */
1723 /* .. ==> 0XF8000B4C[0:0] = 0x00000000U */
1724 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
1725 /* .. INP_TYPE = 0x1 */
1726 /* .. ==> 0XF8000B4C[2:1] = 0x00000001U */
1727 /* .. ==> MASK : 0x00000006U VAL : 0x00000002U */
1728 /* .. DCI_UPDATE_B = 0x0 */
1729 /* .. ==> 0XF8000B4C[3:3] = 0x00000000U */
1730 /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
1731 /* .. TERM_EN = 0x1 */
1732 /* .. ==> 0XF8000B4C[4:4] = 0x00000001U */
1733 /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */
1734 /* .. DCI_TYPE = 0x3 */
1735 /* .. ==> 0XF8000B4C[6:5] = 0x00000003U */
1736 /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */
1737 /* .. IBUF_DISABLE_MODE = 0 */
1738 /* .. ==> 0XF8000B4C[7:7] = 0x00000000U */
1739 /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
1740 /* .. TERM_DISABLE_MODE = 0 */
1741 /* .. ==> 0XF8000B4C[8:8] = 0x00000000U */
1742 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
1743 /* .. OUTPUT_EN = 0x3 */
1744 /* .. ==> 0XF8000B4C[10:9] = 0x00000003U */
1745 /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
1746 /* .. PULLUP_EN = 0x0 */
1747 /* .. ==> 0XF8000B4C[11:11] = 0x00000000U */
1748 /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
1749 /* .. */
1750 EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U),
1751 /* .. reserved_INP_POWER = 0x0 */
1752 /* .. ==> 0XF8000B50[0:0] = 0x00000000U */
1753 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
1754 /* .. INP_TYPE = 0x2 */
1755 /* .. ==> 0XF8000B50[2:1] = 0x00000002U */
1756 /* .. ==> MASK : 0x00000006U VAL : 0x00000004U */
1757 /* .. DCI_UPDATE_B = 0x0 */
1758 /* .. ==> 0XF8000B50[3:3] = 0x00000000U */
1759 /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
1760 /* .. TERM_EN = 0x1 */
1761 /* .. ==> 0XF8000B50[4:4] = 0x00000001U */
1762 /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */
1763 /* .. DCI_TYPE = 0x3 */
1764 /* .. ==> 0XF8000B50[6:5] = 0x00000003U */
1765 /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */
1766 /* .. IBUF_DISABLE_MODE = 0 */
1767 /* .. ==> 0XF8000B50[7:7] = 0x00000000U */
1768 /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
1769 /* .. TERM_DISABLE_MODE = 0 */
1770 /* .. ==> 0XF8000B50[8:8] = 0x00000000U */
1771 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
1772 /* .. OUTPUT_EN = 0x3 */
1773 /* .. ==> 0XF8000B50[10:9] = 0x00000003U */
1774 /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
1775 /* .. PULLUP_EN = 0x0 */
1776 /* .. ==> 0XF8000B50[11:11] = 0x00000000U */
1777 /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
1778 /* .. */
1779 EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U),
1780 /* .. reserved_INP_POWER = 0x0 */
1781 /* .. ==> 0XF8000B54[0:0] = 0x00000000U */
1782 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
1783 /* .. INP_TYPE = 0x2 */
1784 /* .. ==> 0XF8000B54[2:1] = 0x00000002U */
1785 /* .. ==> MASK : 0x00000006U VAL : 0x00000004U */
1786 /* .. DCI_UPDATE_B = 0x0 */
1787 /* .. ==> 0XF8000B54[3:3] = 0x00000000U */
1788 /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
1789 /* .. TERM_EN = 0x1 */
1790 /* .. ==> 0XF8000B54[4:4] = 0x00000001U */
1791 /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */
1792 /* .. DCI_TYPE = 0x3 */
1793 /* .. ==> 0XF8000B54[6:5] = 0x00000003U */
1794 /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */
1795 /* .. IBUF_DISABLE_MODE = 0 */
1796 /* .. ==> 0XF8000B54[7:7] = 0x00000000U */
1797 /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
1798 /* .. TERM_DISABLE_MODE = 0 */
1799 /* .. ==> 0XF8000B54[8:8] = 0x00000000U */
1800 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
1801 /* .. OUTPUT_EN = 0x3 */
1802 /* .. ==> 0XF8000B54[10:9] = 0x00000003U */
1803 /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
1804 /* .. PULLUP_EN = 0x0 */
1805 /* .. ==> 0XF8000B54[11:11] = 0x00000000U */
1806 /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
1807 /* .. */
1808 EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U),
1809 /* .. reserved_INP_POWER = 0x0 */
1810 /* .. ==> 0XF8000B58[0:0] = 0x00000000U */
1811 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
1812 /* .. INP_TYPE = 0x0 */
1813 /* .. ==> 0XF8000B58[2:1] = 0x00000000U */
1814 /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */
1815 /* .. DCI_UPDATE_B = 0x0 */
1816 /* .. ==> 0XF8000B58[3:3] = 0x00000000U */
1817 /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
1818 /* .. TERM_EN = 0x0 */
1819 /* .. ==> 0XF8000B58[4:4] = 0x00000000U */
1820 /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */
1821 /* .. DCI_TYPE = 0x0 */
1822 /* .. ==> 0XF8000B58[6:5] = 0x00000000U */
1823 /* .. ==> MASK : 0x00000060U VAL : 0x00000000U */
1824 /* .. IBUF_DISABLE_MODE = 0x0 */
1825 /* .. ==> 0XF8000B58[7:7] = 0x00000000U */
1826 /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
1827 /* .. TERM_DISABLE_MODE = 0x0 */
1828 /* .. ==> 0XF8000B58[8:8] = 0x00000000U */
1829 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
1830 /* .. OUTPUT_EN = 0x3 */
1831 /* .. ==> 0XF8000B58[10:9] = 0x00000003U */
1832 /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
1833 /* .. PULLUP_EN = 0x0 */
1834 /* .. ==> 0XF8000B58[11:11] = 0x00000000U */
1835 /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
1836 /* .. */
1837 EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U),
1838 /* .. reserved_DRIVE_P = 0x1c */
1839 /* .. ==> 0XF8000B5C[6:0] = 0x0000001CU */
1840 /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */
1841 /* .. reserved_DRIVE_N = 0xc */
1842 /* .. ==> 0XF8000B5C[13:7] = 0x0000000CU */
1843 /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */
1844 /* .. reserved_SLEW_P = 0x3 */
1845 /* .. ==> 0XF8000B5C[18:14] = 0x00000003U */
1846 /* .. ==> MASK : 0x0007C000U VAL : 0x0000C000U */
1847 /* .. reserved_SLEW_N = 0x3 */
1848 /* .. ==> 0XF8000B5C[23:19] = 0x00000003U */
1849 /* .. ==> MASK : 0x00F80000U VAL : 0x00180000U */
1850 /* .. reserved_GTL = 0x0 */
1851 /* .. ==> 0XF8000B5C[26:24] = 0x00000000U */
1852 /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */
1853 /* .. reserved_RTERM = 0x0 */
1854 /* .. ==> 0XF8000B5C[31:27] = 0x00000000U */
1855 /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */
1856 /* .. */
1857 EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
1858 /* .. reserved_DRIVE_P = 0x1c */
1859 /* .. ==> 0XF8000B60[6:0] = 0x0000001CU */
1860 /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */
1861 /* .. reserved_DRIVE_N = 0xc */
1862 /* .. ==> 0XF8000B60[13:7] = 0x0000000CU */
1863 /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */
1864 /* .. reserved_SLEW_P = 0x6 */
1865 /* .. ==> 0XF8000B60[18:14] = 0x00000006U */
1866 /* .. ==> MASK : 0x0007C000U VAL : 0x00018000U */
1867 /* .. reserved_SLEW_N = 0x1f */
1868 /* .. ==> 0XF8000B60[23:19] = 0x0000001FU */
1869 /* .. ==> MASK : 0x00F80000U VAL : 0x00F80000U */
1870 /* .. reserved_GTL = 0x0 */
1871 /* .. ==> 0XF8000B60[26:24] = 0x00000000U */
1872 /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */
1873 /* .. reserved_RTERM = 0x0 */
1874 /* .. ==> 0XF8000B60[31:27] = 0x00000000U */
1875 /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */
1876 /* .. */
1877 EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
1878 /* .. reserved_DRIVE_P = 0x1c */
1879 /* .. ==> 0XF8000B64[6:0] = 0x0000001CU */
1880 /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */
1881 /* .. reserved_DRIVE_N = 0xc */
1882 /* .. ==> 0XF8000B64[13:7] = 0x0000000CU */
1883 /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */
1884 /* .. reserved_SLEW_P = 0x6 */
1885 /* .. ==> 0XF8000B64[18:14] = 0x00000006U */
1886 /* .. ==> MASK : 0x0007C000U VAL : 0x00018000U */
1887 /* .. reserved_SLEW_N = 0x1f */
1888 /* .. ==> 0XF8000B64[23:19] = 0x0000001FU */
1889 /* .. ==> MASK : 0x00F80000U VAL : 0x00F80000U */
1890 /* .. reserved_GTL = 0x0 */
1891 /* .. ==> 0XF8000B64[26:24] = 0x00000000U */
1892 /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */
1893 /* .. reserved_RTERM = 0x0 */
1894 /* .. ==> 0XF8000B64[31:27] = 0x00000000U */
1895 /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */
1896 /* .. */
1897 EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
1898 /* .. reserved_DRIVE_P = 0x1c */
1899 /* .. ==> 0XF8000B68[6:0] = 0x0000001CU */
1900 /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */
1901 /* .. reserved_DRIVE_N = 0xc */
1902 /* .. ==> 0XF8000B68[13:7] = 0x0000000CU */
1903 /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */
1904 /* .. reserved_SLEW_P = 0x6 */
1905 /* .. ==> 0XF8000B68[18:14] = 0x00000006U */
1906 /* .. ==> MASK : 0x0007C000U VAL : 0x00018000U */
1907 /* .. reserved_SLEW_N = 0x1f */
1908 /* .. ==> 0XF8000B68[23:19] = 0x0000001FU */
1909 /* .. ==> MASK : 0x00F80000U VAL : 0x00F80000U */
1910 /* .. reserved_GTL = 0x0 */
1911 /* .. ==> 0XF8000B68[26:24] = 0x00000000U */
1912 /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */
1913 /* .. reserved_RTERM = 0x0 */
1914 /* .. ==> 0XF8000B68[31:27] = 0x00000000U */
1915 /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */
1916 /* .. */
1917 EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
1918 /* .. VREF_INT_EN = 0x0 */
1919 /* .. ==> 0XF8000B6C[0:0] = 0x00000000U */
1920 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
1921 /* .. VREF_SEL = 0x0 */
1922 /* .. ==> 0XF8000B6C[4:1] = 0x00000000U */
1923 /* .. ==> MASK : 0x0000001EU VAL : 0x00000000U */
1924 /* .. VREF_EXT_EN = 0x3 */
1925 /* .. ==> 0XF8000B6C[6:5] = 0x00000003U */
1926 /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */
1927 /* .. reserved_VREF_PULLUP_EN = 0x0 */
1928 /* .. ==> 0XF8000B6C[8:7] = 0x00000000U */
1929 /* .. ==> MASK : 0x00000180U VAL : 0x00000000U */
1930 /* .. REFIO_EN = 0x1 */
1931 /* .. ==> 0XF8000B6C[9:9] = 0x00000001U */
1932 /* .. ==> MASK : 0x00000200U VAL : 0x00000200U */
1933 /* .. reserved_REFIO_TEST = 0x0 */
1934 /* .. ==> 0XF8000B6C[11:10] = 0x00000000U */
1935 /* .. ==> MASK : 0x00000C00U VAL : 0x00000000U */
1936 /* .. reserved_REFIO_PULLUP_EN = 0x0 */
1937 /* .. ==> 0XF8000B6C[12:12] = 0x00000000U */
1938 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
1939 /* .. reserved_DRST_B_PULLUP_EN = 0x0 */
1940 /* .. ==> 0XF8000B6C[13:13] = 0x00000000U */
1941 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
1942 /* .. reserved_CKE_PULLUP_EN = 0x0 */
1943 /* .. ==> 0XF8000B6C[14:14] = 0x00000000U */
1944 /* .. ==> MASK : 0x00004000U VAL : 0x00000000U */
1945 /* .. */
1946 EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU, 0x00000260U),
1947 /* .. .. START: ASSERT RESET */
1948 /* .. .. RESET = 1 */
1949 /* .. .. ==> 0XF8000B70[0:0] = 0x00000001U */
1950 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
1951 /* .. .. */
1952 EMIT_MASKWRITE(0XF8000B70, 0x00000001U, 0x00000001U),
1953 /* .. .. FINISH: ASSERT RESET */
1954 /* .. .. START: DEASSERT RESET */
1955 /* .. .. RESET = 0 */
1956 /* .. .. ==> 0XF8000B70[0:0] = 0x00000000U */
1957 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
1958 /* .. .. reserved_VRN_OUT = 0x1 */
1959 /* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */
1960 /* .. .. ==> MASK : 0x00000020U VAL : 0x00000020U */
1961 /* .. .. */
1962 EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U),
1963 /* .. .. FINISH: DEASSERT RESET */
1964 /* .. .. RESET = 0x1 */
1965 /* .. .. ==> 0XF8000B70[0:0] = 0x00000001U */
1966 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
1967 /* .. .. ENABLE = 0x1 */
1968 /* .. .. ==> 0XF8000B70[1:1] = 0x00000001U */
1969 /* .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */
1970 /* .. .. reserved_VRP_TRI = 0x0 */
1971 /* .. .. ==> 0XF8000B70[2:2] = 0x00000000U */
1972 /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
1973 /* .. .. reserved_VRN_TRI = 0x0 */
1974 /* .. .. ==> 0XF8000B70[3:3] = 0x00000000U */
1975 /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
1976 /* .. .. reserved_VRP_OUT = 0x0 */
1977 /* .. .. ==> 0XF8000B70[4:4] = 0x00000000U */
1978 /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
1979 /* .. .. reserved_VRN_OUT = 0x1 */
1980 /* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */
1981 /* .. .. ==> MASK : 0x00000020U VAL : 0x00000020U */
1982 /* .. .. NREF_OPT1 = 0x0 */
1983 /* .. .. ==> 0XF8000B70[7:6] = 0x00000000U */
1984 /* .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U */
1985 /* .. .. NREF_OPT2 = 0x0 */
1986 /* .. .. ==> 0XF8000B70[10:8] = 0x00000000U */
1987 /* .. .. ==> MASK : 0x00000700U VAL : 0x00000000U */
1988 /* .. .. NREF_OPT4 = 0x1 */
1989 /* .. .. ==> 0XF8000B70[13:11] = 0x00000001U */
1990 /* .. .. ==> MASK : 0x00003800U VAL : 0x00000800U */
1991 /* .. .. PREF_OPT1 = 0x0 */
1992 /* .. .. ==> 0XF8000B70[15:14] = 0x00000000U */
1993 /* .. .. ==> MASK : 0x0000C000U VAL : 0x00000000U */
1994 /* .. .. PREF_OPT2 = 0x0 */
1995 /* .. .. ==> 0XF8000B70[19:17] = 0x00000000U */
1996 /* .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U */
1997 /* .. .. UPDATE_CONTROL = 0x0 */
1998 /* .. .. ==> 0XF8000B70[20:20] = 0x00000000U */
1999 /* .. .. ==> MASK : 0x00100000U VAL : 0x00000000U */
2000 /* .. .. reserved_INIT_COMPLETE = 0x0 */
2001 /* .. .. ==> 0XF8000B70[21:21] = 0x00000000U */
2002 /* .. .. ==> MASK : 0x00200000U VAL : 0x00000000U */
2003 /* .. .. reserved_TST_CLK = 0x0 */
2004 /* .. .. ==> 0XF8000B70[22:22] = 0x00000000U */
2005 /* .. .. ==> MASK : 0x00400000U VAL : 0x00000000U */
2006 /* .. .. reserved_TST_HLN = 0x0 */
2007 /* .. .. ==> 0XF8000B70[23:23] = 0x00000000U */
2008 /* .. .. ==> MASK : 0x00800000U VAL : 0x00000000U */
2009 /* .. .. reserved_TST_HLP = 0x0 */
2010 /* .. .. ==> 0XF8000B70[24:24] = 0x00000000U */
2011 /* .. .. ==> MASK : 0x01000000U VAL : 0x00000000U */
2012 /* .. .. reserved_TST_RST = 0x0 */
2013 /* .. .. ==> 0XF8000B70[25:25] = 0x00000000U */
2014 /* .. .. ==> MASK : 0x02000000U VAL : 0x00000000U */
2015 /* .. .. reserved_INT_DCI_EN = 0x0 */
2016 /* .. .. ==> 0XF8000B70[26:26] = 0x00000000U */
2017 /* .. .. ==> MASK : 0x04000000U VAL : 0x00000000U */
2018 /* .. .. */
2019 EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU, 0x00000823U),
2020 /* .. FINISH: DDRIOB SETTINGS */
2021 /* .. START: MIO PROGRAMMING */
2022 /* .. TRI_ENABLE = 0 */
Michal Simek264065f2016-03-03 13:25:03 +0100[diff] [blame]2023 /* .. ==> 0XF8000700[0:0] = 0x00000000U */
2024 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
2025 /* .. L0_SEL = 0 */
2026 /* .. ==> 0XF8000700[1:1] = 0x00000000U */
2027 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
2028 /* .. L1_SEL = 0 */
2029 /* .. ==> 0XF8000700[2:2] = 0x00000000U */
2030 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
2031 /* .. L2_SEL = 0 */
2032 /* .. ==> 0XF8000700[4:3] = 0x00000000U */
2033 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
2034 /* .. L3_SEL = 0 */
2035 /* .. ==> 0XF8000700[7:5] = 0x00000000U */
2036 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
2037 /* .. Speed = 0 */
2038 /* .. ==> 0XF8000700[8:8] = 0x00000000U */
2039 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
2040 /* .. IO_Type = 3 */
2041 /* .. ==> 0XF8000700[11:9] = 0x00000003U */
2042 /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
2043 /* .. PULLUP = 1 */
2044 /* .. ==> 0XF8000700[12:12] = 0x00000001U */
2045 /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
2046 /* .. DisableRcvr = 0 */
2047 /* .. ==> 0XF8000700[13:13] = 0x00000000U */
2048 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
2049 /* .. */
2050 EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00001600U),
2051 /* .. TRI_ENABLE = 0 */
Nathan Rossi4eeed0e2015-11-24 19:34:09 +1000[diff] [blame]2052 /* .. ==> 0XF8000704[0:0] = 0x00000000U */
2053 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
2054 /* .. L0_SEL = 1 */
2055 /* .. ==> 0XF8000704[1:1] = 0x00000001U */
2056 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
2057 /* .. L1_SEL = 0 */
2058 /* .. ==> 0XF8000704[2:2] = 0x00000000U */
2059 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
2060 /* .. L2_SEL = 0 */
2061 /* .. ==> 0XF8000704[4:3] = 0x00000000U */
2062 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
2063 /* .. L3_SEL = 0 */
2064 /* .. ==> 0XF8000704[7:5] = 0x00000000U */
2065 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
2066 /* .. Speed = 1 */
2067 /* .. ==> 0XF8000704[8:8] = 0x00000001U */
2068 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
2069 /* .. IO_Type = 3 */
2070 /* .. ==> 0XF8000704[11:9] = 0x00000003U */
2071 /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
2072 /* .. PULLUP = 0 */
2073 /* .. ==> 0XF8000704[12:12] = 0x00000000U */
2074 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
2075 /* .. DisableRcvr = 0 */
2076 /* .. ==> 0XF8000704[13:13] = 0x00000000U */
2077 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
2078 /* .. */
2079 EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00000702U),
2080 /* .. TRI_ENABLE = 0 */
2081 /* .. ==> 0XF8000708[0:0] = 0x00000000U */
2082 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
2083 /* .. L0_SEL = 1 */
2084 /* .. ==> 0XF8000708[1:1] = 0x00000001U */
2085 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
2086 /* .. L1_SEL = 0 */
2087 /* .. ==> 0XF8000708[2:2] = 0x00000000U */
2088 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
2089 /* .. L2_SEL = 0 */
2090 /* .. ==> 0XF8000708[4:3] = 0x00000000U */
2091 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
2092 /* .. L3_SEL = 0 */
2093 /* .. ==> 0XF8000708[7:5] = 0x00000000U */
2094 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
2095 /* .. Speed = 1 */
2096 /* .. ==> 0XF8000708[8:8] = 0x00000001U */
2097 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
2098 /* .. IO_Type = 3 */
2099 /* .. ==> 0XF8000708[11:9] = 0x00000003U */
2100 /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
2101 /* .. PULLUP = 0 */
2102 /* .. ==> 0XF8000708[12:12] = 0x00000000U */
2103 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
2104 /* .. DisableRcvr = 0 */
2105 /* .. ==> 0XF8000708[13:13] = 0x00000000U */
2106 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
2107 /* .. */
2108 EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000702U),
2109 /* .. TRI_ENABLE = 0 */
2110 /* .. ==> 0XF800070C[0:0] = 0x00000000U */
2111 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
2112 /* .. L0_SEL = 1 */
2113 /* .. ==> 0XF800070C[1:1] = 0x00000001U */
2114 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
2115 /* .. L1_SEL = 0 */
2116 /* .. ==> 0XF800070C[2:2] = 0x00000000U */
2117 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
2118 /* .. L2_SEL = 0 */
2119 /* .. ==> 0XF800070C[4:3] = 0x00000000U */
2120 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
2121 /* .. L3_SEL = 0 */
2122 /* .. ==> 0XF800070C[7:5] = 0x00000000U */
2123 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
2124 /* .. Speed = 1 */
2125 /* .. ==> 0XF800070C[8:8] = 0x00000001U */
2126 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
2127 /* .. IO_Type = 3 */
2128 /* .. ==> 0XF800070C[11:9] = 0x00000003U */
2129 /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
2130 /* .. PULLUP = 0 */
2131 /* .. ==> 0XF800070C[12:12] = 0x00000000U */
2132 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
2133 /* .. DisableRcvr = 0 */
2134 /* .. ==> 0XF800070C[13:13] = 0x00000000U */
2135 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
2136 /* .. */
2137 EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000702U),
2138 /* .. TRI_ENABLE = 0 */
2139 /* .. ==> 0XF8000710[0:0] = 0x00000000U */
2140 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
2141 /* .. L0_SEL = 1 */
2142 /* .. ==> 0XF8000710[1:1] = 0x00000001U */
2143 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
2144 /* .. L1_SEL = 0 */
2145 /* .. ==> 0XF8000710[2:2] = 0x00000000U */
2146 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
2147 /* .. L2_SEL = 0 */
2148 /* .. ==> 0XF8000710[4:3] = 0x00000000U */
2149 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
2150 /* .. L3_SEL = 0 */
2151 /* .. ==> 0XF8000710[7:5] = 0x00000000U */
2152 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
2153 /* .. Speed = 1 */
2154 /* .. ==> 0XF8000710[8:8] = 0x00000001U */
2155 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
2156 /* .. IO_Type = 3 */
2157 /* .. ==> 0XF8000710[11:9] = 0x00000003U */
2158 /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
2159 /* .. PULLUP = 0 */
2160 /* .. ==> 0XF8000710[12:12] = 0x00000000U */
2161 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
2162 /* .. DisableRcvr = 0 */
2163 /* .. ==> 0XF8000710[13:13] = 0x00000000U */
2164 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
2165 /* .. */
2166 EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000702U),
2167 /* .. TRI_ENABLE = 0 */
2168 /* .. ==> 0XF8000714[0:0] = 0x00000000U */
2169 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
2170 /* .. L0_SEL = 1 */
2171 /* .. ==> 0XF8000714[1:1] = 0x00000001U */
2172 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
2173 /* .. L1_SEL = 0 */
2174 /* .. ==> 0XF8000714[2:2] = 0x00000000U */
2175 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
2176 /* .. L2_SEL = 0 */
2177 /* .. ==> 0XF8000714[4:3] = 0x00000000U */
2178 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
2179 /* .. L3_SEL = 0 */
2180 /* .. ==> 0XF8000714[7:5] = 0x00000000U */
2181 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
2182 /* .. Speed = 1 */
2183 /* .. ==> 0XF8000714[8:8] = 0x00000001U */
2184 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
2185 /* .. IO_Type = 3 */
2186 /* .. ==> 0XF8000714[11:9] = 0x00000003U */
2187 /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
2188 /* .. PULLUP = 0 */
2189 /* .. ==> 0XF8000714[12:12] = 0x00000000U */
2190 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
2191 /* .. DisableRcvr = 0 */
2192 /* .. ==> 0XF8000714[13:13] = 0x00000000U */
2193 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
2194 /* .. */
2195 EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000702U),
2196 /* .. TRI_ENABLE = 0 */
2197 /* .. ==> 0XF8000718[0:0] = 0x00000000U */
2198 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
2199 /* .. L0_SEL = 1 */
2200 /* .. ==> 0XF8000718[1:1] = 0x00000001U */
2201 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
2202 /* .. L1_SEL = 0 */
2203 /* .. ==> 0XF8000718[2:2] = 0x00000000U */
2204 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
2205 /* .. L2_SEL = 0 */
2206 /* .. ==> 0XF8000718[4:3] = 0x00000000U */
2207 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
2208 /* .. L3_SEL = 0 */
2209 /* .. ==> 0XF8000718[7:5] = 0x00000000U */
2210 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
2211 /* .. Speed = 1 */
2212 /* .. ==> 0XF8000718[8:8] = 0x00000001U */
2213 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
2214 /* .. IO_Type = 3 */
2215 /* .. ==> 0XF8000718[11:9] = 0x00000003U */
2216 /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
2217 /* .. PULLUP = 0 */
2218 /* .. ==> 0XF8000718[12:12] = 0x00000000U */
2219 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
2220 /* .. DisableRcvr = 0 */
2221 /* .. ==> 0XF8000718[13:13] = 0x00000000U */
2222 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
2223 /* .. */
2224 EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000702U),
2225 /* .. TRI_ENABLE = 0 */
Michal Simek264065f2016-03-03 13:25:03 +0100[diff] [blame]2226 /* .. ==> 0XF800071C[0:0] = 0x00000000U */
2227 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
2228 /* .. L0_SEL = 0 */
2229 /* .. ==> 0XF800071C[1:1] = 0x00000000U */
2230 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
2231 /* .. L1_SEL = 0 */
2232 /* .. ==> 0XF800071C[2:2] = 0x00000000U */
2233 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
2234 /* .. L2_SEL = 0 */
2235 /* .. ==> 0XF800071C[4:3] = 0x00000000U */
2236 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
2237 /* .. L3_SEL = 0 */
2238 /* .. ==> 0XF800071C[7:5] = 0x00000000U */
2239 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
2240 /* .. Speed = 0 */
2241 /* .. ==> 0XF800071C[8:8] = 0x00000000U */
2242 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
2243 /* .. IO_Type = 3 */
2244 /* .. ==> 0XF800071C[11:9] = 0x00000003U */
2245 /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
2246 /* .. PULLUP = 0 */
2247 /* .. ==> 0XF800071C[12:12] = 0x00000000U */
2248 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
2249 /* .. DisableRcvr = 0 */
2250 /* .. ==> 0XF800071C[13:13] = 0x00000000U */
2251 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
2252 /* .. */
2253 EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000600U),
2254 /* .. TRI_ENABLE = 0 */
2255 /* .. ==> 0XF8000720[0:0] = 0x00000000U */
2256 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
2257 /* .. L0_SEL = 1 */
2258 /* .. ==> 0XF8000720[1:1] = 0x00000001U */
2259 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
2260 /* .. L1_SEL = 0 */
2261 /* .. ==> 0XF8000720[2:2] = 0x00000000U */
2262 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
2263 /* .. L2_SEL = 0 */
2264 /* .. ==> 0XF8000720[4:3] = 0x00000000U */
2265 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
2266 /* .. L3_SEL = 0 */
2267 /* .. ==> 0XF8000720[7:5] = 0x00000000U */
2268 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
2269 /* .. Speed = 1 */
2270 /* .. ==> 0XF8000720[8:8] = 0x00000001U */
2271 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
2272 /* .. IO_Type = 3 */
2273 /* .. ==> 0XF8000720[11:9] = 0x00000003U */
2274 /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
2275 /* .. PULLUP = 0 */
2276 /* .. ==> 0XF8000720[12:12] = 0x00000000U */
2277 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
2278 /* .. DisableRcvr = 0 */
2279 /* .. ==> 0XF8000720[13:13] = 0x00000000U */
2280 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
2281 /* .. */
2282 EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000702U),
2283 /* .. TRI_ENABLE = 0 */
2284 /* .. ==> 0XF8000724[0:0] = 0x00000000U */
2285 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
2286 /* .. L0_SEL = 0 */
2287 /* .. ==> 0XF8000724[1:1] = 0x00000000U */
2288 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
2289 /* .. L1_SEL = 0 */
2290 /* .. ==> 0XF8000724[2:2] = 0x00000000U */
2291 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
2292 /* .. L2_SEL = 0 */
2293 /* .. ==> 0XF8000724[4:3] = 0x00000000U */
2294 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
2295 /* .. L3_SEL = 0 */
2296 /* .. ==> 0XF8000724[7:5] = 0x00000000U */
2297 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
2298 /* .. Speed = 0 */
2299 /* .. ==> 0XF8000724[8:8] = 0x00000000U */
2300 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
2301 /* .. IO_Type = 3 */
2302 /* .. ==> 0XF8000724[11:9] = 0x00000003U */
2303 /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
2304 /* .. PULLUP = 1 */
2305 /* .. ==> 0XF8000724[12:12] = 0x00000001U */
2306 /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
2307 /* .. DisableRcvr = 0 */
2308 /* .. ==> 0XF8000724[13:13] = 0x00000000U */
2309 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
2310 /* .. */
2311 EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00001600U),
2312 /* .. TRI_ENABLE = 0 */
2313 /* .. ==> 0XF8000728[0:0] = 0x00000000U */
2314 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
2315 /* .. L0_SEL = 0 */
2316 /* .. ==> 0XF8000728[1:1] = 0x00000000U */
2317 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
2318 /* .. L1_SEL = 0 */
2319 /* .. ==> 0XF8000728[2:2] = 0x00000000U */
2320 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
2321 /* .. L2_SEL = 0 */
2322 /* .. ==> 0XF8000728[4:3] = 0x00000000U */
2323 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
2324 /* .. L3_SEL = 0 */
2325 /* .. ==> 0XF8000728[7:5] = 0x00000000U */
2326 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
2327 /* .. Speed = 0 */
2328 /* .. ==> 0XF8000728[8:8] = 0x00000000U */
2329 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
2330 /* .. IO_Type = 3 */
2331 /* .. ==> 0XF8000728[11:9] = 0x00000003U */
2332 /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
2333 /* .. PULLUP = 1 */
2334 /* .. ==> 0XF8000728[12:12] = 0x00000001U */
2335 /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
2336 /* .. DisableRcvr = 0 */
2337 /* .. ==> 0XF8000728[13:13] = 0x00000000U */
2338 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
2339 /* .. */
2340 EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x00001600U),
2341 /* .. TRI_ENABLE = 0 */
2342 /* .. ==> 0XF800072C[0:0] = 0x00000000U */
2343 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
2344 /* .. L0_SEL = 0 */
2345 /* .. ==> 0XF800072C[1:1] = 0x00000000U */
2346 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
2347 /* .. L1_SEL = 0 */
2348 /* .. ==> 0XF800072C[2:2] = 0x00000000U */
2349 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
2350 /* .. L2_SEL = 0 */
2351 /* .. ==> 0XF800072C[4:3] = 0x00000000U */
2352 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
2353 /* .. L3_SEL = 0 */
2354 /* .. ==> 0XF800072C[7:5] = 0x00000000U */
2355 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
2356 /* .. Speed = 0 */
2357 /* .. ==> 0XF800072C[8:8] = 0x00000000U */
2358 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
2359 /* .. IO_Type = 3 */
2360 /* .. ==> 0XF800072C[11:9] = 0x00000003U */
2361 /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
2362 /* .. PULLUP = 1 */
2363 /* .. ==> 0XF800072C[12:12] = 0x00000001U */
2364 /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
2365 /* .. DisableRcvr = 0 */
2366 /* .. ==> 0XF800072C[13:13] = 0x00000000U */
2367 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
2368 /* .. */
2369 EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x00001600U),
2370 /* .. TRI_ENABLE = 0 */
2371 /* .. ==> 0XF8000730[0:0] = 0x00000000U */
2372 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
2373 /* .. L0_SEL = 0 */
2374 /* .. ==> 0XF8000730[1:1] = 0x00000000U */
2375 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
2376 /* .. L1_SEL = 0 */
2377 /* .. ==> 0XF8000730[2:2] = 0x00000000U */
2378 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
2379 /* .. L2_SEL = 0 */
2380 /* .. ==> 0XF8000730[4:3] = 0x00000000U */
2381 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
2382 /* .. L3_SEL = 0 */
2383 /* .. ==> 0XF8000730[7:5] = 0x00000000U */
2384 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
2385 /* .. Speed = 0 */
2386 /* .. ==> 0XF8000730[8:8] = 0x00000000U */
2387 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
2388 /* .. IO_Type = 3 */
2389 /* .. ==> 0XF8000730[11:9] = 0x00000003U */
2390 /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
2391 /* .. PULLUP = 1 */
2392 /* .. ==> 0XF8000730[12:12] = 0x00000001U */
2393 /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
2394 /* .. DisableRcvr = 0 */
2395 /* .. ==> 0XF8000730[13:13] = 0x00000000U */
2396 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
2397 /* .. */
2398 EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x00001600U),
2399 /* .. TRI_ENABLE = 0 */
2400 /* .. ==> 0XF8000734[0:0] = 0x00000000U */
2401 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
2402 /* .. L0_SEL = 0 */
2403 /* .. ==> 0XF8000734[1:1] = 0x00000000U */
2404 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
2405 /* .. L1_SEL = 0 */
2406 /* .. ==> 0XF8000734[2:2] = 0x00000000U */
2407 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
2408 /* .. L2_SEL = 0 */
2409 /* .. ==> 0XF8000734[4:3] = 0x00000000U */
2410 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
2411 /* .. L3_SEL = 0 */
2412 /* .. ==> 0XF8000734[7:5] = 0x00000000U */
2413 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
2414 /* .. Speed = 0 */
2415 /* .. ==> 0XF8000734[8:8] = 0x00000000U */
2416 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
2417 /* .. IO_Type = 3 */
2418 /* .. ==> 0XF8000734[11:9] = 0x00000003U */
2419 /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
2420 /* .. PULLUP = 1 */
2421 /* .. ==> 0XF8000734[12:12] = 0x00000001U */
2422 /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
2423 /* .. DisableRcvr = 0 */
2424 /* .. ==> 0XF8000734[13:13] = 0x00000000U */
2425 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
2426 /* .. */
2427 EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x00001600U),
2428 /* .. TRI_ENABLE = 0 */
2429 /* .. ==> 0XF8000738[0:0] = 0x00000000U */
2430 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
2431 /* .. L0_SEL = 0 */
2432 /* .. ==> 0XF8000738[1:1] = 0x00000000U */
2433 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
2434 /* .. L1_SEL = 0 */
2435 /* .. ==> 0XF8000738[2:2] = 0x00000000U */
2436 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
2437 /* .. L2_SEL = 0 */
2438 /* .. ==> 0XF8000738[4:3] = 0x00000000U */
2439 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
2440 /* .. L3_SEL = 0 */
2441 /* .. ==> 0XF8000738[7:5] = 0x00000000U */
2442 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
2443 /* .. Speed = 0 */
2444 /* .. ==> 0XF8000738[8:8] = 0x00000000U */
2445 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
2446 /* .. IO_Type = 3 */
2447 /* .. ==> 0XF8000738[11:9] = 0x00000003U */
2448 /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
2449 /* .. PULLUP = 1 */
2450 /* .. ==> 0XF8000738[12:12] = 0x00000001U */
2451 /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
2452 /* .. DisableRcvr = 0 */
2453 /* .. ==> 0XF8000738[13:13] = 0x00000000U */
2454 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
2455 /* .. */
2456 EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x00001600U),
2457 /* .. TRI_ENABLE = 0 */
2458 /* .. ==> 0XF800073C[0:0] = 0x00000000U */
2459 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
2460 /* .. L0_SEL = 0 */
2461 /* .. ==> 0XF800073C[1:1] = 0x00000000U */
2462 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
2463 /* .. L1_SEL = 0 */
2464 /* .. ==> 0XF800073C[2:2] = 0x00000000U */
2465 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
2466 /* .. L2_SEL = 0 */
2467 /* .. ==> 0XF800073C[4:3] = 0x00000000U */
2468 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
2469 /* .. L3_SEL = 0 */
2470 /* .. ==> 0XF800073C[7:5] = 0x00000000U */
2471 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
2472 /* .. Speed = 0 */
2473 /* .. ==> 0XF800073C[8:8] = 0x00000000U */
2474 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
2475 /* .. IO_Type = 3 */
2476 /* .. ==> 0XF800073C[11:9] = 0x00000003U */
2477 /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
2478 /* .. PULLUP = 1 */
2479 /* .. ==> 0XF800073C[12:12] = 0x00000001U */
2480 /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
2481 /* .. DisableRcvr = 0 */
2482 /* .. ==> 0XF800073C[13:13] = 0x00000000U */
2483 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
2484 /* .. */
2485 EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x00001600U),
2486 /* .. TRI_ENABLE = 0 */
Nathan Rossi4eeed0e2015-11-24 19:34:09 +1000[diff] [blame]2487 /* .. ==> 0XF8000740[0:0] = 0x00000000U */
2488 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
2489 /* .. L0_SEL = 1 */
2490 /* .. ==> 0XF8000740[1:1] = 0x00000001U */
2491 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
2492 /* .. L1_SEL = 0 */
2493 /* .. ==> 0XF8000740[2:2] = 0x00000000U */
2494 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
2495 /* .. L2_SEL = 0 */
2496 /* .. ==> 0XF8000740[4:3] = 0x00000000U */
2497 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
2498 /* .. L3_SEL = 0 */
2499 /* .. ==> 0XF8000740[7:5] = 0x00000000U */
2500 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
2501 /* .. Speed = 1 */
2502 /* .. ==> 0XF8000740[8:8] = 0x00000001U */
2503 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
2504 /* .. IO_Type = 4 */
2505 /* .. ==> 0XF8000740[11:9] = 0x00000004U */
2506 /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
2507 /* .. PULLUP = 0 */
2508 /* .. ==> 0XF8000740[12:12] = 0x00000000U */
2509 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
2510 /* .. DisableRcvr = 1 */
2511 /* .. ==> 0XF8000740[13:13] = 0x00000001U */
2512 /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
2513 /* .. */
2514 EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x00002902U),
2515 /* .. TRI_ENABLE = 0 */
2516 /* .. ==> 0XF8000744[0:0] = 0x00000000U */
2517 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
2518 /* .. L0_SEL = 1 */
2519 /* .. ==> 0XF8000744[1:1] = 0x00000001U */
2520 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
2521 /* .. L1_SEL = 0 */
2522 /* .. ==> 0XF8000744[2:2] = 0x00000000U */
2523 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
2524 /* .. L2_SEL = 0 */
2525 /* .. ==> 0XF8000744[4:3] = 0x00000000U */
2526 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
2527 /* .. L3_SEL = 0 */
2528 /* .. ==> 0XF8000744[7:5] = 0x00000000U */
2529 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
2530 /* .. Speed = 1 */
2531 /* .. ==> 0XF8000744[8:8] = 0x00000001U */
2532 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
2533 /* .. IO_Type = 4 */
2534 /* .. ==> 0XF8000744[11:9] = 0x00000004U */
2535 /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
2536 /* .. PULLUP = 0 */
2537 /* .. ==> 0XF8000744[12:12] = 0x00000000U */
2538 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
2539 /* .. DisableRcvr = 1 */
2540 /* .. ==> 0XF8000744[13:13] = 0x00000001U */
2541 /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
2542 /* .. */
2543 EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x00002902U),
2544 /* .. TRI_ENABLE = 0 */
2545 /* .. ==> 0XF8000748[0:0] = 0x00000000U */
2546 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
2547 /* .. L0_SEL = 1 */
2548 /* .. ==> 0XF8000748[1:1] = 0x00000001U */
2549 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
2550 /* .. L1_SEL = 0 */
2551 /* .. ==> 0XF8000748[2:2] = 0x00000000U */
2552 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
2553 /* .. L2_SEL = 0 */
2554 /* .. ==> 0XF8000748[4:3] = 0x00000000U */
2555 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
2556 /* .. L3_SEL = 0 */
2557 /* .. ==> 0XF8000748[7:5] = 0x00000000U */
2558 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
2559 /* .. Speed = 1 */
2560 /* .. ==> 0XF8000748[8:8] = 0x00000001U */
2561 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
2562 /* .. IO_Type = 4 */
2563 /* .. ==> 0XF8000748[11:9] = 0x00000004U */
2564 /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
2565 /* .. PULLUP = 0 */
2566 /* .. ==> 0XF8000748[12:12] = 0x00000000U */
2567 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
2568 /* .. DisableRcvr = 1 */
2569 /* .. ==> 0XF8000748[13:13] = 0x00000001U */
2570 /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
2571 /* .. */
2572 EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00002902U),
2573 /* .. TRI_ENABLE = 0 */
2574 /* .. ==> 0XF800074C[0:0] = 0x00000000U */
2575 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
2576 /* .. L0_SEL = 1 */
2577 /* .. ==> 0XF800074C[1:1] = 0x00000001U */
2578 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
2579 /* .. L1_SEL = 0 */
2580 /* .. ==> 0XF800074C[2:2] = 0x00000000U */
2581 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
2582 /* .. L2_SEL = 0 */
2583 /* .. ==> 0XF800074C[4:3] = 0x00000000U */
2584 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
2585 /* .. L3_SEL = 0 */
2586 /* .. ==> 0XF800074C[7:5] = 0x00000000U */
2587 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
2588 /* .. Speed = 1 */
2589 /* .. ==> 0XF800074C[8:8] = 0x00000001U */
2590 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
2591 /* .. IO_Type = 4 */
2592 /* .. ==> 0XF800074C[11:9] = 0x00000004U */
2593 /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
2594 /* .. PULLUP = 0 */
2595 /* .. ==> 0XF800074C[12:12] = 0x00000000U */
2596 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
2597 /* .. DisableRcvr = 1 */
2598 /* .. ==> 0XF800074C[13:13] = 0x00000001U */
2599 /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
2600 /* .. */
2601 EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00002902U),
2602 /* .. TRI_ENABLE = 0 */
2603 /* .. ==> 0XF8000750[0:0] = 0x00000000U */
2604 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
2605 /* .. L0_SEL = 1 */
2606 /* .. ==> 0XF8000750[1:1] = 0x00000001U */
2607 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
2608 /* .. L1_SEL = 0 */
2609 /* .. ==> 0XF8000750[2:2] = 0x00000000U */
2610 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
2611 /* .. L2_SEL = 0 */
2612 /* .. ==> 0XF8000750[4:3] = 0x00000000U */
2613 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
2614 /* .. L3_SEL = 0 */
2615 /* .. ==> 0XF8000750[7:5] = 0x00000000U */
2616 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
2617 /* .. Speed = 1 */
2618 /* .. ==> 0XF8000750[8:8] = 0x00000001U */
2619 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
2620 /* .. IO_Type = 4 */
2621 /* .. ==> 0XF8000750[11:9] = 0x00000004U */
2622 /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
2623 /* .. PULLUP = 0 */
2624 /* .. ==> 0XF8000750[12:12] = 0x00000000U */
2625 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
2626 /* .. DisableRcvr = 1 */
2627 /* .. ==> 0XF8000750[13:13] = 0x00000001U */
2628 /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
2629 /* .. */
2630 EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00002902U),
2631 /* .. TRI_ENABLE = 0 */
2632 /* .. ==> 0XF8000754[0:0] = 0x00000000U */
2633 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
2634 /* .. L0_SEL = 1 */
2635 /* .. ==> 0XF8000754[1:1] = 0x00000001U */
2636 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
2637 /* .. L1_SEL = 0 */
2638 /* .. ==> 0XF8000754[2:2] = 0x00000000U */
2639 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
2640 /* .. L2_SEL = 0 */
2641 /* .. ==> 0XF8000754[4:3] = 0x00000000U */
2642 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
2643 /* .. L3_SEL = 0 */
2644 /* .. ==> 0XF8000754[7:5] = 0x00000000U */
2645 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
2646 /* .. Speed = 1 */
2647 /* .. ==> 0XF8000754[8:8] = 0x00000001U */
2648 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
2649 /* .. IO_Type = 4 */
2650 /* .. ==> 0XF8000754[11:9] = 0x00000004U */
2651 /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
2652 /* .. PULLUP = 0 */
2653 /* .. ==> 0XF8000754[12:12] = 0x00000000U */
2654 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
2655 /* .. DisableRcvr = 1 */
2656 /* .. ==> 0XF8000754[13:13] = 0x00000001U */
2657 /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
2658 /* .. */
2659 EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00002902U),
2660 /* .. TRI_ENABLE = 1 */
2661 /* .. ==> 0XF8000758[0:0] = 0x00000001U */
2662 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
2663 /* .. L0_SEL = 1 */
2664 /* .. ==> 0XF8000758[1:1] = 0x00000001U */
2665 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
2666 /* .. L1_SEL = 0 */
2667 /* .. ==> 0XF8000758[2:2] = 0x00000000U */
2668 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
2669 /* .. L2_SEL = 0 */
2670 /* .. ==> 0XF8000758[4:3] = 0x00000000U */
2671 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
2672 /* .. L3_SEL = 0 */
2673 /* .. ==> 0XF8000758[7:5] = 0x00000000U */
2674 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
2675 /* .. Speed = 1 */
2676 /* .. ==> 0XF8000758[8:8] = 0x00000001U */
2677 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
2678 /* .. IO_Type = 4 */
2679 /* .. ==> 0XF8000758[11:9] = 0x00000004U */
2680 /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
2681 /* .. PULLUP = 0 */
2682 /* .. ==> 0XF8000758[12:12] = 0x00000000U */
2683 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
2684 /* .. DisableRcvr = 0 */
2685 /* .. ==> 0XF8000758[13:13] = 0x00000000U */
2686 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
2687 /* .. */
2688 EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00000903U),
2689 /* .. TRI_ENABLE = 1 */
2690 /* .. ==> 0XF800075C[0:0] = 0x00000001U */
2691 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
2692 /* .. L0_SEL = 1 */
2693 /* .. ==> 0XF800075C[1:1] = 0x00000001U */
2694 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
2695 /* .. L1_SEL = 0 */
2696 /* .. ==> 0XF800075C[2:2] = 0x00000000U */
2697 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
2698 /* .. L2_SEL = 0 */
2699 /* .. ==> 0XF800075C[4:3] = 0x00000000U */
2700 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
2701 /* .. L3_SEL = 0 */
2702 /* .. ==> 0XF800075C[7:5] = 0x00000000U */
2703 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
2704 /* .. Speed = 1 */
2705 /* .. ==> 0XF800075C[8:8] = 0x00000001U */
2706 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
2707 /* .. IO_Type = 4 */
2708 /* .. ==> 0XF800075C[11:9] = 0x00000004U */
2709 /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
2710 /* .. PULLUP = 0 */
2711 /* .. ==> 0XF800075C[12:12] = 0x00000000U */
2712 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
2713 /* .. DisableRcvr = 0 */
2714 /* .. ==> 0XF800075C[13:13] = 0x00000000U */
2715 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
2716 /* .. */
2717 EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00000903U),
2718 /* .. TRI_ENABLE = 1 */
2719 /* .. ==> 0XF8000760[0:0] = 0x00000001U */
2720 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
2721 /* .. L0_SEL = 1 */
2722 /* .. ==> 0XF8000760[1:1] = 0x00000001U */
2723 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
2724 /* .. L1_SEL = 0 */
2725 /* .. ==> 0XF8000760[2:2] = 0x00000000U */
2726 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
2727 /* .. L2_SEL = 0 */
2728 /* .. ==> 0XF8000760[4:3] = 0x00000000U */
2729 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
2730 /* .. L3_SEL = 0 */
2731 /* .. ==> 0XF8000760[7:5] = 0x00000000U */
2732 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
2733 /* .. Speed = 1 */
2734 /* .. ==> 0XF8000760[8:8] = 0x00000001U */
2735 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
2736 /* .. IO_Type = 4 */
2737 /* .. ==> 0XF8000760[11:9] = 0x00000004U */
2738 /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
2739 /* .. PULLUP = 0 */
2740 /* .. ==> 0XF8000760[12:12] = 0x00000000U */
2741 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
2742 /* .. DisableRcvr = 0 */
2743 /* .. ==> 0XF8000760[13:13] = 0x00000000U */
2744 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
2745 /* .. */
2746 EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00000903U),
2747 /* .. TRI_ENABLE = 1 */
2748 /* .. ==> 0XF8000764[0:0] = 0x00000001U */
2749 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
2750 /* .. L0_SEL = 1 */
2751 /* .. ==> 0XF8000764[1:1] = 0x00000001U */
2752 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
2753 /* .. L1_SEL = 0 */
2754 /* .. ==> 0XF8000764[2:2] = 0x00000000U */
2755 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
2756 /* .. L2_SEL = 0 */
2757 /* .. ==> 0XF8000764[4:3] = 0x00000000U */
2758 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
2759 /* .. L3_SEL = 0 */
2760 /* .. ==> 0XF8000764[7:5] = 0x00000000U */
2761 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
2762 /* .. Speed = 1 */
2763 /* .. ==> 0XF8000764[8:8] = 0x00000001U */
2764 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
2765 /* .. IO_Type = 4 */
2766 /* .. ==> 0XF8000764[11:9] = 0x00000004U */
2767 /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
2768 /* .. PULLUP = 0 */
2769 /* .. ==> 0XF8000764[12:12] = 0x00000000U */
2770 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
2771 /* .. DisableRcvr = 0 */
2772 /* .. ==> 0XF8000764[13:13] = 0x00000000U */
2773 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
2774 /* .. */
2775 EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00000903U),
2776 /* .. TRI_ENABLE = 1 */
2777 /* .. ==> 0XF8000768[0:0] = 0x00000001U */
2778 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
2779 /* .. L0_SEL = 1 */
2780 /* .. ==> 0XF8000768[1:1] = 0x00000001U */
2781 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
2782 /* .. L1_SEL = 0 */
2783 /* .. ==> 0XF8000768[2:2] = 0x00000000U */
2784 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
2785 /* .. L2_SEL = 0 */
2786 /* .. ==> 0XF8000768[4:3] = 0x00000000U */
2787 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
2788 /* .. L3_SEL = 0 */
2789 /* .. ==> 0XF8000768[7:5] = 0x00000000U */
2790 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
2791 /* .. Speed = 1 */
2792 /* .. ==> 0XF8000768[8:8] = 0x00000001U */
2793 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
2794 /* .. IO_Type = 4 */
2795 /* .. ==> 0XF8000768[11:9] = 0x00000004U */
2796 /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
2797 /* .. PULLUP = 0 */
2798 /* .. ==> 0XF8000768[12:12] = 0x00000000U */
2799 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
2800 /* .. DisableRcvr = 0 */
2801 /* .. ==> 0XF8000768[13:13] = 0x00000000U */
2802 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
2803 /* .. */
2804 EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00000903U),
2805 /* .. TRI_ENABLE = 1 */
2806 /* .. ==> 0XF800076C[0:0] = 0x00000001U */
2807 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
2808 /* .. L0_SEL = 1 */
2809 /* .. ==> 0XF800076C[1:1] = 0x00000001U */
2810 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
2811 /* .. L1_SEL = 0 */
2812 /* .. ==> 0XF800076C[2:2] = 0x00000000U */
2813 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
2814 /* .. L2_SEL = 0 */
2815 /* .. ==> 0XF800076C[4:3] = 0x00000000U */
2816 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
2817 /* .. L3_SEL = 0 */
2818 /* .. ==> 0XF800076C[7:5] = 0x00000000U */
2819 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
2820 /* .. Speed = 1 */
2821 /* .. ==> 0XF800076C[8:8] = 0x00000001U */
2822 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
2823 /* .. IO_Type = 4 */
2824 /* .. ==> 0XF800076C[11:9] = 0x00000004U */
2825 /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
2826 /* .. PULLUP = 0 */
2827 /* .. ==> 0XF800076C[12:12] = 0x00000000U */
2828 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
2829 /* .. DisableRcvr = 0 */
2830 /* .. ==> 0XF800076C[13:13] = 0x00000000U */
2831 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
2832 /* .. */
2833 EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00000903U),
2834 /* .. TRI_ENABLE = 0 */
2835 /* .. ==> 0XF8000770[0:0] = 0x00000000U */
2836 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
2837 /* .. L0_SEL = 0 */
2838 /* .. ==> 0XF8000770[1:1] = 0x00000000U */
2839 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
2840 /* .. L1_SEL = 1 */
2841 /* .. ==> 0XF8000770[2:2] = 0x00000001U */
2842 /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
2843 /* .. L2_SEL = 0 */
2844 /* .. ==> 0XF8000770[4:3] = 0x00000000U */
2845 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
2846 /* .. L3_SEL = 0 */
2847 /* .. ==> 0XF8000770[7:5] = 0x00000000U */
2848 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
2849 /* .. Speed = 1 */
2850 /* .. ==> 0XF8000770[8:8] = 0x00000001U */
2851 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
2852 /* .. IO_Type = 1 */
2853 /* .. ==> 0XF8000770[11:9] = 0x00000001U */
2854 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
2855 /* .. PULLUP = 0 */
2856 /* .. ==> 0XF8000770[12:12] = 0x00000000U */
2857 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
2858 /* .. DisableRcvr = 0 */
2859 /* .. ==> 0XF8000770[13:13] = 0x00000000U */
2860 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
2861 /* .. */
2862 EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00000304U),
2863 /* .. TRI_ENABLE = 1 */
2864 /* .. ==> 0XF8000774[0:0] = 0x00000001U */
2865 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
2866 /* .. L0_SEL = 0 */
2867 /* .. ==> 0XF8000774[1:1] = 0x00000000U */
2868 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
2869 /* .. L1_SEL = 1 */
2870 /* .. ==> 0XF8000774[2:2] = 0x00000001U */
2871 /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
2872 /* .. L2_SEL = 0 */
2873 /* .. ==> 0XF8000774[4:3] = 0x00000000U */
2874 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
2875 /* .. L3_SEL = 0 */
2876 /* .. ==> 0XF8000774[7:5] = 0x00000000U */
2877 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
2878 /* .. Speed = 1 */
2879 /* .. ==> 0XF8000774[8:8] = 0x00000001U */
2880 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
2881 /* .. IO_Type = 1 */
2882 /* .. ==> 0XF8000774[11:9] = 0x00000001U */
2883 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
2884 /* .. PULLUP = 0 */
2885 /* .. ==> 0XF8000774[12:12] = 0x00000000U */
2886 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
2887 /* .. DisableRcvr = 0 */
2888 /* .. ==> 0XF8000774[13:13] = 0x00000000U */
2889 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
2890 /* .. */
2891 EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00000305U),
2892 /* .. TRI_ENABLE = 0 */
2893 /* .. ==> 0XF8000778[0:0] = 0x00000000U */
2894 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
2895 /* .. L0_SEL = 0 */
2896 /* .. ==> 0XF8000778[1:1] = 0x00000000U */
2897 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
2898 /* .. L1_SEL = 1 */
2899 /* .. ==> 0XF8000778[2:2] = 0x00000001U */
2900 /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
2901 /* .. L2_SEL = 0 */
2902 /* .. ==> 0XF8000778[4:3] = 0x00000000U */
2903 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
2904 /* .. L3_SEL = 0 */
2905 /* .. ==> 0XF8000778[7:5] = 0x00000000U */
2906 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
2907 /* .. Speed = 1 */
2908 /* .. ==> 0XF8000778[8:8] = 0x00000001U */
2909 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
2910 /* .. IO_Type = 1 */
2911 /* .. ==> 0XF8000778[11:9] = 0x00000001U */
2912 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
2913 /* .. PULLUP = 0 */
2914 /* .. ==> 0XF8000778[12:12] = 0x00000000U */
2915 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
2916 /* .. DisableRcvr = 0 */
2917 /* .. ==> 0XF8000778[13:13] = 0x00000000U */
2918 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
2919 /* .. */
2920 EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00000304U),
2921 /* .. TRI_ENABLE = 1 */
2922 /* .. ==> 0XF800077C[0:0] = 0x00000001U */
2923 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
2924 /* .. L0_SEL = 0 */
2925 /* .. ==> 0XF800077C[1:1] = 0x00000000U */
2926 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
2927 /* .. L1_SEL = 1 */
2928 /* .. ==> 0XF800077C[2:2] = 0x00000001U */
2929 /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
2930 /* .. L2_SEL = 0 */
2931 /* .. ==> 0XF800077C[4:3] = 0x00000000U */
2932 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
2933 /* .. L3_SEL = 0 */
2934 /* .. ==> 0XF800077C[7:5] = 0x00000000U */
2935 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
2936 /* .. Speed = 1 */
2937 /* .. ==> 0XF800077C[8:8] = 0x00000001U */
2938 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
2939 /* .. IO_Type = 1 */
2940 /* .. ==> 0XF800077C[11:9] = 0x00000001U */
2941 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
2942 /* .. PULLUP = 0 */
2943 /* .. ==> 0XF800077C[12:12] = 0x00000000U */
2944 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
2945 /* .. DisableRcvr = 0 */
2946 /* .. ==> 0XF800077C[13:13] = 0x00000000U */
2947 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
2948 /* .. */
2949 EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00000305U),
2950 /* .. TRI_ENABLE = 0 */
2951 /* .. ==> 0XF8000780[0:0] = 0x00000000U */
2952 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
2953 /* .. L0_SEL = 0 */
2954 /* .. ==> 0XF8000780[1:1] = 0x00000000U */
2955 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
2956 /* .. L1_SEL = 1 */
2957 /* .. ==> 0XF8000780[2:2] = 0x00000001U */
2958 /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
2959 /* .. L2_SEL = 0 */
2960 /* .. ==> 0XF8000780[4:3] = 0x00000000U */
2961 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
2962 /* .. L3_SEL = 0 */
2963 /* .. ==> 0XF8000780[7:5] = 0x00000000U */
2964 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
2965 /* .. Speed = 1 */
2966 /* .. ==> 0XF8000780[8:8] = 0x00000001U */
2967 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
2968 /* .. IO_Type = 1 */
2969 /* .. ==> 0XF8000780[11:9] = 0x00000001U */
2970 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
2971 /* .. PULLUP = 0 */
2972 /* .. ==> 0XF8000780[12:12] = 0x00000000U */
2973 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
2974 /* .. DisableRcvr = 0 */
2975 /* .. ==> 0XF8000780[13:13] = 0x00000000U */
2976 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
2977 /* .. */
2978 EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00000304U),
2979 /* .. TRI_ENABLE = 0 */
2980 /* .. ==> 0XF8000784[0:0] = 0x00000000U */
2981 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
2982 /* .. L0_SEL = 0 */
2983 /* .. ==> 0XF8000784[1:1] = 0x00000000U */
2984 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
2985 /* .. L1_SEL = 1 */
2986 /* .. ==> 0XF8000784[2:2] = 0x00000001U */
2987 /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
2988 /* .. L2_SEL = 0 */
2989 /* .. ==> 0XF8000784[4:3] = 0x00000000U */
2990 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
2991 /* .. L3_SEL = 0 */
2992 /* .. ==> 0XF8000784[7:5] = 0x00000000U */
2993 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
2994 /* .. Speed = 1 */
2995 /* .. ==> 0XF8000784[8:8] = 0x00000001U */
2996 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
2997 /* .. IO_Type = 1 */
2998 /* .. ==> 0XF8000784[11:9] = 0x00000001U */
2999 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
3000 /* .. PULLUP = 0 */
3001 /* .. ==> 0XF8000784[12:12] = 0x00000000U */
3002 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
3003 /* .. DisableRcvr = 0 */
3004 /* .. ==> 0XF8000784[13:13] = 0x00000000U */
3005 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
3006 /* .. */
3007 EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00000304U),
3008 /* .. TRI_ENABLE = 0 */
3009 /* .. ==> 0XF8000788[0:0] = 0x00000000U */
3010 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
3011 /* .. L0_SEL = 0 */
3012 /* .. ==> 0XF8000788[1:1] = 0x00000000U */
3013 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
3014 /* .. L1_SEL = 1 */
3015 /* .. ==> 0XF8000788[2:2] = 0x00000001U */
3016 /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
3017 /* .. L2_SEL = 0 */
3018 /* .. ==> 0XF8000788[4:3] = 0x00000000U */
3019 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
3020 /* .. L3_SEL = 0 */
3021 /* .. ==> 0XF8000788[7:5] = 0x00000000U */
3022 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
3023 /* .. Speed = 1 */
3024 /* .. ==> 0XF8000788[8:8] = 0x00000001U */
3025 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
3026 /* .. IO_Type = 1 */
3027 /* .. ==> 0XF8000788[11:9] = 0x00000001U */
3028 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
3029 /* .. PULLUP = 0 */
3030 /* .. ==> 0XF8000788[12:12] = 0x00000000U */
3031 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
3032 /* .. DisableRcvr = 0 */
3033 /* .. ==> 0XF8000788[13:13] = 0x00000000U */
3034 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
3035 /* .. */
3036 EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00000304U),
3037 /* .. TRI_ENABLE = 0 */
3038 /* .. ==> 0XF800078C[0:0] = 0x00000000U */
3039 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
3040 /* .. L0_SEL = 0 */
3041 /* .. ==> 0XF800078C[1:1] = 0x00000000U */
3042 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
3043 /* .. L1_SEL = 1 */
3044 /* .. ==> 0XF800078C[2:2] = 0x00000001U */
3045 /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
3046 /* .. L2_SEL = 0 */
3047 /* .. ==> 0XF800078C[4:3] = 0x00000000U */
3048 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
3049 /* .. L3_SEL = 0 */
3050 /* .. ==> 0XF800078C[7:5] = 0x00000000U */
3051 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
3052 /* .. Speed = 1 */
3053 /* .. ==> 0XF800078C[8:8] = 0x00000001U */
3054 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
3055 /* .. IO_Type = 1 */
3056 /* .. ==> 0XF800078C[11:9] = 0x00000001U */
3057 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
3058 /* .. PULLUP = 0 */
3059 /* .. ==> 0XF800078C[12:12] = 0x00000000U */
3060 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
3061 /* .. DisableRcvr = 0 */
3062 /* .. ==> 0XF800078C[13:13] = 0x00000000U */
3063 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
3064 /* .. */
3065 EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00000304U),
3066 /* .. TRI_ENABLE = 1 */
3067 /* .. ==> 0XF8000790[0:0] = 0x00000001U */
3068 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
3069 /* .. L0_SEL = 0 */
3070 /* .. ==> 0XF8000790[1:1] = 0x00000000U */
3071 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
3072 /* .. L1_SEL = 1 */
3073 /* .. ==> 0XF8000790[2:2] = 0x00000001U */
3074 /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
3075 /* .. L2_SEL = 0 */
3076 /* .. ==> 0XF8000790[4:3] = 0x00000000U */
3077 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
3078 /* .. L3_SEL = 0 */
3079 /* .. ==> 0XF8000790[7:5] = 0x00000000U */
3080 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
3081 /* .. Speed = 1 */
3082 /* .. ==> 0XF8000790[8:8] = 0x00000001U */
3083 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
3084 /* .. IO_Type = 1 */
3085 /* .. ==> 0XF8000790[11:9] = 0x00000001U */
3086 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
3087 /* .. PULLUP = 0 */
3088 /* .. ==> 0XF8000790[12:12] = 0x00000000U */
3089 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
3090 /* .. DisableRcvr = 0 */
3091 /* .. ==> 0XF8000790[13:13] = 0x00000000U */
3092 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
3093 /* .. */
3094 EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00000305U),
3095 /* .. TRI_ENABLE = 0 */
3096 /* .. ==> 0XF8000794[0:0] = 0x00000000U */
3097 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
3098 /* .. L0_SEL = 0 */
3099 /* .. ==> 0XF8000794[1:1] = 0x00000000U */
3100 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
3101 /* .. L1_SEL = 1 */
3102 /* .. ==> 0XF8000794[2:2] = 0x00000001U */
3103 /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
3104 /* .. L2_SEL = 0 */
3105 /* .. ==> 0XF8000794[4:3] = 0x00000000U */
3106 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
3107 /* .. L3_SEL = 0 */
3108 /* .. ==> 0XF8000794[7:5] = 0x00000000U */
3109 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
3110 /* .. Speed = 1 */
3111 /* .. ==> 0XF8000794[8:8] = 0x00000001U */
3112 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
3113 /* .. IO_Type = 1 */
3114 /* .. ==> 0XF8000794[11:9] = 0x00000001U */
3115 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
3116 /* .. PULLUP = 0 */
3117 /* .. ==> 0XF8000794[12:12] = 0x00000000U */
3118 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
3119 /* .. DisableRcvr = 0 */
3120 /* .. ==> 0XF8000794[13:13] = 0x00000000U */
3121 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
3122 /* .. */
3123 EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00000304U),
3124 /* .. TRI_ENABLE = 0 */
3125 /* .. ==> 0XF8000798[0:0] = 0x00000000U */
3126 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
3127 /* .. L0_SEL = 0 */
3128 /* .. ==> 0XF8000798[1:1] = 0x00000000U */
3129 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
3130 /* .. L1_SEL = 1 */
3131 /* .. ==> 0XF8000798[2:2] = 0x00000001U */
3132 /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
3133 /* .. L2_SEL = 0 */
3134 /* .. ==> 0XF8000798[4:3] = 0x00000000U */
3135 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
3136 /* .. L3_SEL = 0 */
3137 /* .. ==> 0XF8000798[7:5] = 0x00000000U */
3138 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
3139 /* .. Speed = 1 */
3140 /* .. ==> 0XF8000798[8:8] = 0x00000001U */
3141 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
3142 /* .. IO_Type = 1 */
3143 /* .. ==> 0XF8000798[11:9] = 0x00000001U */
3144 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
3145 /* .. PULLUP = 0 */
3146 /* .. ==> 0XF8000798[12:12] = 0x00000000U */
3147 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
3148 /* .. DisableRcvr = 0 */
3149 /* .. ==> 0XF8000798[13:13] = 0x00000000U */
3150 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
3151 /* .. */
3152 EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00000304U),
3153 /* .. TRI_ENABLE = 0 */
3154 /* .. ==> 0XF800079C[0:0] = 0x00000000U */
3155 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
3156 /* .. L0_SEL = 0 */
3157 /* .. ==> 0XF800079C[1:1] = 0x00000000U */
3158 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
3159 /* .. L1_SEL = 1 */
3160 /* .. ==> 0XF800079C[2:2] = 0x00000001U */
3161 /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
3162 /* .. L2_SEL = 0 */
3163 /* .. ==> 0XF800079C[4:3] = 0x00000000U */
3164 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
3165 /* .. L3_SEL = 0 */
3166 /* .. ==> 0XF800079C[7:5] = 0x00000000U */
3167 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
3168 /* .. Speed = 1 */
3169 /* .. ==> 0XF800079C[8:8] = 0x00000001U */
3170 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
3171 /* .. IO_Type = 1 */
3172 /* .. ==> 0XF800079C[11:9] = 0x00000001U */
3173 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
3174 /* .. PULLUP = 0 */
3175 /* .. ==> 0XF800079C[12:12] = 0x00000000U */
3176 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
3177 /* .. DisableRcvr = 0 */
3178 /* .. ==> 0XF800079C[13:13] = 0x00000000U */
3179 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
3180 /* .. */
3181 EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00000304U),
3182 /* .. TRI_ENABLE = 0 */
3183 /* .. ==> 0XF80007A0[0:0] = 0x00000000U */
3184 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
3185 /* .. L0_SEL = 0 */
3186 /* .. ==> 0XF80007A0[1:1] = 0x00000000U */
3187 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
3188 /* .. L1_SEL = 0 */
3189 /* .. ==> 0XF80007A0[2:2] = 0x00000000U */
3190 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
3191 /* .. L2_SEL = 0 */
3192 /* .. ==> 0XF80007A0[4:3] = 0x00000000U */
3193 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
3194 /* .. L3_SEL = 4 */
3195 /* .. ==> 0XF80007A0[7:5] = 0x00000004U */
3196 /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
3197 /* .. Speed = 1 */
3198 /* .. ==> 0XF80007A0[8:8] = 0x00000001U */
3199 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
3200 /* .. IO_Type = 1 */
3201 /* .. ==> 0XF80007A0[11:9] = 0x00000001U */
3202 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
3203 /* .. PULLUP = 0 */
3204 /* .. ==> 0XF80007A0[12:12] = 0x00000000U */
3205 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
3206 /* .. DisableRcvr = 0 */
3207 /* .. ==> 0XF80007A0[13:13] = 0x00000000U */
3208 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
3209 /* .. */
3210 EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00000380U),
3211 /* .. TRI_ENABLE = 0 */
3212 /* .. ==> 0XF80007A4[0:0] = 0x00000000U */
3213 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
3214 /* .. L0_SEL = 0 */
3215 /* .. ==> 0XF80007A4[1:1] = 0x00000000U */
3216 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
3217 /* .. L1_SEL = 0 */
3218 /* .. ==> 0XF80007A4[2:2] = 0x00000000U */
3219 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
3220 /* .. L2_SEL = 0 */
3221 /* .. ==> 0XF80007A4[4:3] = 0x00000000U */
3222 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
3223 /* .. L3_SEL = 4 */
3224 /* .. ==> 0XF80007A4[7:5] = 0x00000004U */
3225 /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
3226 /* .. Speed = 1 */
3227 /* .. ==> 0XF80007A4[8:8] = 0x00000001U */
3228 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
3229 /* .. IO_Type = 1 */
3230 /* .. ==> 0XF80007A4[11:9] = 0x00000001U */
3231 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
3232 /* .. PULLUP = 0 */
3233 /* .. ==> 0XF80007A4[12:12] = 0x00000000U */
3234 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
3235 /* .. DisableRcvr = 0 */
3236 /* .. ==> 0XF80007A4[13:13] = 0x00000000U */
3237 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
3238 /* .. */
3239 EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00000380U),
3240 /* .. TRI_ENABLE = 0 */
3241 /* .. ==> 0XF80007A8[0:0] = 0x00000000U */
3242 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
3243 /* .. L0_SEL = 0 */
3244 /* .. ==> 0XF80007A8[1:1] = 0x00000000U */
3245 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
3246 /* .. L1_SEL = 0 */
3247 /* .. ==> 0XF80007A8[2:2] = 0x00000000U */
3248 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
3249 /* .. L2_SEL = 0 */
3250 /* .. ==> 0XF80007A8[4:3] = 0x00000000U */
3251 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
3252 /* .. L3_SEL = 4 */
3253 /* .. ==> 0XF80007A8[7:5] = 0x00000004U */
3254 /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
3255 /* .. Speed = 1 */
3256 /* .. ==> 0XF80007A8[8:8] = 0x00000001U */
3257 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
3258 /* .. IO_Type = 1 */
3259 /* .. ==> 0XF80007A8[11:9] = 0x00000001U */
3260 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
3261 /* .. PULLUP = 0 */
3262 /* .. ==> 0XF80007A8[12:12] = 0x00000000U */
3263 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
3264 /* .. DisableRcvr = 0 */
3265 /* .. ==> 0XF80007A8[13:13] = 0x00000000U */
3266 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
3267 /* .. */
3268 EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00000380U),
3269 /* .. TRI_ENABLE = 0 */
3270 /* .. ==> 0XF80007AC[0:0] = 0x00000000U */
3271 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
3272 /* .. L0_SEL = 0 */
3273 /* .. ==> 0XF80007AC[1:1] = 0x00000000U */
3274 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
3275 /* .. L1_SEL = 0 */
3276 /* .. ==> 0XF80007AC[2:2] = 0x00000000U */
3277 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
3278 /* .. L2_SEL = 0 */
3279 /* .. ==> 0XF80007AC[4:3] = 0x00000000U */
3280 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
3281 /* .. L3_SEL = 4 */
3282 /* .. ==> 0XF80007AC[7:5] = 0x00000004U */
3283 /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
3284 /* .. Speed = 1 */
3285 /* .. ==> 0XF80007AC[8:8] = 0x00000001U */
3286 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
3287 /* .. IO_Type = 1 */
3288 /* .. ==> 0XF80007AC[11:9] = 0x00000001U */
3289 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
3290 /* .. PULLUP = 0 */
3291 /* .. ==> 0XF80007AC[12:12] = 0x00000000U */
3292 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
3293 /* .. DisableRcvr = 0 */
3294 /* .. ==> 0XF80007AC[13:13] = 0x00000000U */
3295 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
3296 /* .. */
3297 EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00000380U),
3298 /* .. TRI_ENABLE = 0 */
3299 /* .. ==> 0XF80007B0[0:0] = 0x00000000U */
3300 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
3301 /* .. L0_SEL = 0 */
3302 /* .. ==> 0XF80007B0[1:1] = 0x00000000U */
3303 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
3304 /* .. L1_SEL = 0 */
3305 /* .. ==> 0XF80007B0[2:2] = 0x00000000U */
3306 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
3307 /* .. L2_SEL = 0 */
3308 /* .. ==> 0XF80007B0[4:3] = 0x00000000U */
3309 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
3310 /* .. L3_SEL = 4 */
3311 /* .. ==> 0XF80007B0[7:5] = 0x00000004U */
3312 /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
3313 /* .. Speed = 1 */
3314 /* .. ==> 0XF80007B0[8:8] = 0x00000001U */
3315 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
3316 /* .. IO_Type = 1 */
3317 /* .. ==> 0XF80007B0[11:9] = 0x00000001U */
3318 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
3319 /* .. PULLUP = 0 */
3320 /* .. ==> 0XF80007B0[12:12] = 0x00000000U */
3321 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
3322 /* .. DisableRcvr = 0 */
3323 /* .. ==> 0XF80007B0[13:13] = 0x00000000U */
3324 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
3325 /* .. */
3326 EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00000380U),
3327 /* .. TRI_ENABLE = 0 */
3328 /* .. ==> 0XF80007B4[0:0] = 0x00000000U */
3329 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
3330 /* .. L0_SEL = 0 */
3331 /* .. ==> 0XF80007B4[1:1] = 0x00000000U */
3332 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
3333 /* .. L1_SEL = 0 */
3334 /* .. ==> 0XF80007B4[2:2] = 0x00000000U */
3335 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
3336 /* .. L2_SEL = 0 */
3337 /* .. ==> 0XF80007B4[4:3] = 0x00000000U */
3338 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
3339 /* .. L3_SEL = 4 */
3340 /* .. ==> 0XF80007B4[7:5] = 0x00000004U */
3341 /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
3342 /* .. Speed = 1 */
3343 /* .. ==> 0XF80007B4[8:8] = 0x00000001U */
3344 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
3345 /* .. IO_Type = 1 */
3346 /* .. ==> 0XF80007B4[11:9] = 0x00000001U */
3347 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
3348 /* .. PULLUP = 0 */
3349 /* .. ==> 0XF80007B4[12:12] = 0x00000000U */
3350 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
3351 /* .. DisableRcvr = 0 */
3352 /* .. ==> 0XF80007B4[13:13] = 0x00000000U */
3353 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
3354 /* .. */
3355 EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00000380U),
Michal Simek264065f2016-03-03 13:25:03 +0100[diff] [blame]3356 /* .. TRI_ENABLE = 0 */
3357 /* .. ==> 0XF80007B8[0:0] = 0x00000000U */
3358 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
3359 /* .. L0_SEL = 0 */
3360 /* .. ==> 0XF80007B8[1:1] = 0x00000000U */
3361 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
3362 /* .. L1_SEL = 0 */
3363 /* .. ==> 0XF80007B8[2:2] = 0x00000000U */
3364 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
3365 /* .. L2_SEL = 0 */
3366 /* .. ==> 0XF80007B8[4:3] = 0x00000000U */
3367 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
3368 /* .. L3_SEL = 0 */
3369 /* .. ==> 0XF80007B8[7:5] = 0x00000000U */
3370 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
3371 /* .. Speed = 0 */
3372 /* .. ==> 0XF80007B8[8:8] = 0x00000000U */
3373 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
3374 /* .. IO_Type = 1 */
3375 /* .. ==> 0XF80007B8[11:9] = 0x00000001U */
3376 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
3377 /* .. PULLUP = 1 */
3378 /* .. ==> 0XF80007B8[12:12] = 0x00000001U */
3379 /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
3380 /* .. DisableRcvr = 0 */
3381 /* .. ==> 0XF80007B8[13:13] = 0x00000000U */
3382 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
3383 /* .. */
3384 EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00001200U),
Nathan Rossi4eeed0e2015-11-24 19:34:09 +1000[diff] [blame]3385 /* .. TRI_ENABLE = 1 */
3386 /* .. ==> 0XF80007BC[0:0] = 0x00000001U */
3387 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
3388 /* .. Speed = 0 */
3389 /* .. ==> 0XF80007BC[8:8] = 0x00000000U */
3390 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
3391 /* .. IO_Type = 1 */
3392 /* .. ==> 0XF80007BC[11:9] = 0x00000001U */
3393 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
3394 /* .. PULLUP = 0 */
3395 /* .. ==> 0XF80007BC[12:12] = 0x00000000U */
3396 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
3397 /* .. DisableRcvr = 0 */
3398 /* .. ==> 0XF80007BC[13:13] = 0x00000000U */
3399 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
3400 /* .. */
3401 EMIT_MASKWRITE(0XF80007BC, 0x00003F01U, 0x00000201U),
3402 /* .. TRI_ENABLE = 0 */
3403 /* .. ==> 0XF80007C0[0:0] = 0x00000000U */
3404 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
3405 /* .. L0_SEL = 0 */
3406 /* .. ==> 0XF80007C0[1:1] = 0x00000000U */
3407 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
3408 /* .. L1_SEL = 0 */
3409 /* .. ==> 0XF80007C0[2:2] = 0x00000000U */
3410 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
3411 /* .. L2_SEL = 0 */
3412 /* .. ==> 0XF80007C0[4:3] = 0x00000000U */
3413 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
3414 /* .. L3_SEL = 7 */
3415 /* .. ==> 0XF80007C0[7:5] = 0x00000007U */
3416 /* .. ==> MASK : 0x000000E0U VAL : 0x000000E0U */
3417 /* .. Speed = 0 */
3418 /* .. ==> 0XF80007C0[8:8] = 0x00000000U */
3419 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
3420 /* .. IO_Type = 1 */
3421 /* .. ==> 0XF80007C0[11:9] = 0x00000001U */
3422 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
3423 /* .. PULLUP = 0 */
3424 /* .. ==> 0XF80007C0[12:12] = 0x00000000U */
3425 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
3426 /* .. DisableRcvr = 0 */
3427 /* .. ==> 0XF80007C0[13:13] = 0x00000000U */
3428 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
3429 /* .. */
3430 EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x000002E0U),
3431 /* .. TRI_ENABLE = 1 */
3432 /* .. ==> 0XF80007C4[0:0] = 0x00000001U */
3433 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
3434 /* .. L0_SEL = 0 */
3435 /* .. ==> 0XF80007C4[1:1] = 0x00000000U */
3436 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
3437 /* .. L1_SEL = 0 */
3438 /* .. ==> 0XF80007C4[2:2] = 0x00000000U */
3439 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
3440 /* .. L2_SEL = 0 */
3441 /* .. ==> 0XF80007C4[4:3] = 0x00000000U */
3442 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
3443 /* .. L3_SEL = 7 */
3444 /* .. ==> 0XF80007C4[7:5] = 0x00000007U */
3445 /* .. ==> MASK : 0x000000E0U VAL : 0x000000E0U */
3446 /* .. Speed = 0 */
3447 /* .. ==> 0XF80007C4[8:8] = 0x00000000U */
3448 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
3449 /* .. IO_Type = 1 */
3450 /* .. ==> 0XF80007C4[11:9] = 0x00000001U */
3451 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
3452 /* .. PULLUP = 0 */
3453 /* .. ==> 0XF80007C4[12:12] = 0x00000000U */
3454 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
3455 /* .. DisableRcvr = 0 */
3456 /* .. ==> 0XF80007C4[13:13] = 0x00000000U */
3457 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
3458 /* .. */
3459 EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x000002E1U),
3460 /* .. TRI_ENABLE = 0 */
Michal Simek264065f2016-03-03 13:25:03 +0100[diff] [blame]3461 /* .. ==> 0XF80007C8[0:0] = 0x00000000U */
3462 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
3463 /* .. L0_SEL = 0 */
3464 /* .. ==> 0XF80007C8[1:1] = 0x00000000U */
3465 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
3466 /* .. L1_SEL = 0 */
3467 /* .. ==> 0XF80007C8[2:2] = 0x00000000U */
3468 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
3469 /* .. L2_SEL = 0 */
3470 /* .. ==> 0XF80007C8[4:3] = 0x00000000U */
3471 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
3472 /* .. L3_SEL = 0 */
3473 /* .. ==> 0XF80007C8[7:5] = 0x00000000U */
3474 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
3475 /* .. Speed = 0 */
3476 /* .. ==> 0XF80007C8[8:8] = 0x00000000U */
3477 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
3478 /* .. IO_Type = 1 */
3479 /* .. ==> 0XF80007C8[11:9] = 0x00000001U */
3480 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
3481 /* .. PULLUP = 0 */
3482 /* .. ==> 0XF80007C8[12:12] = 0x00000000U */
3483 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
3484 /* .. DisableRcvr = 0 */
3485 /* .. ==> 0XF80007C8[13:13] = 0x00000000U */
3486 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
3487 /* .. */
3488 EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x00000200U),
3489 /* .. TRI_ENABLE = 0 */
3490 /* .. ==> 0XF80007CC[0:0] = 0x00000000U */
3491 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
3492 /* .. L0_SEL = 0 */
3493 /* .. ==> 0XF80007CC[1:1] = 0x00000000U */
3494 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
3495 /* .. L1_SEL = 0 */
3496 /* .. ==> 0XF80007CC[2:2] = 0x00000000U */
3497 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
3498 /* .. L2_SEL = 0 */
3499 /* .. ==> 0XF80007CC[4:3] = 0x00000000U */
3500 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
3501 /* .. L3_SEL = 0 */
3502 /* .. ==> 0XF80007CC[7:5] = 0x00000000U */
3503 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
3504 /* .. Speed = 0 */
3505 /* .. ==> 0XF80007CC[8:8] = 0x00000000U */
3506 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
3507 /* .. IO_Type = 1 */
3508 /* .. ==> 0XF80007CC[11:9] = 0x00000001U */
3509 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
3510 /* .. PULLUP = 0 */
3511 /* .. ==> 0XF80007CC[12:12] = 0x00000000U */
3512 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
3513 /* .. DisableRcvr = 0 */
3514 /* .. ==> 0XF80007CC[13:13] = 0x00000000U */
3515 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
3516 /* .. */
3517 EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x00000200U),
3518 /* .. TRI_ENABLE = 0 */
Nathan Rossi4eeed0e2015-11-24 19:34:09 +1000[diff] [blame]3519 /* .. ==> 0XF80007D0[0:0] = 0x00000000U */
3520 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
3521 /* .. L0_SEL = 0 */
3522 /* .. ==> 0XF80007D0[1:1] = 0x00000000U */
3523 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
3524 /* .. L1_SEL = 0 */
3525 /* .. ==> 0XF80007D0[2:2] = 0x00000000U */
3526 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
3527 /* .. L2_SEL = 0 */
3528 /* .. ==> 0XF80007D0[4:3] = 0x00000000U */
3529 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
3530 /* .. L3_SEL = 4 */
3531 /* .. ==> 0XF80007D0[7:5] = 0x00000004U */
3532 /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
3533 /* .. Speed = 0 */
3534 /* .. ==> 0XF80007D0[8:8] = 0x00000000U */
3535 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
3536 /* .. IO_Type = 1 */
3537 /* .. ==> 0XF80007D0[11:9] = 0x00000001U */
3538 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
3539 /* .. PULLUP = 0 */
3540 /* .. ==> 0XF80007D0[12:12] = 0x00000000U */
3541 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
3542 /* .. DisableRcvr = 0 */
3543 /* .. ==> 0XF80007D0[13:13] = 0x00000000U */
3544 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
3545 /* .. */
3546 EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00000280U),
3547 /* .. TRI_ENABLE = 0 */
3548 /* .. ==> 0XF80007D4[0:0] = 0x00000000U */
3549 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
3550 /* .. L0_SEL = 0 */
3551 /* .. ==> 0XF80007D4[1:1] = 0x00000000U */
3552 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
3553 /* .. L1_SEL = 0 */
3554 /* .. ==> 0XF80007D4[2:2] = 0x00000000U */
3555 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
3556 /* .. L2_SEL = 0 */
3557 /* .. ==> 0XF80007D4[4:3] = 0x00000000U */
3558 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
3559 /* .. L3_SEL = 4 */
3560 /* .. ==> 0XF80007D4[7:5] = 0x00000004U */
3561 /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
3562 /* .. Speed = 0 */
3563 /* .. ==> 0XF80007D4[8:8] = 0x00000000U */
3564 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
3565 /* .. IO_Type = 1 */
3566 /* .. ==> 0XF80007D4[11:9] = 0x00000001U */
3567 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
3568 /* .. PULLUP = 0 */
3569 /* .. ==> 0XF80007D4[12:12] = 0x00000000U */
3570 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
3571 /* .. DisableRcvr = 0 */
3572 /* .. ==> 0XF80007D4[13:13] = 0x00000000U */
3573 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
3574 /* .. */
3575 EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00000280U),
3576 /* .. SDIO0_WP_SEL = 55 */
3577 /* .. ==> 0XF8000830[5:0] = 0x00000037U */
3578 /* .. ==> MASK : 0x0000003FU VAL : 0x00000037U */
3579 /* .. SDIO0_CD_SEL = 47 */
3580 /* .. ==> 0XF8000830[21:16] = 0x0000002FU */
3581 /* .. ==> MASK : 0x003F0000U VAL : 0x002F0000U */
3582 /* .. */
3583 EMIT_MASKWRITE(0XF8000830, 0x003F003FU, 0x002F0037U),
3584 /* .. FINISH: MIO PROGRAMMING */
3585 /* .. START: LOCK IT BACK */
3586 /* .. LOCK_KEY = 0X767B */
3587 /* .. ==> 0XF8000004[15:0] = 0x0000767BU */
3588 /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */
3589 /* .. */
3590 EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
3591 /* .. FINISH: LOCK IT BACK */
3592 /* FINISH: top */
3593 /* */
3594 EMIT_EXIT(),
3595
3596 /* */
3597};
3598
3599unsigned long ps7_peripherals_init_data_3_0[] = {
3600 /* START: top */
3601 /* .. START: SLCR SETTINGS */
3602 /* .. UNLOCK_KEY = 0XDF0D */
3603 /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
3604 /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */
3605 /* .. */
3606 EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
3607 /* .. FINISH: SLCR SETTINGS */
3608 /* .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS */
3609 /* .. IBUF_DISABLE_MODE = 0x1 */
3610 /* .. ==> 0XF8000B48[7:7] = 0x00000001U */
3611 /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */
3612 /* .. TERM_DISABLE_MODE = 0x1 */
3613 /* .. ==> 0XF8000B48[8:8] = 0x00000001U */
3614 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
3615 /* .. */
3616 EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U),
3617 /* .. IBUF_DISABLE_MODE = 0x1 */
3618 /* .. ==> 0XF8000B4C[7:7] = 0x00000001U */
3619 /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */
3620 /* .. TERM_DISABLE_MODE = 0x1 */
3621 /* .. ==> 0XF8000B4C[8:8] = 0x00000001U */
3622 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
3623 /* .. */
3624 EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U),
3625 /* .. IBUF_DISABLE_MODE = 0x1 */
3626 /* .. ==> 0XF8000B50[7:7] = 0x00000001U */
3627 /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */
3628 /* .. TERM_DISABLE_MODE = 0x1 */
3629 /* .. ==> 0XF8000B50[8:8] = 0x00000001U */
3630 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
3631 /* .. */
3632 EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
3633 /* .. IBUF_DISABLE_MODE = 0x1 */
3634 /* .. ==> 0XF8000B54[7:7] = 0x00000001U */
3635 /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */
3636 /* .. TERM_DISABLE_MODE = 0x1 */
3637 /* .. ==> 0XF8000B54[8:8] = 0x00000001U */
3638 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
3639 /* .. */
3640 EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
3641 /* .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS */
3642 /* .. START: LOCK IT BACK */
3643 /* .. LOCK_KEY = 0X767B */
3644 /* .. ==> 0XF8000004[15:0] = 0x0000767BU */
3645 /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */
3646 /* .. */
3647 EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
3648 /* .. FINISH: LOCK IT BACK */
3649 /* .. START: SRAM/NOR SET OPMODE */
3650 /* .. FINISH: SRAM/NOR SET OPMODE */
3651 /* .. START: UART REGISTERS */
3652 /* .. BDIV = 0x6 */
3653 /* .. ==> 0XE0001034[7:0] = 0x00000006U */
3654 /* .. ==> MASK : 0x000000FFU VAL : 0x00000006U */
3655 /* .. */
3656 EMIT_MASKWRITE(0XE0001034, 0x000000FFU, 0x00000006U),
Michal Simek264065f2016-03-03 13:25:03 +0100[diff] [blame]3657 /* .. CD = 0x7c */
3658 /* .. ==> 0XE0001018[15:0] = 0x0000007CU */
3659 /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU */
Nathan Rossi4eeed0e2015-11-24 19:34:09 +1000[diff] [blame]3660 /* .. */
Michal Simek264065f2016-03-03 13:25:03 +0100[diff] [blame]3661 EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000007CU),
Nathan Rossi4eeed0e2015-11-24 19:34:09 +1000[diff] [blame]3662 /* .. STPBRK = 0x0 */
3663 /* .. ==> 0XE0001000[8:8] = 0x00000000U */
3664 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
3665 /* .. STTBRK = 0x0 */
3666 /* .. ==> 0XE0001000[7:7] = 0x00000000U */
3667 /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
3668 /* .. RSTTO = 0x0 */
3669 /* .. ==> 0XE0001000[6:6] = 0x00000000U */
3670 /* .. ==> MASK : 0x00000040U VAL : 0x00000000U */
3671 /* .. TXDIS = 0x0 */
3672 /* .. ==> 0XE0001000[5:5] = 0x00000000U */
3673 /* .. ==> MASK : 0x00000020U VAL : 0x00000000U */
3674 /* .. TXEN = 0x1 */
3675 /* .. ==> 0XE0001000[4:4] = 0x00000001U */
3676 /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */
3677 /* .. RXDIS = 0x0 */
3678 /* .. ==> 0XE0001000[3:3] = 0x00000000U */
3679 /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
3680 /* .. RXEN = 0x1 */
3681 /* .. ==> 0XE0001000[2:2] = 0x00000001U */
3682 /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
3683 /* .. TXRES = 0x1 */
3684 /* .. ==> 0XE0001000[1:1] = 0x00000001U */
3685 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
3686 /* .. RXRES = 0x1 */
3687 /* .. ==> 0XE0001000[0:0] = 0x00000001U */
3688 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
3689 /* .. */
3690 EMIT_MASKWRITE(0XE0001000, 0x000001FFU, 0x00000017U),
3691 /* .. CHMODE = 0x0 */
3692 /* .. ==> 0XE0001004[9:8] = 0x00000000U */
3693 /* .. ==> MASK : 0x00000300U VAL : 0x00000000U */
3694 /* .. NBSTOP = 0x0 */
3695 /* .. ==> 0XE0001004[7:6] = 0x00000000U */
3696 /* .. ==> MASK : 0x000000C0U VAL : 0x00000000U */
3697 /* .. PAR = 0x4 */
3698 /* .. ==> 0XE0001004[5:3] = 0x00000004U */
3699 /* .. ==> MASK : 0x00000038U VAL : 0x00000020U */
3700 /* .. CHRL = 0x0 */
3701 /* .. ==> 0XE0001004[2:1] = 0x00000000U */
3702 /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */
3703 /* .. CLKS = 0x0 */
3704 /* .. ==> 0XE0001004[0:0] = 0x00000000U */
3705 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
3706 /* .. */
3707 EMIT_MASKWRITE(0XE0001004, 0x000003FFU, 0x00000020U),
3708 /* .. FINISH: UART REGISTERS */
Nathan Rossi4eeed0e2015-11-24 19:34:09 +1000[diff] [blame]3709 /* .. START: QSPI REGISTERS */
3710 /* .. Holdb_dr = 1 */
3711 /* .. ==> 0XE000D000[19:19] = 0x00000001U */
3712 /* .. ==> MASK : 0x00080000U VAL : 0x00080000U */
3713 /* .. */
3714 EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U),
3715 /* .. FINISH: QSPI REGISTERS */
3716 /* .. START: PL POWER ON RESET REGISTERS */
3717 /* .. PCFG_POR_CNT_4K = 0 */
3718 /* .. ==> 0XF8007000[29:29] = 0x00000000U */
3719 /* .. ==> MASK : 0x20000000U VAL : 0x00000000U */
3720 /* .. */
3721 EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
3722 /* .. FINISH: PL POWER ON RESET REGISTERS */
3723 /* .. START: SMC TIMING CALCULATION REGISTER UPDATE */
3724 /* .. .. START: NAND SET CYCLE */
3725 /* .. .. FINISH: NAND SET CYCLE */
3726 /* .. .. START: OPMODE */
3727 /* .. .. FINISH: OPMODE */
3728 /* .. .. START: DIRECT COMMAND */
3729 /* .. .. FINISH: DIRECT COMMAND */
3730 /* .. .. START: SRAM/NOR CS0 SET CYCLE */
3731 /* .. .. FINISH: SRAM/NOR CS0 SET CYCLE */
3732 /* .. .. START: DIRECT COMMAND */
3733 /* .. .. FINISH: DIRECT COMMAND */
3734 /* .. .. START: NOR CS0 BASE ADDRESS */
3735 /* .. .. FINISH: NOR CS0 BASE ADDRESS */
3736 /* .. .. START: SRAM/NOR CS1 SET CYCLE */
3737 /* .. .. FINISH: SRAM/NOR CS1 SET CYCLE */
3738 /* .. .. START: DIRECT COMMAND */
3739 /* .. .. FINISH: DIRECT COMMAND */
3740 /* .. .. START: NOR CS1 BASE ADDRESS */
3741 /* .. .. FINISH: NOR CS1 BASE ADDRESS */
3742 /* .. .. START: USB RESET */
3743 /* .. .. .. START: USB0 RESET */
3744 /* .. .. .. .. START: DIR MODE BANK 0 */
3745 /* .. .. .. .. FINISH: DIR MODE BANK 0 */
3746 /* .. .. .. .. START: DIR MODE BANK 1 */
Michal Simek264065f2016-03-03 13:25:03 +0100[diff] [blame]3747 /* .. .. .. .. DIRECTION_1 = 0x4000 */
3748 /* .. .. .. .. ==> 0XE000A244[21:0] = 0x00004000U */
3749 /* .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U */
3750 /* .. .. .. .. */
3751 EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU, 0x00004000U),
Nathan Rossi4eeed0e2015-11-24 19:34:09 +1000[diff] [blame]3752 /* .. .. .. .. FINISH: DIR MODE BANK 1 */
3753 /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
3754 /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
3755 /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
3756 /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
3757 /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
Michal Simek264065f2016-03-03 13:25:03 +0100[diff] [blame]3758 /* .. .. .. .. MASK_1_LSW = 0xbfff */
3759 /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
3760 /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */
3761 /* .. .. .. .. DATA_1_LSW = 0x4000 */
3762 /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U */
3763 /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U */
3764 /* .. .. .. .. */
3765 EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U),
Nathan Rossi4eeed0e2015-11-24 19:34:09 +1000[diff] [blame]3766 /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
3767 /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
3768 /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
3769 /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
3770 /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
3771 /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
Michal Simek264065f2016-03-03 13:25:03 +0100[diff] [blame]3772 /* .. .. .. .. OP_ENABLE_1 = 0x4000 */
3773 /* .. .. .. .. ==> 0XE000A248[21:0] = 0x00004000U */
3774 /* .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U */
3775 /* .. .. .. .. */
3776 EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU, 0x00004000U),
Nathan Rossi4eeed0e2015-11-24 19:34:09 +1000[diff] [blame]3777 /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
3778 /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
3779 /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
3780 /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
3781 /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
3782 /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
Michal Simek264065f2016-03-03 13:25:03 +0100[diff] [blame]3783 /* .. .. .. .. MASK_1_LSW = 0xbfff */
3784 /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
3785 /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */
3786 /* .. .. .. .. DATA_1_LSW = 0x0 */
3787 /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U */
3788 /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U */
3789 /* .. .. .. .. */
3790 EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF0000U),
Nathan Rossi4eeed0e2015-11-24 19:34:09 +1000[diff] [blame]3791 /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
3792 /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
3793 /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
3794 /* .. .. .. .. START: ADD 1 MS DELAY */
3795 /* .. .. .. .. */
3796 EMIT_MASKDELAY(0XF8F00200, 1),
3797 /* .. .. .. .. FINISH: ADD 1 MS DELAY */
3798 /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
3799 /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
3800 /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
3801 /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
3802 /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
Michal Simek264065f2016-03-03 13:25:03 +0100[diff] [blame]3803 /* .. .. .. .. MASK_1_LSW = 0xbfff */
3804 /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
3805 /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */
3806 /* .. .. .. .. DATA_1_LSW = 0x4000 */
3807 /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U */
3808 /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U */
3809 /* .. .. .. .. */
3810 EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U),
Nathan Rossi4eeed0e2015-11-24 19:34:09 +1000[diff] [blame]3811 /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
3812 /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
3813 /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
3814 /* .. .. .. FINISH: USB0 RESET */
3815 /* .. .. .. START: USB1 RESET */
3816 /* .. .. .. .. START: DIR MODE BANK 0 */
3817 /* .. .. .. .. FINISH: DIR MODE BANK 0 */
3818 /* .. .. .. .. START: DIR MODE BANK 1 */
3819 /* .. .. .. .. FINISH: DIR MODE BANK 1 */
3820 /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
3821 /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
3822 /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
3823 /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
3824 /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
3825 /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
3826 /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
3827 /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
3828 /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
3829 /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
3830 /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
3831 /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
3832 /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
3833 /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
3834 /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
3835 /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
3836 /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
3837 /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
3838 /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
3839 /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
3840 /* .. .. .. .. START: ADD 1 MS DELAY */
3841 /* .. .. .. .. */
3842 EMIT_MASKDELAY(0XF8F00200, 1),
3843 /* .. .. .. .. FINISH: ADD 1 MS DELAY */
3844 /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
3845 /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
3846 /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
3847 /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
3848 /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
3849 /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
3850 /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
3851 /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
3852 /* .. .. .. FINISH: USB1 RESET */
3853 /* .. .. FINISH: USB RESET */
3854 /* .. .. START: ENET RESET */
3855 /* .. .. .. START: ENET0 RESET */
3856 /* .. .. .. .. START: DIR MODE BANK 0 */
3857 /* .. .. .. .. FINISH: DIR MODE BANK 0 */
3858 /* .. .. .. .. START: DIR MODE BANK 1 */
3859 /* .. .. .. .. FINISH: DIR MODE BANK 1 */
3860 /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
3861 /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
3862 /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
3863 /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
3864 /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
3865 /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
3866 /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
3867 /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
3868 /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
3869 /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
3870 /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
3871 /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
3872 /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
3873 /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
3874 /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
3875 /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
3876 /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
3877 /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
3878 /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
3879 /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
3880 /* .. .. .. .. START: ADD 1 MS DELAY */
3881 /* .. .. .. .. */
3882 EMIT_MASKDELAY(0XF8F00200, 1),
3883 /* .. .. .. .. FINISH: ADD 1 MS DELAY */
3884 /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
3885 /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
3886 /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
3887 /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
3888 /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
3889 /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
3890 /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
3891 /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
3892 /* .. .. .. FINISH: ENET0 RESET */
3893 /* .. .. .. START: ENET1 RESET */
3894 /* .. .. .. .. START: DIR MODE BANK 0 */
3895 /* .. .. .. .. FINISH: DIR MODE BANK 0 */
3896 /* .. .. .. .. START: DIR MODE BANK 1 */
3897 /* .. .. .. .. FINISH: DIR MODE BANK 1 */
3898 /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
3899 /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
3900 /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
3901 /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
3902 /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
3903 /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
3904 /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
3905 /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
3906 /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
3907 /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
3908 /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
3909 /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
3910 /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
3911 /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
3912 /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
3913 /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
3914 /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
3915 /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
3916 /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
3917 /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
3918 /* .. .. .. .. START: ADD 1 MS DELAY */
3919 /* .. .. .. .. */
3920 EMIT_MASKDELAY(0XF8F00200, 1),
3921 /* .. .. .. .. FINISH: ADD 1 MS DELAY */
3922 /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
3923 /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
3924 /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
3925 /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
3926 /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
3927 /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
3928 /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
3929 /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
3930 /* .. .. .. FINISH: ENET1 RESET */
3931 /* .. .. FINISH: ENET RESET */
3932 /* .. .. START: I2C RESET */
3933 /* .. .. .. START: I2C0 RESET */
3934 /* .. .. .. .. START: DIR MODE GPIO BANK0 */
3935 /* .. .. .. .. FINISH: DIR MODE GPIO BANK0 */
3936 /* .. .. .. .. START: DIR MODE GPIO BANK1 */
3937 /* .. .. .. .. FINISH: DIR MODE GPIO BANK1 */
3938 /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
3939 /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
3940 /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
3941 /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
3942 /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
3943 /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
3944 /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
3945 /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
3946 /* .. .. .. .. START: OUTPUT ENABLE */
3947 /* .. .. .. .. FINISH: OUTPUT ENABLE */
3948 /* .. .. .. .. START: OUTPUT ENABLE */
3949 /* .. .. .. .. FINISH: OUTPUT ENABLE */
3950 /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
3951 /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
3952 /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
3953 /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
3954 /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
3955 /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
3956 /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
3957 /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
3958 /* .. .. .. .. START: ADD 1 MS DELAY */
3959 /* .. .. .. .. */
3960 EMIT_MASKDELAY(0XF8F00200, 1),
3961 /* .. .. .. .. FINISH: ADD 1 MS DELAY */
3962 /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
3963 /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
3964 /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
3965 /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
3966 /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
3967 /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
3968 /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
3969 /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
3970 /* .. .. .. FINISH: I2C0 RESET */
3971 /* .. .. .. START: I2C1 RESET */
3972 /* .. .. .. .. START: DIR MODE GPIO BANK0 */
3973 /* .. .. .. .. FINISH: DIR MODE GPIO BANK0 */
3974 /* .. .. .. .. START: DIR MODE GPIO BANK1 */
3975 /* .. .. .. .. FINISH: DIR MODE GPIO BANK1 */
3976 /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
3977 /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
3978 /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
3979 /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
3980 /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
3981 /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
3982 /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
3983 /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
3984 /* .. .. .. .. START: OUTPUT ENABLE */
3985 /* .. .. .. .. FINISH: OUTPUT ENABLE */
3986 /* .. .. .. .. START: OUTPUT ENABLE */
3987 /* .. .. .. .. FINISH: OUTPUT ENABLE */
3988 /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
3989 /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
3990 /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
3991 /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
3992 /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
3993 /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
3994 /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
3995 /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
3996 /* .. .. .. .. START: ADD 1 MS DELAY */
3997 /* .. .. .. .. */
3998 EMIT_MASKDELAY(0XF8F00200, 1),
3999 /* .. .. .. .. FINISH: ADD 1 MS DELAY */
4000 /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
4001 /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
4002 /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
4003 /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
4004 /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
4005 /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
4006 /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
4007 /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
4008 /* .. .. .. FINISH: I2C1 RESET */
4009 /* .. .. FINISH: I2C RESET */
4010 /* .. .. START: NOR CHIP SELECT */
4011 /* .. .. .. START: DIR MODE BANK 0 */
4012 /* .. .. .. FINISH: DIR MODE BANK 0 */
4013 /* .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
4014 /* .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
4015 /* .. .. .. START: OUTPUT ENABLE BANK 0 */
4016 /* .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
4017 /* .. .. FINISH: NOR CHIP SELECT */
4018 /* .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE */
4019 /* FINISH: top */
4020 /* */
4021 EMIT_EXIT(),
4022
4023 /* */
4024};
4025
4026unsigned long ps7_post_config_3_0[] = {
4027 /* START: top */
4028 /* .. START: SLCR SETTINGS */
4029 /* .. UNLOCK_KEY = 0XDF0D */
4030 /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
4031 /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */
4032 /* .. */
4033 EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
4034 /* .. FINISH: SLCR SETTINGS */
4035 /* .. START: ENABLING LEVEL SHIFTER */
4036 /* .. USER_LVL_INP_EN_0 = 1 */
4037 /* .. ==> 0XF8000900[3:3] = 0x00000001U */
4038 /* .. ==> MASK : 0x00000008U VAL : 0x00000008U */
4039 /* .. USER_LVL_OUT_EN_0 = 1 */
4040 /* .. ==> 0XF8000900[2:2] = 0x00000001U */
4041 /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
4042 /* .. USER_LVL_INP_EN_1 = 1 */
4043 /* .. ==> 0XF8000900[1:1] = 0x00000001U */
4044 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
4045 /* .. USER_LVL_OUT_EN_1 = 1 */
4046 /* .. ==> 0XF8000900[0:0] = 0x00000001U */
4047 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
4048 /* .. */
4049 EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU),
4050 /* .. FINISH: ENABLING LEVEL SHIFTER */
Nathan Rossi4eeed0e2015-11-24 19:34:09 +1000[diff] [blame]4051 /* .. START: FPGA RESETS TO 0 */
4052 /* .. reserved_3 = 0 */
4053 /* .. ==> 0XF8000240[31:25] = 0x00000000U */
4054 /* .. ==> MASK : 0xFE000000U VAL : 0x00000000U */
4055 /* .. reserved_FPGA_ACP_RST = 0 */
4056 /* .. ==> 0XF8000240[24:24] = 0x00000000U */
4057 /* .. ==> MASK : 0x01000000U VAL : 0x00000000U */
4058 /* .. reserved_FPGA_AXDS3_RST = 0 */
4059 /* .. ==> 0XF8000240[23:23] = 0x00000000U */
4060 /* .. ==> MASK : 0x00800000U VAL : 0x00000000U */
4061 /* .. reserved_FPGA_AXDS2_RST = 0 */
4062 /* .. ==> 0XF8000240[22:22] = 0x00000000U */
4063 /* .. ==> MASK : 0x00400000U VAL : 0x00000000U */
4064 /* .. reserved_FPGA_AXDS1_RST = 0 */
4065 /* .. ==> 0XF8000240[21:21] = 0x00000000U */
4066 /* .. ==> MASK : 0x00200000U VAL : 0x00000000U */
4067 /* .. reserved_FPGA_AXDS0_RST = 0 */
4068 /* .. ==> 0XF8000240[20:20] = 0x00000000U */
4069 /* .. ==> MASK : 0x00100000U VAL : 0x00000000U */
4070 /* .. reserved_2 = 0 */
4071 /* .. ==> 0XF8000240[19:18] = 0x00000000U */
4072 /* .. ==> MASK : 0x000C0000U VAL : 0x00000000U */
4073 /* .. reserved_FSSW1_FPGA_RST = 0 */
4074 /* .. ==> 0XF8000240[17:17] = 0x00000000U */
4075 /* .. ==> MASK : 0x00020000U VAL : 0x00000000U */
4076 /* .. reserved_FSSW0_FPGA_RST = 0 */
4077 /* .. ==> 0XF8000240[16:16] = 0x00000000U */
4078 /* .. ==> MASK : 0x00010000U VAL : 0x00000000U */
4079 /* .. reserved_1 = 0 */
4080 /* .. ==> 0XF8000240[15:14] = 0x00000000U */
4081 /* .. ==> MASK : 0x0000C000U VAL : 0x00000000U */
4082 /* .. reserved_FPGA_FMSW1_RST = 0 */
4083 /* .. ==> 0XF8000240[13:13] = 0x00000000U */
4084 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
4085 /* .. reserved_FPGA_FMSW0_RST = 0 */
4086 /* .. ==> 0XF8000240[12:12] = 0x00000000U */
4087 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
4088 /* .. reserved_FPGA_DMA3_RST = 0 */
4089 /* .. ==> 0XF8000240[11:11] = 0x00000000U */
4090 /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
4091 /* .. reserved_FPGA_DMA2_RST = 0 */
4092 /* .. ==> 0XF8000240[10:10] = 0x00000000U */
4093 /* .. ==> MASK : 0x00000400U VAL : 0x00000000U */
4094 /* .. reserved_FPGA_DMA1_RST = 0 */
4095 /* .. ==> 0XF8000240[9:9] = 0x00000000U */
4096 /* .. ==> MASK : 0x00000200U VAL : 0x00000000U */
4097 /* .. reserved_FPGA_DMA0_RST = 0 */
4098 /* .. ==> 0XF8000240[8:8] = 0x00000000U */
4099 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
4100 /* .. reserved = 0 */
4101 /* .. ==> 0XF8000240[7:4] = 0x00000000U */
4102 /* .. ==> MASK : 0x000000F0U VAL : 0x00000000U */
4103 /* .. FPGA3_OUT_RST = 0 */
4104 /* .. ==> 0XF8000240[3:3] = 0x00000000U */
4105 /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
4106 /* .. FPGA2_OUT_RST = 0 */
4107 /* .. ==> 0XF8000240[2:2] = 0x00000000U */
4108 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
4109 /* .. FPGA1_OUT_RST = 0 */
4110 /* .. ==> 0XF8000240[1:1] = 0x00000000U */
4111 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
4112 /* .. FPGA0_OUT_RST = 0 */
4113 /* .. ==> 0XF8000240[0:0] = 0x00000000U */
4114 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
4115 /* .. */
4116 EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U),
4117 /* .. FINISH: FPGA RESETS TO 0 */
4118 /* .. START: AFI REGISTERS */
4119 /* .. .. START: AFI0 REGISTERS */
4120 /* .. .. FINISH: AFI0 REGISTERS */
4121 /* .. .. START: AFI1 REGISTERS */
4122 /* .. .. FINISH: AFI1 REGISTERS */
4123 /* .. .. START: AFI2 REGISTERS */
4124 /* .. .. FINISH: AFI2 REGISTERS */
4125 /* .. .. START: AFI3 REGISTERS */
4126 /* .. .. FINISH: AFI3 REGISTERS */
Michal Simek264065f2016-03-03 13:25:03 +0100[diff] [blame]4127 /* .. .. START: AFI2 SECURE REGISTER */
4128 /* .. .. FINISH: AFI2 SECURE REGISTER */
Nathan Rossi4eeed0e2015-11-24 19:34:09 +1000[diff] [blame]4129 /* .. FINISH: AFI REGISTERS */
4130 /* .. START: LOCK IT BACK */
4131 /* .. LOCK_KEY = 0X767B */
4132 /* .. ==> 0XF8000004[15:0] = 0x0000767BU */
4133 /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */
4134 /* .. */
4135 EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
4136 /* .. FINISH: LOCK IT BACK */
4137 /* FINISH: top */
4138 /* */
4139 EMIT_EXIT(),
4140
4141 /* */
4142};
4143
Nathan Rossi4eeed0e2015-11-24 19:34:09 +1000[diff] [blame]4144
4145unsigned long ps7_pll_init_data_2_0[] = {
4146 /* START: top */
4147 /* .. START: SLCR SETTINGS */
4148 /* .. UNLOCK_KEY = 0XDF0D */
4149 /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
4150 /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */
4151 /* .. */
4152 EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
4153 /* .. FINISH: SLCR SETTINGS */
4154 /* .. START: PLL SLCR REGISTERS */
4155 /* .. .. START: ARM PLL INIT */
4156 /* .. .. PLL_RES = 0xc */
4157 /* .. .. ==> 0XF8000110[7:4] = 0x0000000CU */
4158 /* .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U */
4159 /* .. .. PLL_CP = 0x2 */
4160 /* .. .. ==> 0XF8000110[11:8] = 0x00000002U */
4161 /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */
4162 /* .. .. LOCK_CNT = 0x177 */
4163 /* .. .. ==> 0XF8000110[21:12] = 0x00000177U */
4164 /* .. .. ==> MASK : 0x003FF000U VAL : 0x00177000U */
4165 /* .. .. */
4166 EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x001772C0U),
4167 /* .. .. .. START: UPDATE FB_DIV */
4168 /* .. .. .. PLL_FDIV = 0x1a */
4169 /* .. .. .. ==> 0XF8000100[18:12] = 0x0000001AU */
4170 /* .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001A000U */
4171 /* .. .. .. */
4172 EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x0001A000U),
4173 /* .. .. .. FINISH: UPDATE FB_DIV */
4174 /* .. .. .. START: BY PASS PLL */
4175 /* .. .. .. PLL_BYPASS_FORCE = 1 */
4176 /* .. .. .. ==> 0XF8000100[4:4] = 0x00000001U */
4177 /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U */
4178 /* .. .. .. */
4179 EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U),
4180 /* .. .. .. FINISH: BY PASS PLL */
4181 /* .. .. .. START: ASSERT RESET */
4182 /* .. .. .. PLL_RESET = 1 */
4183 /* .. .. .. ==> 0XF8000100[0:0] = 0x00000001U */
4184 /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
4185 /* .. .. .. */
4186 EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U),
4187 /* .. .. .. FINISH: ASSERT RESET */
4188 /* .. .. .. START: DEASSERT RESET */
4189 /* .. .. .. PLL_RESET = 0 */
4190 /* .. .. .. ==> 0XF8000100[0:0] = 0x00000000U */
4191 /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
4192 /* .. .. .. */
4193 EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U),
4194 /* .. .. .. FINISH: DEASSERT RESET */
4195 /* .. .. .. START: CHECK PLL STATUS */
4196 /* .. .. .. ARM_PLL_LOCK = 1 */
4197 /* .. .. .. ==> 0XF800010C[0:0] = 0x00000001U */
4198 /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
4199 /* .. .. .. */
4200 EMIT_MASKPOLL(0XF800010C, 0x00000001U),
4201 /* .. .. .. FINISH: CHECK PLL STATUS */
4202 /* .. .. .. START: REMOVE PLL BY PASS */
4203 /* .. .. .. PLL_BYPASS_FORCE = 0 */
4204 /* .. .. .. ==> 0XF8000100[4:4] = 0x00000000U */
4205 /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
4206 /* .. .. .. */
4207 EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U),
4208 /* .. .. .. FINISH: REMOVE PLL BY PASS */
4209 /* .. .. .. SRCSEL = 0x0 */
4210 /* .. .. .. ==> 0XF8000120[5:4] = 0x00000000U */
4211 /* .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
4212 /* .. .. .. DIVISOR = 0x2 */
4213 /* .. .. .. ==> 0XF8000120[13:8] = 0x00000002U */
4214 /* .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U */
4215 /* .. .. .. CPU_6OR4XCLKACT = 0x1 */
4216 /* .. .. .. ==> 0XF8000120[24:24] = 0x00000001U */
4217 /* .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U */
4218 /* .. .. .. CPU_3OR2XCLKACT = 0x1 */
4219 /* .. .. .. ==> 0XF8000120[25:25] = 0x00000001U */
4220 /* .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U */
4221 /* .. .. .. CPU_2XCLKACT = 0x1 */
4222 /* .. .. .. ==> 0XF8000120[26:26] = 0x00000001U */
4223 /* .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U */
4224 /* .. .. .. CPU_1XCLKACT = 0x1 */
4225 /* .. .. .. ==> 0XF8000120[27:27] = 0x00000001U */
4226 /* .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U */
4227 /* .. .. .. CPU_PERI_CLKACT = 0x1 */
4228 /* .. .. .. ==> 0XF8000120[28:28] = 0x00000001U */
4229 /* .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U */
4230 /* .. .. .. */
4231 EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U),
4232 /* .. .. FINISH: ARM PLL INIT */
4233 /* .. .. START: DDR PLL INIT */
4234 /* .. .. PLL_RES = 0xc */
4235 /* .. .. ==> 0XF8000114[7:4] = 0x0000000CU */
4236 /* .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U */
4237 /* .. .. PLL_CP = 0x2 */
4238 /* .. .. ==> 0XF8000114[11:8] = 0x00000002U */
4239 /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */
4240 /* .. .. LOCK_CNT = 0x1db */
4241 /* .. .. ==> 0XF8000114[21:12] = 0x000001DBU */
4242 /* .. .. ==> MASK : 0x003FF000U VAL : 0x001DB000U */
4243 /* .. .. */
4244 EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x001DB2C0U),
4245 /* .. .. .. START: UPDATE FB_DIV */
4246 /* .. .. .. PLL_FDIV = 0x15 */
4247 /* .. .. .. ==> 0XF8000104[18:12] = 0x00000015U */
4248 /* .. .. .. ==> MASK : 0x0007F000U VAL : 0x00015000U */
4249 /* .. .. .. */
4250 EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00015000U),
4251 /* .. .. .. FINISH: UPDATE FB_DIV */
4252 /* .. .. .. START: BY PASS PLL */
4253 /* .. .. .. PLL_BYPASS_FORCE = 1 */
4254 /* .. .. .. ==> 0XF8000104[4:4] = 0x00000001U */
4255 /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U */
4256 /* .. .. .. */
4257 EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U),
4258 /* .. .. .. FINISH: BY PASS PLL */
4259 /* .. .. .. START: ASSERT RESET */
4260 /* .. .. .. PLL_RESET = 1 */
4261 /* .. .. .. ==> 0XF8000104[0:0] = 0x00000001U */
4262 /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
4263 /* .. .. .. */
4264 EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U),
4265 /* .. .. .. FINISH: ASSERT RESET */
4266 /* .. .. .. START: DEASSERT RESET */
4267 /* .. .. .. PLL_RESET = 0 */
4268 /* .. .. .. ==> 0XF8000104[0:0] = 0x00000000U */
4269 /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
4270 /* .. .. .. */
4271 EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U),
4272 /* .. .. .. FINISH: DEASSERT RESET */
4273 /* .. .. .. START: CHECK PLL STATUS */
4274 /* .. .. .. DDR_PLL_LOCK = 1 */
4275 /* .. .. .. ==> 0XF800010C[1:1] = 0x00000001U */
4276 /* .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */
4277 /* .. .. .. */
4278 EMIT_MASKPOLL(0XF800010C, 0x00000002U),
4279 /* .. .. .. FINISH: CHECK PLL STATUS */
4280 /* .. .. .. START: REMOVE PLL BY PASS */
4281 /* .. .. .. PLL_BYPASS_FORCE = 0 */
4282 /* .. .. .. ==> 0XF8000104[4:4] = 0x00000000U */
4283 /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
4284 /* .. .. .. */
4285 EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U),
4286 /* .. .. .. FINISH: REMOVE PLL BY PASS */
4287 /* .. .. .. DDR_3XCLKACT = 0x1 */
4288 /* .. .. .. ==> 0XF8000124[0:0] = 0x00000001U */
4289 /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
4290 /* .. .. .. DDR_2XCLKACT = 0x1 */
4291 /* .. .. .. ==> 0XF8000124[1:1] = 0x00000001U */
4292 /* .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */
4293 /* .. .. .. DDR_3XCLK_DIVISOR = 0x2 */
4294 /* .. .. .. ==> 0XF8000124[25:20] = 0x00000002U */
4295 /* .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U */
4296 /* .. .. .. DDR_2XCLK_DIVISOR = 0x3 */
4297 /* .. .. .. ==> 0XF8000124[31:26] = 0x00000003U */
4298 /* .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U */
4299 /* .. .. .. */
4300 EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U),
4301 /* .. .. FINISH: DDR PLL INIT */
4302 /* .. .. START: IO PLL INIT */
4303 /* .. .. PLL_RES = 0xc */
4304 /* .. .. ==> 0XF8000118[7:4] = 0x0000000CU */
4305 /* .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U */
4306 /* .. .. PLL_CP = 0x2 */
4307 /* .. .. ==> 0XF8000118[11:8] = 0x00000002U */
4308 /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */
4309 /* .. .. LOCK_CNT = 0x1f4 */
4310 /* .. .. ==> 0XF8000118[21:12] = 0x000001F4U */
4311 /* .. .. ==> MASK : 0x003FF000U VAL : 0x001F4000U */
4312 /* .. .. */
4313 EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x001F42C0U),
4314 /* .. .. .. START: UPDATE FB_DIV */
4315 /* .. .. .. PLL_FDIV = 0x14 */
4316 /* .. .. .. ==> 0XF8000108[18:12] = 0x00000014U */
4317 /* .. .. .. ==> MASK : 0x0007F000U VAL : 0x00014000U */
4318 /* .. .. .. */
4319 EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x00014000U),
4320 /* .. .. .. FINISH: UPDATE FB_DIV */
4321 /* .. .. .. START: BY PASS PLL */
4322 /* .. .. .. PLL_BYPASS_FORCE = 1 */
4323 /* .. .. .. ==> 0XF8000108[4:4] = 0x00000001U */
4324 /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U */
4325 /* .. .. .. */
4326 EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U),
4327 /* .. .. .. FINISH: BY PASS PLL */
4328 /* .. .. .. START: ASSERT RESET */
4329 /* .. .. .. PLL_RESET = 1 */
4330 /* .. .. .. ==> 0XF8000108[0:0] = 0x00000001U */
4331 /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
4332 /* .. .. .. */
4333 EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U),
4334 /* .. .. .. FINISH: ASSERT RESET */
4335 /* .. .. .. START: DEASSERT RESET */
4336 /* .. .. .. PLL_RESET = 0 */
4337 /* .. .. .. ==> 0XF8000108[0:0] = 0x00000000U */
4338 /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
4339 /* .. .. .. */
4340 EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U),
4341 /* .. .. .. FINISH: DEASSERT RESET */
4342 /* .. .. .. START: CHECK PLL STATUS */
4343 /* .. .. .. IO_PLL_LOCK = 1 */
4344 /* .. .. .. ==> 0XF800010C[2:2] = 0x00000001U */
4345 /* .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U */
4346 /* .. .. .. */
4347 EMIT_MASKPOLL(0XF800010C, 0x00000004U),
4348 /* .. .. .. FINISH: CHECK PLL STATUS */
4349 /* .. .. .. START: REMOVE PLL BY PASS */
4350 /* .. .. .. PLL_BYPASS_FORCE = 0 */
4351 /* .. .. .. ==> 0XF8000108[4:4] = 0x00000000U */
4352 /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
4353 /* .. .. .. */
4354 EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U),
4355 /* .. .. .. FINISH: REMOVE PLL BY PASS */
4356 /* .. .. FINISH: IO PLL INIT */
4357 /* .. FINISH: PLL SLCR REGISTERS */
4358 /* .. START: LOCK IT BACK */
4359 /* .. LOCK_KEY = 0X767B */
4360 /* .. ==> 0XF8000004[15:0] = 0x0000767BU */
4361 /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */
4362 /* .. */
4363 EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
4364 /* .. FINISH: LOCK IT BACK */
4365 /* FINISH: top */
4366 /* */
4367 EMIT_EXIT(),
4368
4369 /* */
4370};
4371
4372unsigned long ps7_clock_init_data_2_0[] = {
4373 /* START: top */
4374 /* .. START: SLCR SETTINGS */
4375 /* .. UNLOCK_KEY = 0XDF0D */
4376 /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
4377 /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */
4378 /* .. */
4379 EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
4380 /* .. FINISH: SLCR SETTINGS */
4381 /* .. START: CLOCK CONTROL SLCR REGISTERS */
4382 /* .. CLKACT = 0x1 */
4383 /* .. ==> 0XF8000128[0:0] = 0x00000001U */
4384 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
4385 /* .. DIVISOR0 = 0x34 */
4386 /* .. ==> 0XF8000128[13:8] = 0x00000034U */
4387 /* .. ==> MASK : 0x00003F00U VAL : 0x00003400U */
4388 /* .. DIVISOR1 = 0x2 */
4389 /* .. ==> 0XF8000128[25:20] = 0x00000002U */
4390 /* .. ==> MASK : 0x03F00000U VAL : 0x00200000U */
4391 /* .. */
4392 EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00203401U),
4393 /* .. CLKACT = 0x1 */
4394 /* .. ==> 0XF8000138[0:0] = 0x00000001U */
4395 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
4396 /* .. SRCSEL = 0x0 */
4397 /* .. ==> 0XF8000138[4:4] = 0x00000000U */
4398 /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */
4399 /* .. */
4400 EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000001U),
4401 /* .. CLKACT = 0x1 */
4402 /* .. ==> 0XF8000140[0:0] = 0x00000001U */
4403 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
4404 /* .. SRCSEL = 0x0 */
4405 /* .. ==> 0XF8000140[6:4] = 0x00000000U */
4406 /* .. ==> MASK : 0x00000070U VAL : 0x00000000U */
4407 /* .. DIVISOR = 0x8 */
4408 /* .. ==> 0XF8000140[13:8] = 0x00000008U */
4409 /* .. ==> MASK : 0x00003F00U VAL : 0x00000800U */
4410 /* .. DIVISOR1 = 0x1 */
4411 /* .. ==> 0XF8000140[25:20] = 0x00000001U */
4412 /* .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
4413 /* .. */
4414 EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00100801U),
4415 /* .. CLKACT = 0x1 */
4416 /* .. ==> 0XF800014C[0:0] = 0x00000001U */
4417 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
4418 /* .. SRCSEL = 0x0 */
4419 /* .. ==> 0XF800014C[5:4] = 0x00000000U */
4420 /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */
4421 /* .. DIVISOR = 0x5 */
4422 /* .. ==> 0XF800014C[13:8] = 0x00000005U */
4423 /* .. ==> MASK : 0x00003F00U VAL : 0x00000500U */
4424 /* .. */
4425 EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000501U),
4426 /* .. CLKACT0 = 0x1 */
4427 /* .. ==> 0XF8000150[0:0] = 0x00000001U */
4428 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
4429 /* .. CLKACT1 = 0x0 */
4430 /* .. ==> 0XF8000150[1:1] = 0x00000000U */
4431 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
4432 /* .. SRCSEL = 0x0 */
4433 /* .. ==> 0XF8000150[5:4] = 0x00000000U */
4434 /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */
4435 /* .. DIVISOR = 0x14 */
4436 /* .. ==> 0XF8000150[13:8] = 0x00000014U */
4437 /* .. ==> MASK : 0x00003F00U VAL : 0x00001400U */
4438 /* .. */
4439 EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00001401U),
4440 /* .. CLKACT0 = 0x0 */
4441 /* .. ==> 0XF8000154[0:0] = 0x00000000U */
4442 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
4443 /* .. CLKACT1 = 0x1 */
4444 /* .. ==> 0XF8000154[1:1] = 0x00000001U */
4445 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
4446 /* .. SRCSEL = 0x0 */
4447 /* .. ==> 0XF8000154[5:4] = 0x00000000U */
4448 /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */
Michal Simek264065f2016-03-03 13:25:03 +0100[diff] [blame]4449 /* .. DIVISOR = 0xa */
4450 /* .. ==> 0XF8000154[13:8] = 0x0000000AU */
4451 /* .. ==> MASK : 0x00003F00U VAL : 0x00000A00U */
Nathan Rossi4eeed0e2015-11-24 19:34:09 +1000[diff] [blame]4452 /* .. */
Michal Simek264065f2016-03-03 13:25:03 +0100[diff] [blame]4453 EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A02U),
Nathan Rossi4eeed0e2015-11-24 19:34:09 +1000[diff] [blame]4454 /* .. .. START: TRACE CLOCK */
4455 /* .. .. FINISH: TRACE CLOCK */
4456 /* .. .. CLKACT = 0x1 */
4457 /* .. .. ==> 0XF8000168[0:0] = 0x00000001U */
4458 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
4459 /* .. .. SRCSEL = 0x0 */
4460 /* .. .. ==> 0XF8000168[5:4] = 0x00000000U */
4461 /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
4462 /* .. .. DIVISOR = 0x5 */
4463 /* .. .. ==> 0XF8000168[13:8] = 0x00000005U */
4464 /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U */
4465 /* .. .. */
4466 EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000501U),
4467 /* .. .. SRCSEL = 0x0 */
4468 /* .. .. ==> 0XF8000170[5:4] = 0x00000000U */
4469 /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
4470 /* .. .. DIVISOR0 = 0xa */
4471 /* .. .. ==> 0XF8000170[13:8] = 0x0000000AU */
4472 /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U */
4473 /* .. .. DIVISOR1 = 0x1 */
4474 /* .. .. ==> 0XF8000170[25:20] = 0x00000001U */
4475 /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
4476 /* .. .. */
4477 EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00100A00U),
Michal Simek264065f2016-03-03 13:25:03 +0100[diff] [blame]4478 /* .. .. SRCSEL = 0x0 */
4479 /* .. .. ==> 0XF8000180[5:4] = 0x00000000U */
4480 /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
4481 /* .. .. DIVISOR0 = 0x7 */
4482 /* .. .. ==> 0XF8000180[13:8] = 0x00000007U */
4483 /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000700U */
Nathan Rossi4eeed0e2015-11-24 19:34:09 +1000[diff] [blame]4484 /* .. .. DIVISOR1 = 0x1 */
4485 /* .. .. ==> 0XF8000180[25:20] = 0x00000001U */
4486 /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
4487 /* .. .. */
Michal Simek264065f2016-03-03 13:25:03 +0100[diff] [blame]4488 EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100700U),
4489 /* .. .. SRCSEL = 0x0 */
4490 /* .. .. ==> 0XF8000190[5:4] = 0x00000000U */
4491 /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
4492 /* .. .. DIVISOR0 = 0x5 */
4493 /* .. .. ==> 0XF8000190[13:8] = 0x00000005U */
4494 /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U */
4495 /* .. .. DIVISOR1 = 0x1 */
4496 /* .. .. ==> 0XF8000190[25:20] = 0x00000001U */
4497 /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
Nathan Rossi4eeed0e2015-11-24 19:34:09 +1000[diff] [blame]4498 /* .. .. */
Michal Simek264065f2016-03-03 13:25:03 +0100[diff] [blame]4499 EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00100500U),
Nathan Rossi4eeed0e2015-11-24 19:34:09 +1000[diff] [blame]4500 /* .. .. SRCSEL = 0x0 */
4501 /* .. .. ==> 0XF80001A0[5:4] = 0x00000000U */
4502 /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
Michal Simek264065f2016-03-03 13:25:03 +0100[diff] [blame]4503 /* .. .. DIVISOR0 = 0x14 */
4504 /* .. .. ==> 0XF80001A0[13:8] = 0x00000014U */
4505 /* .. .. ==> MASK : 0x00003F00U VAL : 0x00001400U */
Nathan Rossi4eeed0e2015-11-24 19:34:09 +1000[diff] [blame]4506 /* .. .. DIVISOR1 = 0x1 */
4507 /* .. .. ==> 0XF80001A0[25:20] = 0x00000001U */
4508 /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
4509 /* .. .. */
Michal Simek264065f2016-03-03 13:25:03 +0100[diff] [blame]4510 EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00101400U),
Nathan Rossi4eeed0e2015-11-24 19:34:09 +1000[diff] [blame]4511 /* .. .. CLK_621_TRUE = 0x1 */
4512 /* .. .. ==> 0XF80001C4[0:0] = 0x00000001U */
4513 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
4514 /* .. .. */
4515 EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U),
4516 /* .. .. DMA_CPU_2XCLKACT = 0x1 */
4517 /* .. .. ==> 0XF800012C[0:0] = 0x00000001U */
4518 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
4519 /* .. .. USB0_CPU_1XCLKACT = 0x1 */
4520 /* .. .. ==> 0XF800012C[2:2] = 0x00000001U */
4521 /* .. .. ==> MASK : 0x00000004U VAL : 0x00000004U */
4522 /* .. .. USB1_CPU_1XCLKACT = 0x1 */
4523 /* .. .. ==> 0XF800012C[3:3] = 0x00000001U */
4524 /* .. .. ==> MASK : 0x00000008U VAL : 0x00000008U */
4525 /* .. .. GEM0_CPU_1XCLKACT = 0x1 */
4526 /* .. .. ==> 0XF800012C[6:6] = 0x00000001U */
4527 /* .. .. ==> MASK : 0x00000040U VAL : 0x00000040U */
4528 /* .. .. GEM1_CPU_1XCLKACT = 0x0 */
4529 /* .. .. ==> 0XF800012C[7:7] = 0x00000000U */
4530 /* .. .. ==> MASK : 0x00000080U VAL : 0x00000000U */
4531 /* .. .. SDI0_CPU_1XCLKACT = 0x1 */
4532 /* .. .. ==> 0XF800012C[10:10] = 0x00000001U */
4533 /* .. .. ==> MASK : 0x00000400U VAL : 0x00000400U */
4534 /* .. .. SDI1_CPU_1XCLKACT = 0x0 */
4535 /* .. .. ==> 0XF800012C[11:11] = 0x00000000U */
4536 /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */
4537 /* .. .. SPI0_CPU_1XCLKACT = 0x0 */
4538 /* .. .. ==> 0XF800012C[14:14] = 0x00000000U */
4539 /* .. .. ==> MASK : 0x00004000U VAL : 0x00000000U */
4540 /* .. .. SPI1_CPU_1XCLKACT = 0x0 */
4541 /* .. .. ==> 0XF800012C[15:15] = 0x00000000U */
4542 /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */
4543 /* .. .. CAN0_CPU_1XCLKACT = 0x0 */
4544 /* .. .. ==> 0XF800012C[16:16] = 0x00000000U */
4545 /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
4546 /* .. .. CAN1_CPU_1XCLKACT = 0x0 */
4547 /* .. .. ==> 0XF800012C[17:17] = 0x00000000U */
4548 /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
4549 /* .. .. I2C0_CPU_1XCLKACT = 0x1 */
4550 /* .. .. ==> 0XF800012C[18:18] = 0x00000001U */
4551 /* .. .. ==> MASK : 0x00040000U VAL : 0x00040000U */
4552 /* .. .. I2C1_CPU_1XCLKACT = 0x1 */
4553 /* .. .. ==> 0XF800012C[19:19] = 0x00000001U */
4554 /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */
4555 /* .. .. UART0_CPU_1XCLKACT = 0x0 */
4556 /* .. .. ==> 0XF800012C[20:20] = 0x00000000U */
4557 /* .. .. ==> MASK : 0x00100000U VAL : 0x00000000U */
4558 /* .. .. UART1_CPU_1XCLKACT = 0x1 */
4559 /* .. .. ==> 0XF800012C[21:21] = 0x00000001U */
4560 /* .. .. ==> MASK : 0x00200000U VAL : 0x00200000U */
4561 /* .. .. GPIO_CPU_1XCLKACT = 0x1 */
4562 /* .. .. ==> 0XF800012C[22:22] = 0x00000001U */
4563 /* .. .. ==> MASK : 0x00400000U VAL : 0x00400000U */
4564 /* .. .. LQSPI_CPU_1XCLKACT = 0x1 */
4565 /* .. .. ==> 0XF800012C[23:23] = 0x00000001U */
4566 /* .. .. ==> MASK : 0x00800000U VAL : 0x00800000U */
4567 /* .. .. SMC_CPU_1XCLKACT = 0x1 */
4568 /* .. .. ==> 0XF800012C[24:24] = 0x00000001U */
4569 /* .. .. ==> MASK : 0x01000000U VAL : 0x01000000U */
4570 /* .. .. */
4571 EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01EC044DU),
4572 /* .. FINISH: CLOCK CONTROL SLCR REGISTERS */
4573 /* .. START: THIS SHOULD BE BLANK */
4574 /* .. FINISH: THIS SHOULD BE BLANK */
4575 /* .. START: LOCK IT BACK */
4576 /* .. LOCK_KEY = 0X767B */
4577 /* .. ==> 0XF8000004[15:0] = 0x0000767BU */
4578 /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */
4579 /* .. */
4580 EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
4581 /* .. FINISH: LOCK IT BACK */
4582 /* FINISH: top */
4583 /* */
4584 EMIT_EXIT(),
4585
4586 /* */
4587};
4588
4589unsigned long ps7_ddr_init_data_2_0[] = {
4590 /* START: top */
4591 /* .. START: DDR INITIALIZATION */
4592 /* .. .. START: LOCK DDR */
4593 /* .. .. reg_ddrc_soft_rstb = 0 */
4594 /* .. .. ==> 0XF8006000[0:0] = 0x00000000U */
4595 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
4596 /* .. .. reg_ddrc_powerdown_en = 0x0 */
4597 /* .. .. ==> 0XF8006000[1:1] = 0x00000000U */
4598 /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
4599 /* .. .. reg_ddrc_data_bus_width = 0x0 */
4600 /* .. .. ==> 0XF8006000[3:2] = 0x00000000U */
4601 /* .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U */
4602 /* .. .. reg_ddrc_burst8_refresh = 0x0 */
4603 /* .. .. ==> 0XF8006000[6:4] = 0x00000000U */
4604 /* .. .. ==> MASK : 0x00000070U VAL : 0x00000000U */
4605 /* .. .. reg_ddrc_rdwr_idle_gap = 0x1 */
4606 /* .. .. ==> 0XF8006000[13:7] = 0x00000001U */
4607 /* .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U */
4608 /* .. .. reg_ddrc_dis_rd_bypass = 0x0 */
4609 /* .. .. ==> 0XF8006000[14:14] = 0x00000000U */
4610 /* .. .. ==> MASK : 0x00004000U VAL : 0x00000000U */
4611 /* .. .. reg_ddrc_dis_act_bypass = 0x0 */
4612 /* .. .. ==> 0XF8006000[15:15] = 0x00000000U */
4613 /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */
4614 /* .. .. reg_ddrc_dis_auto_refresh = 0x0 */
4615 /* .. .. ==> 0XF8006000[16:16] = 0x00000000U */
4616 /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
4617 /* .. .. */
4618 EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U),
4619 /* .. .. FINISH: LOCK DDR */
4620 /* .. .. reg_ddrc_t_rfc_nom_x32 = 0x7f */
4621 /* .. .. ==> 0XF8006004[11:0] = 0x0000007FU */
4622 /* .. .. ==> MASK : 0x00000FFFU VAL : 0x0000007FU */
4623 /* .. .. reg_ddrc_active_ranks = 0x1 */
4624 /* .. .. ==> 0XF8006004[13:12] = 0x00000001U */
4625 /* .. .. ==> MASK : 0x00003000U VAL : 0x00001000U */
4626 /* .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 */
4627 /* .. .. ==> 0XF8006004[18:14] = 0x00000000U */
4628 /* .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U */
4629 /* .. .. reg_ddrc_wr_odt_block = 0x1 */
4630 /* .. .. ==> 0XF8006004[20:19] = 0x00000001U */
4631 /* .. .. ==> MASK : 0x00180000U VAL : 0x00080000U */
4632 /* .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0 */
4633 /* .. .. ==> 0XF8006004[21:21] = 0x00000000U */
4634 /* .. .. ==> MASK : 0x00200000U VAL : 0x00000000U */
4635 /* .. .. reg_ddrc_addrmap_cs_bit1 = 0x0 */
4636 /* .. .. ==> 0XF8006004[26:22] = 0x00000000U */
4637 /* .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U */
4638 /* .. .. reg_ddrc_addrmap_open_bank = 0x0 */
4639 /* .. .. ==> 0XF8006004[27:27] = 0x00000000U */
4640 /* .. .. ==> MASK : 0x08000000U VAL : 0x00000000U */
4641 /* .. .. reg_ddrc_addrmap_4bank_ram = 0x0 */
4642 /* .. .. ==> 0XF8006004[28:28] = 0x00000000U */
4643 /* .. .. ==> MASK : 0x10000000U VAL : 0x00000000U */
4644 /* .. .. */
4645 EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU, 0x0008107FU),
4646 /* .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf */
4647 /* .. .. ==> 0XF8006008[10:0] = 0x0000000FU */
4648 /* .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU */
4649 /* .. .. reg_ddrc_hpr_max_starve_x32 = 0xf */
4650 /* .. .. ==> 0XF8006008[21:11] = 0x0000000FU */
4651 /* .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U */
4652 /* .. .. reg_ddrc_hpr_xact_run_length = 0xf */
4653 /* .. .. ==> 0XF8006008[25:22] = 0x0000000FU */
4654 /* .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U */
4655 /* .. .. */
4656 EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU),
4657 /* .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 */
4658 /* .. .. ==> 0XF800600C[10:0] = 0x00000001U */
4659 /* .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U */
4660 /* .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 */
4661 /* .. .. ==> 0XF800600C[21:11] = 0x00000002U */
4662 /* .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U */
4663 /* .. .. reg_ddrc_lpr_xact_run_length = 0x8 */
4664 /* .. .. ==> 0XF800600C[25:22] = 0x00000008U */
4665 /* .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U */
4666 /* .. .. */
4667 EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U),
4668 /* .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 */
4669 /* .. .. ==> 0XF8006010[10:0] = 0x00000001U */
4670 /* .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U */
4671 /* .. .. reg_ddrc_w_xact_run_length = 0x8 */
4672 /* .. .. ==> 0XF8006010[14:11] = 0x00000008U */
4673 /* .. .. ==> MASK : 0x00007800U VAL : 0x00004000U */
4674 /* .. .. reg_ddrc_w_max_starve_x32 = 0x2 */
4675 /* .. .. ==> 0XF8006010[25:15] = 0x00000002U */
4676 /* .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U */
4677 /* .. .. */
4678 EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U),
4679 /* .. .. reg_ddrc_t_rc = 0x1a */
4680 /* .. .. ==> 0XF8006014[5:0] = 0x0000001AU */
4681 /* .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU */
4682 /* .. .. reg_ddrc_t_rfc_min = 0x54 */
4683 /* .. .. ==> 0XF8006014[13:6] = 0x00000054U */
4684 /* .. .. ==> MASK : 0x00003FC0U VAL : 0x00001500U */
4685 /* .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 */
4686 /* .. .. ==> 0XF8006014[20:14] = 0x00000010U */
4687 /* .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U */
4688 /* .. .. */
4689 EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x0004151AU),
4690 /* .. .. reg_ddrc_wr2pre = 0x12 */
4691 /* .. .. ==> 0XF8006018[4:0] = 0x00000012U */
4692 /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U */
4693 /* .. .. reg_ddrc_powerdown_to_x32 = 0x6 */
4694 /* .. .. ==> 0XF8006018[9:5] = 0x00000006U */
4695 /* .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U */
4696 /* .. .. reg_ddrc_t_faw = 0x15 */
4697 /* .. .. ==> 0XF8006018[15:10] = 0x00000015U */
4698 /* .. .. ==> MASK : 0x0000FC00U VAL : 0x00005400U */
4699 /* .. .. reg_ddrc_t_ras_max = 0x23 */
4700 /* .. .. ==> 0XF8006018[21:16] = 0x00000023U */
4701 /* .. .. ==> MASK : 0x003F0000U VAL : 0x00230000U */
4702 /* .. .. reg_ddrc_t_ras_min = 0x13 */
4703 /* .. .. ==> 0XF8006018[26:22] = 0x00000013U */
4704 /* .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U */
4705 /* .. .. reg_ddrc_t_cke = 0x4 */
4706 /* .. .. ==> 0XF8006018[31:28] = 0x00000004U */
4707 /* .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U */
4708 /* .. .. */
4709 EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x44E354D2U),
4710 /* .. .. reg_ddrc_write_latency = 0x5 */
4711 /* .. .. ==> 0XF800601C[4:0] = 0x00000005U */
4712 /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U */
4713 /* .. .. reg_ddrc_rd2wr = 0x7 */
4714 /* .. .. ==> 0XF800601C[9:5] = 0x00000007U */
4715 /* .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U */
4716 /* .. .. reg_ddrc_wr2rd = 0xe */
4717 /* .. .. ==> 0XF800601C[14:10] = 0x0000000EU */
4718 /* .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U */
4719 /* .. .. reg_ddrc_t_xp = 0x4 */
4720 /* .. .. ==> 0XF800601C[19:15] = 0x00000004U */
4721 /* .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U */
4722 /* .. .. reg_ddrc_pad_pd = 0x0 */
4723 /* .. .. ==> 0XF800601C[22:20] = 0x00000000U */
4724 /* .. .. ==> MASK : 0x00700000U VAL : 0x00000000U */
4725 /* .. .. reg_ddrc_rd2pre = 0x4 */
4726 /* .. .. ==> 0XF800601C[27:23] = 0x00000004U */
4727 /* .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U */
4728 /* .. .. reg_ddrc_t_rcd = 0x7 */
4729 /* .. .. ==> 0XF800601C[31:28] = 0x00000007U */
4730 /* .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U */
4731 /* .. .. */
4732 EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0x720238E5U),
4733 /* .. .. reg_ddrc_t_ccd = 0x4 */
4734 /* .. .. ==> 0XF8006020[4:2] = 0x00000004U */
4735 /* .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U */
4736 /* .. .. reg_ddrc_t_rrd = 0x6 */
4737 /* .. .. ==> 0XF8006020[7:5] = 0x00000006U */
4738 /* .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U */
4739 /* .. .. reg_ddrc_refresh_margin = 0x2 */
4740 /* .. .. ==> 0XF8006020[11:8] = 0x00000002U */
4741 /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */
4742 /* .. .. reg_ddrc_t_rp = 0x7 */
4743 /* .. .. ==> 0XF8006020[15:12] = 0x00000007U */
4744 /* .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U */
4745 /* .. .. reg_ddrc_refresh_to_x32 = 0x8 */
4746 /* .. .. ==> 0XF8006020[20:16] = 0x00000008U */
4747 /* .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U */
4748 /* .. .. reg_ddrc_sdram = 0x1 */
4749 /* .. .. ==> 0XF8006020[21:21] = 0x00000001U */
4750 /* .. .. ==> MASK : 0x00200000U VAL : 0x00200000U */
4751 /* .. .. reg_ddrc_mobile = 0x0 */
4752 /* .. .. ==> 0XF8006020[22:22] = 0x00000000U */
4753 /* .. .. ==> MASK : 0x00400000U VAL : 0x00000000U */
4754 /* .. .. reg_ddrc_clock_stop_en = 0x0 */
4755 /* .. .. ==> 0XF8006020[23:23] = 0x00000000U */
4756 /* .. .. ==> MASK : 0x00800000U VAL : 0x00000000U */
4757 /* .. .. reg_ddrc_read_latency = 0x7 */
4758 /* .. .. ==> 0XF8006020[28:24] = 0x00000007U */
4759 /* .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U */
4760 /* .. .. reg_phy_mode_ddr1_ddr2 = 0x1 */
4761 /* .. .. ==> 0XF8006020[29:29] = 0x00000001U */
4762 /* .. .. ==> MASK : 0x20000000U VAL : 0x20000000U */
4763 /* .. .. reg_ddrc_dis_pad_pd = 0x0 */
4764 /* .. .. ==> 0XF8006020[30:30] = 0x00000000U */
4765 /* .. .. ==> MASK : 0x40000000U VAL : 0x00000000U */
4766 /* .. .. reg_ddrc_loopback = 0x0 */
4767 /* .. .. ==> 0XF8006020[31:31] = 0x00000000U */
4768 /* .. .. ==> MASK : 0x80000000U VAL : 0x00000000U */
4769 /* .. .. */
4770 EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU, 0x272872D0U),
4771 /* .. .. reg_ddrc_en_2t_timing_mode = 0x0 */
4772 /* .. .. ==> 0XF8006024[0:0] = 0x00000000U */
4773 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
4774 /* .. .. reg_ddrc_prefer_write = 0x0 */
4775 /* .. .. ==> 0XF8006024[1:1] = 0x00000000U */
4776 /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
4777 /* .. .. reg_ddrc_max_rank_rd = 0xf */
4778 /* .. .. ==> 0XF8006024[5:2] = 0x0000000FU */
4779 /* .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU */
4780 /* .. .. reg_ddrc_mr_wr = 0x0 */
4781 /* .. .. ==> 0XF8006024[6:6] = 0x00000000U */
4782 /* .. .. ==> MASK : 0x00000040U VAL : 0x00000000U */
4783 /* .. .. reg_ddrc_mr_addr = 0x0 */
4784 /* .. .. ==> 0XF8006024[8:7] = 0x00000000U */
4785 /* .. .. ==> MASK : 0x00000180U VAL : 0x00000000U */
4786 /* .. .. reg_ddrc_mr_data = 0x0 */
4787 /* .. .. ==> 0XF8006024[24:9] = 0x00000000U */
4788 /* .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U */
4789 /* .. .. ddrc_reg_mr_wr_busy = 0x0 */
4790 /* .. .. ==> 0XF8006024[25:25] = 0x00000000U */
4791 /* .. .. ==> MASK : 0x02000000U VAL : 0x00000000U */
4792 /* .. .. reg_ddrc_mr_type = 0x0 */
4793 /* .. .. ==> 0XF8006024[26:26] = 0x00000000U */
4794 /* .. .. ==> MASK : 0x04000000U VAL : 0x00000000U */
4795 /* .. .. reg_ddrc_mr_rdata_valid = 0x0 */
4796 /* .. .. ==> 0XF8006024[27:27] = 0x00000000U */
4797 /* .. .. ==> MASK : 0x08000000U VAL : 0x00000000U */
4798 /* .. .. */
4799 EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU, 0x0000003CU),
4800 /* .. .. reg_ddrc_final_wait_x32 = 0x7 */
4801 /* .. .. ==> 0XF8006028[6:0] = 0x00000007U */
4802 /* .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U */
4803 /* .. .. reg_ddrc_pre_ocd_x32 = 0x0 */
4804 /* .. .. ==> 0XF8006028[10:7] = 0x00000000U */
4805 /* .. .. ==> MASK : 0x00000780U VAL : 0x00000000U */
4806 /* .. .. reg_ddrc_t_mrd = 0x4 */
4807 /* .. .. ==> 0XF8006028[13:11] = 0x00000004U */
4808 /* .. .. ==> MASK : 0x00003800U VAL : 0x00002000U */
4809 /* .. .. */
4810 EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U),
4811 /* .. .. reg_ddrc_emr2 = 0x8 */
4812 /* .. .. ==> 0XF800602C[15:0] = 0x00000008U */
4813 /* .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U */
4814 /* .. .. reg_ddrc_emr3 = 0x0 */
4815 /* .. .. ==> 0XF800602C[31:16] = 0x00000000U */
4816 /* .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U */
4817 /* .. .. */
4818 EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000008U),
4819 /* .. .. reg_ddrc_mr = 0x930 */
4820 /* .. .. ==> 0XF8006030[15:0] = 0x00000930U */
4821 /* .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U */
4822 /* .. .. reg_ddrc_emr = 0x4 */
4823 /* .. .. ==> 0XF8006030[31:16] = 0x00000004U */
4824 /* .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U */
4825 /* .. .. */
4826 EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040930U),
4827 /* .. .. reg_ddrc_burst_rdwr = 0x4 */
4828 /* .. .. ==> 0XF8006034[3:0] = 0x00000004U */
4829 /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U */
Michal Simek264065f2016-03-03 13:25:03 +0100[diff] [blame]4830 /* .. .. reg_ddrc_pre_cke_x1024 = 0x167 */
4831 /* .. .. ==> 0XF8006034[13:4] = 0x00000167U */
4832 /* .. .. ==> MASK : 0x00003FF0U VAL : 0x00001670U */
Nathan Rossi4eeed0e2015-11-24 19:34:09 +1000[diff] [blame]4833 /* .. .. reg_ddrc_post_cke_x1024 = 0x1 */
4834 /* .. .. ==> 0XF8006034[25:16] = 0x00000001U */
4835 /* .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U */
4836 /* .. .. reg_ddrc_burstchop = 0x0 */
4837 /* .. .. ==> 0XF8006034[28:28] = 0x00000000U */
4838 /* .. .. ==> MASK : 0x10000000U VAL : 0x00000000U */
4839 /* .. .. */
Michal Simek264065f2016-03-03 13:25:03 +0100[diff] [blame]4840 EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x00011674U),
Nathan Rossi4eeed0e2015-11-24 19:34:09 +1000[diff] [blame]4841 /* .. .. reg_ddrc_force_low_pri_n = 0x0 */
4842 /* .. .. ==> 0XF8006038[0:0] = 0x00000000U */
4843 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
4844 /* .. .. reg_ddrc_dis_dq = 0x0 */
4845 /* .. .. ==> 0XF8006038[1:1] = 0x00000000U */
4846 /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
4847 /* .. .. reg_phy_debug_mode = 0x0 */
4848 /* .. .. ==> 0XF8006038[6:6] = 0x00000000U */
4849 /* .. .. ==> MASK : 0x00000040U VAL : 0x00000000U */
4850 /* .. .. reg_phy_wr_level_start = 0x0 */
4851 /* .. .. ==> 0XF8006038[7:7] = 0x00000000U */
4852 /* .. .. ==> MASK : 0x00000080U VAL : 0x00000000U */
4853 /* .. .. reg_phy_rd_level_start = 0x0 */
4854 /* .. .. ==> 0XF8006038[8:8] = 0x00000000U */
4855 /* .. .. ==> MASK : 0x00000100U VAL : 0x00000000U */
4856 /* .. .. reg_phy_dq0_wait_t = 0x0 */
4857 /* .. .. ==> 0XF8006038[12:9] = 0x00000000U */
4858 /* .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U */
4859 /* .. .. */
4860 EMIT_MASKWRITE(0XF8006038, 0x00001FC3U, 0x00000000U),
4861 /* .. .. reg_ddrc_addrmap_bank_b0 = 0x7 */
4862 /* .. .. ==> 0XF800603C[3:0] = 0x00000007U */
4863 /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U */
4864 /* .. .. reg_ddrc_addrmap_bank_b1 = 0x7 */
4865 /* .. .. ==> 0XF800603C[7:4] = 0x00000007U */
4866 /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U */
4867 /* .. .. reg_ddrc_addrmap_bank_b2 = 0x7 */
4868 /* .. .. ==> 0XF800603C[11:8] = 0x00000007U */
4869 /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U */
4870 /* .. .. reg_ddrc_addrmap_col_b5 = 0x0 */
4871 /* .. .. ==> 0XF800603C[15:12] = 0x00000000U */
4872 /* .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U */
4873 /* .. .. reg_ddrc_addrmap_col_b6 = 0x0 */
4874 /* .. .. ==> 0XF800603C[19:16] = 0x00000000U */
4875 /* .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U */
4876 /* .. .. */
4877 EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U),
4878 /* .. .. reg_ddrc_addrmap_col_b2 = 0x0 */
4879 /* .. .. ==> 0XF8006040[3:0] = 0x00000000U */
4880 /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U */
4881 /* .. .. reg_ddrc_addrmap_col_b3 = 0x0 */
4882 /* .. .. ==> 0XF8006040[7:4] = 0x00000000U */
4883 /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */
4884 /* .. .. reg_ddrc_addrmap_col_b4 = 0x0 */
4885 /* .. .. ==> 0XF8006040[11:8] = 0x00000000U */
4886 /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U */
4887 /* .. .. reg_ddrc_addrmap_col_b7 = 0x0 */
4888 /* .. .. ==> 0XF8006040[15:12] = 0x00000000U */
4889 /* .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U */
4890 /* .. .. reg_ddrc_addrmap_col_b8 = 0x0 */
4891 /* .. .. ==> 0XF8006040[19:16] = 0x00000000U */
4892 /* .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U */
4893 /* .. .. reg_ddrc_addrmap_col_b9 = 0xf */
4894 /* .. .. ==> 0XF8006040[23:20] = 0x0000000FU */
4895 /* .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U */
4896 /* .. .. reg_ddrc_addrmap_col_b10 = 0xf */
4897 /* .. .. ==> 0XF8006040[27:24] = 0x0000000FU */
4898 /* .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U */
4899 /* .. .. reg_ddrc_addrmap_col_b11 = 0xf */
4900 /* .. .. ==> 0XF8006040[31:28] = 0x0000000FU */
4901 /* .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U */
4902 /* .. .. */
4903 EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U),
4904 /* .. .. reg_ddrc_addrmap_row_b0 = 0x6 */
4905 /* .. .. ==> 0XF8006044[3:0] = 0x00000006U */
4906 /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U */
4907 /* .. .. reg_ddrc_addrmap_row_b1 = 0x6 */
4908 /* .. .. ==> 0XF8006044[7:4] = 0x00000006U */
4909 /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U */
4910 /* .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 */
4911 /* .. .. ==> 0XF8006044[11:8] = 0x00000006U */
4912 /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U */
4913 /* .. .. reg_ddrc_addrmap_row_b12 = 0x6 */
4914 /* .. .. ==> 0XF8006044[15:12] = 0x00000006U */
4915 /* .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U */
4916 /* .. .. reg_ddrc_addrmap_row_b13 = 0x6 */
4917 /* .. .. ==> 0XF8006044[19:16] = 0x00000006U */
4918 /* .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U */
4919 /* .. .. reg_ddrc_addrmap_row_b14 = 0xf */
4920 /* .. .. ==> 0XF8006044[23:20] = 0x0000000FU */
4921 /* .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U */
4922 /* .. .. reg_ddrc_addrmap_row_b15 = 0xf */
4923 /* .. .. ==> 0XF8006044[27:24] = 0x0000000FU */
4924 /* .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U */
4925 /* .. .. */
4926 EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0FF66666U),
4927 /* .. .. reg_ddrc_rank0_rd_odt = 0x0 */
4928 /* .. .. ==> 0XF8006048[2:0] = 0x00000000U */
4929 /* .. .. ==> MASK : 0x00000007U VAL : 0x00000000U */
4930 /* .. .. reg_ddrc_rank0_wr_odt = 0x1 */
4931 /* .. .. ==> 0XF8006048[5:3] = 0x00000001U */
4932 /* .. .. ==> MASK : 0x00000038U VAL : 0x00000008U */
4933 /* .. .. reg_ddrc_rank1_rd_odt = 0x1 */
4934 /* .. .. ==> 0XF8006048[8:6] = 0x00000001U */
4935 /* .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U */
4936 /* .. .. reg_ddrc_rank1_wr_odt = 0x1 */
4937 /* .. .. ==> 0XF8006048[11:9] = 0x00000001U */
4938 /* .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
4939 /* .. .. reg_phy_rd_local_odt = 0x0 */
4940 /* .. .. ==> 0XF8006048[13:12] = 0x00000000U */
4941 /* .. .. ==> MASK : 0x00003000U VAL : 0x00000000U */
4942 /* .. .. reg_phy_wr_local_odt = 0x3 */
4943 /* .. .. ==> 0XF8006048[15:14] = 0x00000003U */
4944 /* .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U */
4945 /* .. .. reg_phy_idle_local_odt = 0x3 */
4946 /* .. .. ==> 0XF8006048[17:16] = 0x00000003U */
4947 /* .. .. ==> MASK : 0x00030000U VAL : 0x00030000U */
4948 /* .. .. reg_ddrc_rank2_rd_odt = 0x0 */
4949 /* .. .. ==> 0XF8006048[20:18] = 0x00000000U */
4950 /* .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U */
4951 /* .. .. reg_ddrc_rank2_wr_odt = 0x0 */
4952 /* .. .. ==> 0XF8006048[23:21] = 0x00000000U */
4953 /* .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U */
4954 /* .. .. reg_ddrc_rank3_rd_odt = 0x0 */
4955 /* .. .. ==> 0XF8006048[26:24] = 0x00000000U */
4956 /* .. .. ==> MASK : 0x07000000U VAL : 0x00000000U */
4957 /* .. .. reg_ddrc_rank3_wr_odt = 0x0 */
4958 /* .. .. ==> 0XF8006048[29:27] = 0x00000000U */
4959 /* .. .. ==> MASK : 0x38000000U VAL : 0x00000000U */
4960 /* .. .. */
4961 EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU, 0x0003C248U),
4962 /* .. .. reg_phy_rd_cmd_to_data = 0x0 */
4963 /* .. .. ==> 0XF8006050[3:0] = 0x00000000U */
4964 /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U */
4965 /* .. .. reg_phy_wr_cmd_to_data = 0x0 */
4966 /* .. .. ==> 0XF8006050[7:4] = 0x00000000U */
4967 /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */
4968 /* .. .. reg_phy_rdc_we_to_re_delay = 0x8 */
4969 /* .. .. ==> 0XF8006050[11:8] = 0x00000008U */
4970 /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U */
4971 /* .. .. reg_phy_rdc_fifo_rst_disable = 0x0 */
4972 /* .. .. ==> 0XF8006050[15:15] = 0x00000000U */
4973 /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */
4974 /* .. .. reg_phy_use_fixed_re = 0x1 */
4975 /* .. .. ==> 0XF8006050[16:16] = 0x00000001U */
4976 /* .. .. ==> MASK : 0x00010000U VAL : 0x00010000U */
4977 /* .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 */
4978 /* .. .. ==> 0XF8006050[17:17] = 0x00000000U */
4979 /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
4980 /* .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 */
4981 /* .. .. ==> 0XF8006050[18:18] = 0x00000000U */
4982 /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
4983 /* .. .. reg_phy_clk_stall_level = 0x0 */
4984 /* .. .. ==> 0XF8006050[19:19] = 0x00000000U */
4985 /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */
4986 /* .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 */
4987 /* .. .. ==> 0XF8006050[27:24] = 0x00000007U */
4988 /* .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U */
4989 /* .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 */
4990 /* .. .. ==> 0XF8006050[31:28] = 0x00000007U */
4991 /* .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U */
4992 /* .. .. */
4993 EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U),
4994 /* .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1 */
4995 /* .. .. ==> 0XF8006058[7:0] = 0x00000001U */
4996 /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U */
4997 /* .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1 */
4998 /* .. .. ==> 0XF8006058[15:8] = 0x00000001U */
4999 /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U */
5000 /* .. .. reg_ddrc_dis_dll_calib = 0x0 */
5001 /* .. .. ==> 0XF8006058[16:16] = 0x00000000U */
5002 /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
5003 /* .. .. */
5004 EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU, 0x00000101U),
5005 /* .. .. reg_ddrc_rd_odt_delay = 0x3 */
5006 /* .. .. ==> 0XF800605C[3:0] = 0x00000003U */
5007 /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U */
5008 /* .. .. reg_ddrc_wr_odt_delay = 0x0 */
5009 /* .. .. ==> 0XF800605C[7:4] = 0x00000000U */
5010 /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */
5011 /* .. .. reg_ddrc_rd_odt_hold = 0x0 */
5012 /* .. .. ==> 0XF800605C[11:8] = 0x00000000U */
5013 /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U */
5014 /* .. .. reg_ddrc_wr_odt_hold = 0x5 */
5015 /* .. .. ==> 0XF800605C[15:12] = 0x00000005U */
5016 /* .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U */
5017 /* .. .. */
5018 EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U),
5019 /* .. .. reg_ddrc_pageclose = 0x0 */
5020 /* .. .. ==> 0XF8006060[0:0] = 0x00000000U */
5021 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
5022 /* .. .. reg_ddrc_lpr_num_entries = 0x1f */
5023 /* .. .. ==> 0XF8006060[6:1] = 0x0000001FU */
5024 /* .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU */
5025 /* .. .. reg_ddrc_auto_pre_en = 0x0 */
5026 /* .. .. ==> 0XF8006060[7:7] = 0x00000000U */
5027 /* .. .. ==> MASK : 0x00000080U VAL : 0x00000000U */
5028 /* .. .. reg_ddrc_refresh_update_level = 0x0 */
5029 /* .. .. ==> 0XF8006060[8:8] = 0x00000000U */
5030 /* .. .. ==> MASK : 0x00000100U VAL : 0x00000000U */
5031 /* .. .. reg_ddrc_dis_wc = 0x0 */
5032 /* .. .. ==> 0XF8006060[9:9] = 0x00000000U */
5033 /* .. .. ==> MASK : 0x00000200U VAL : 0x00000000U */
5034 /* .. .. reg_ddrc_dis_collision_page_opt = 0x0 */
5035 /* .. .. ==> 0XF8006060[10:10] = 0x00000000U */
5036 /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
5037 /* .. .. reg_ddrc_selfref_en = 0x0 */
5038 /* .. .. ==> 0XF8006060[12:12] = 0x00000000U */
5039 /* .. .. ==> MASK : 0x00001000U VAL : 0x00000000U */
5040 /* .. .. */
5041 EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU),
5042 /* .. .. reg_ddrc_go2critical_hysteresis = 0x0 */
5043 /* .. .. ==> 0XF8006064[12:5] = 0x00000000U */
5044 /* .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U */
5045 /* .. .. reg_arb_go2critical_en = 0x1 */
5046 /* .. .. ==> 0XF8006064[17:17] = 0x00000001U */
5047 /* .. .. ==> MASK : 0x00020000U VAL : 0x00020000U */
5048 /* .. .. */
5049 EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U),
5050 /* .. .. reg_ddrc_wrlvl_ww = 0x41 */
5051 /* .. .. ==> 0XF8006068[7:0] = 0x00000041U */
5052 /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U */
5053 /* .. .. reg_ddrc_rdlvl_rr = 0x41 */
5054 /* .. .. ==> 0XF8006068[15:8] = 0x00000041U */
5055 /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U */
5056 /* .. .. reg_ddrc_dfi_t_wlmrd = 0x28 */
5057 /* .. .. ==> 0XF8006068[25:16] = 0x00000028U */
5058 /* .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U */
5059 /* .. .. */
5060 EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284141U),
5061 /* .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 */
5062 /* .. .. ==> 0XF800606C[7:0] = 0x00000010U */
5063 /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U */
5064 /* .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 */
5065 /* .. .. ==> 0XF800606C[15:8] = 0x00000016U */
5066 /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U */
5067 /* .. .. */
5068 EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U),
5069 /* .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1 */
5070 /* .. .. ==> 0XF8006078[3:0] = 0x00000001U */
5071 /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U */
5072 /* .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1 */
5073 /* .. .. ==> 0XF8006078[7:4] = 0x00000001U */
5074 /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U */
5075 /* .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 */
5076 /* .. .. ==> 0XF8006078[11:8] = 0x00000001U */
5077 /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U */
5078 /* .. .. reg_ddrc_t_cksre = 0x6 */
5079 /* .. .. ==> 0XF8006078[15:12] = 0x00000006U */
5080 /* .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U */
5081 /* .. .. reg_ddrc_t_cksrx = 0x6 */
5082 /* .. .. ==> 0XF8006078[19:16] = 0x00000006U */
5083 /* .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U */
5084 /* .. .. reg_ddrc_t_ckesr = 0x4 */
5085 /* .. .. ==> 0XF8006078[25:20] = 0x00000004U */
5086 /* .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U */
5087 /* .. .. */
5088 EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU, 0x00466111U),
5089 /* .. .. reg_ddrc_t_ckpde = 0x2 */
5090 /* .. .. ==> 0XF800607C[3:0] = 0x00000002U */
5091 /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U */
5092 /* .. .. reg_ddrc_t_ckpdx = 0x2 */
5093 /* .. .. ==> 0XF800607C[7:4] = 0x00000002U */
5094 /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U */
5095 /* .. .. reg_ddrc_t_ckdpde = 0x2 */
5096 /* .. .. ==> 0XF800607C[11:8] = 0x00000002U */
5097 /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */
5098 /* .. .. reg_ddrc_t_ckdpdx = 0x2 */
5099 /* .. .. ==> 0XF800607C[15:12] = 0x00000002U */
5100 /* .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U */
5101 /* .. .. reg_ddrc_t_ckcsx = 0x3 */
5102 /* .. .. ==> 0XF800607C[19:16] = 0x00000003U */
5103 /* .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U */
5104 /* .. .. */
5105 EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU, 0x00032222U),
5106 /* .. .. refresh_timer0_start_value_x32 = 0x0 */
5107 /* .. .. ==> 0XF80060A0[11:0] = 0x00000000U */
5108 /* .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U */
5109 /* .. .. refresh_timer1_start_value_x32 = 0x8 */
5110 /* .. .. ==> 0XF80060A0[23:12] = 0x00000008U */
5111 /* .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U */
5112 /* .. .. */
5113 EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU, 0x00008000U),
5114 /* .. .. reg_ddrc_dis_auto_zq = 0x0 */
5115 /* .. .. ==> 0XF80060A4[0:0] = 0x00000000U */
5116 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
5117 /* .. .. reg_ddrc_ddr3 = 0x1 */
5118 /* .. .. ==> 0XF80060A4[1:1] = 0x00000001U */
5119 /* .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */
5120 /* .. .. reg_ddrc_t_mod = 0x200 */
5121 /* .. .. ==> 0XF80060A4[11:2] = 0x00000200U */
5122 /* .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U */
5123 /* .. .. reg_ddrc_t_zq_long_nop = 0x200 */
5124 /* .. .. ==> 0XF80060A4[21:12] = 0x00000200U */
5125 /* .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U */
5126 /* .. .. reg_ddrc_t_zq_short_nop = 0x40 */
5127 /* .. .. ==> 0XF80060A4[31:22] = 0x00000040U */
5128 /* .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U */
5129 /* .. .. */
5130 EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U),
5131 /* .. .. t_zq_short_interval_x1024 = 0xc845 */
5132 /* .. .. ==> 0XF80060A8[19:0] = 0x0000C845U */
5133 /* .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000C845U */
5134 /* .. .. dram_rstn_x1024 = 0x67 */
5135 /* .. .. ==> 0XF80060A8[27:20] = 0x00000067U */
5136 /* .. .. ==> MASK : 0x0FF00000U VAL : 0x06700000U */
5137 /* .. .. */
5138 EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0670C845U),
5139 /* .. .. deeppowerdown_en = 0x0 */
5140 /* .. .. ==> 0XF80060AC[0:0] = 0x00000000U */
5141 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
5142 /* .. .. deeppowerdown_to_x1024 = 0xff */
5143 /* .. .. ==> 0XF80060AC[8:1] = 0x000000FFU */
5144 /* .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU */
5145 /* .. .. */
5146 EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU),
5147 /* .. .. dfi_wrlvl_max_x1024 = 0xfff */
5148 /* .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU */
5149 /* .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU */
5150 /* .. .. dfi_rdlvl_max_x1024 = 0xfff */
5151 /* .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU */
5152 /* .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U */
5153 /* .. .. ddrc_reg_twrlvl_max_error = 0x0 */
5154 /* .. .. ==> 0XF80060B0[24:24] = 0x00000000U */
5155 /* .. .. ==> MASK : 0x01000000U VAL : 0x00000000U */
5156 /* .. .. ddrc_reg_trdlvl_max_error = 0x0 */
5157 /* .. .. ==> 0XF80060B0[25:25] = 0x00000000U */
5158 /* .. .. ==> MASK : 0x02000000U VAL : 0x00000000U */
5159 /* .. .. reg_ddrc_dfi_wr_level_en = 0x1 */
5160 /* .. .. ==> 0XF80060B0[26:26] = 0x00000001U */
5161 /* .. .. ==> MASK : 0x04000000U VAL : 0x04000000U */
5162 /* .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 */
5163 /* .. .. ==> 0XF80060B0[27:27] = 0x00000001U */
5164 /* .. .. ==> MASK : 0x08000000U VAL : 0x08000000U */
5165 /* .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 */
5166 /* .. .. ==> 0XF80060B0[28:28] = 0x00000001U */
5167 /* .. .. ==> MASK : 0x10000000U VAL : 0x10000000U */
5168 /* .. .. */
5169 EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
5170 /* .. .. reg_ddrc_2t_delay = 0x0 */
5171 /* .. .. ==> 0XF80060B4[8:0] = 0x00000000U */
5172 /* .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U */
5173 /* .. .. reg_ddrc_skip_ocd = 0x1 */
5174 /* .. .. ==> 0XF80060B4[9:9] = 0x00000001U */
5175 /* .. .. ==> MASK : 0x00000200U VAL : 0x00000200U */
5176 /* .. .. reg_ddrc_dis_pre_bypass = 0x0 */
5177 /* .. .. ==> 0XF80060B4[10:10] = 0x00000000U */
5178 /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
5179 /* .. .. */
5180 EMIT_MASKWRITE(0XF80060B4, 0x000007FFU, 0x00000200U),
5181 /* .. .. reg_ddrc_dfi_t_rddata_en = 0x6 */
5182 /* .. .. ==> 0XF80060B8[4:0] = 0x00000006U */
5183 /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U */
5184 /* .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 */
5185 /* .. .. ==> 0XF80060B8[14:5] = 0x00000003U */
5186 /* .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U */
5187 /* .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 */
5188 /* .. .. ==> 0XF80060B8[24:15] = 0x00000040U */
5189 /* .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U */
5190 /* .. .. */
5191 EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x00200066U),
5192 /* .. .. START: RESET ECC ERROR */
5193 /* .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 */
5194 /* .. .. ==> 0XF80060C4[0:0] = 0x00000001U */
5195 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
5196 /* .. .. Clear_Correctable_DRAM_ECC_error = 1 */
5197 /* .. .. ==> 0XF80060C4[1:1] = 0x00000001U */
5198 /* .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */
5199 /* .. .. */
5200 EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000003U),
5201 /* .. .. FINISH: RESET ECC ERROR */
5202 /* .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 */
5203 /* .. .. ==> 0XF80060C4[0:0] = 0x00000000U */
5204 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
5205 /* .. .. Clear_Correctable_DRAM_ECC_error = 0x0 */
5206 /* .. .. ==> 0XF80060C4[1:1] = 0x00000000U */
5207 /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
5208 /* .. .. */
5209 EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U),
5210 /* .. .. CORR_ECC_LOG_VALID = 0x0 */
5211 /* .. .. ==> 0XF80060C8[0:0] = 0x00000000U */
5212 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
5213 /* .. .. ECC_CORRECTED_BIT_NUM = 0x0 */
5214 /* .. .. ==> 0XF80060C8[7:1] = 0x00000000U */
5215 /* .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U */
5216 /* .. .. */
5217 EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U),
5218 /* .. .. UNCORR_ECC_LOG_VALID = 0x0 */
5219 /* .. .. ==> 0XF80060DC[0:0] = 0x00000000U */
5220 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
5221 /* .. .. */
5222 EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U),
5223 /* .. .. STAT_NUM_CORR_ERR = 0x0 */
5224 /* .. .. ==> 0XF80060F0[15:8] = 0x00000000U */
5225 /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U */
5226 /* .. .. STAT_NUM_UNCORR_ERR = 0x0 */
5227 /* .. .. ==> 0XF80060F0[7:0] = 0x00000000U */
5228 /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U */
5229 /* .. .. */
5230 EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U),
5231 /* .. .. reg_ddrc_ecc_mode = 0x0 */
5232 /* .. .. ==> 0XF80060F4[2:0] = 0x00000000U */
5233 /* .. .. ==> MASK : 0x00000007U VAL : 0x00000000U */
5234 /* .. .. reg_ddrc_dis_scrub = 0x1 */
5235 /* .. .. ==> 0XF80060F4[3:3] = 0x00000001U */
5236 /* .. .. ==> MASK : 0x00000008U VAL : 0x00000008U */
5237 /* .. .. */
5238 EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U),
5239 /* .. .. reg_phy_dif_on = 0x0 */
5240 /* .. .. ==> 0XF8006114[3:0] = 0x00000000U */
5241 /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U */
5242 /* .. .. reg_phy_dif_off = 0x0 */
5243 /* .. .. ==> 0XF8006114[7:4] = 0x00000000U */
5244 /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */
5245 /* .. .. */
5246 EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U),
5247 /* .. .. reg_phy_data_slice_in_use = 0x1 */
5248 /* .. .. ==> 0XF8006118[0:0] = 0x00000001U */
5249 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
5250 /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
5251 /* .. .. ==> 0XF8006118[1:1] = 0x00000000U */
5252 /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
5253 /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
5254 /* .. .. ==> 0XF8006118[2:2] = 0x00000000U */
5255 /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
5256 /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
5257 /* .. .. ==> 0XF8006118[3:3] = 0x00000000U */
5258 /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
5259 /* .. .. reg_phy_board_lpbk_tx = 0x0 */
5260 /* .. .. ==> 0XF8006118[4:4] = 0x00000000U */
5261 /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
5262 /* .. .. reg_phy_board_lpbk_rx = 0x0 */
5263 /* .. .. ==> 0XF8006118[5:5] = 0x00000000U */
5264 /* .. .. ==> MASK : 0x00000020U VAL : 0x00000000U */
5265 /* .. .. reg_phy_bist_shift_dq = 0x0 */
5266 /* .. .. ==> 0XF8006118[14:6] = 0x00000000U */
5267 /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */
5268 /* .. .. reg_phy_bist_err_clr = 0x0 */
5269 /* .. .. ==> 0XF8006118[23:15] = 0x00000000U */
5270 /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */
5271 /* .. .. reg_phy_dq_offset = 0x40 */
5272 /* .. .. ==> 0XF8006118[30:24] = 0x00000040U */
5273 /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */
5274 /* .. .. */
5275 EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU, 0x40000001U),
5276 /* .. .. reg_phy_data_slice_in_use = 0x1 */
5277 /* .. .. ==> 0XF800611C[0:0] = 0x00000001U */
5278 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
5279 /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
5280 /* .. .. ==> 0XF800611C[1:1] = 0x00000000U */
5281 /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
5282 /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
5283 /* .. .. ==> 0XF800611C[2:2] = 0x00000000U */
5284 /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
5285 /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
5286 /* .. .. ==> 0XF800611C[3:3] = 0x00000000U */
5287 /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
5288 /* .. .. reg_phy_board_lpbk_tx = 0x0 */
5289 /* .. .. ==> 0XF800611C[4:4] = 0x00000000U */
5290 /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
5291 /* .. .. reg_phy_board_lpbk_rx = 0x0 */
5292 /* .. .. ==> 0XF800611C[5:5] = 0x00000000U */
5293 /* .. .. ==> MASK : 0x00000020U VAL : 0x00000000U */
5294 /* .. .. reg_phy_bist_shift_dq = 0x0 */
5295 /* .. .. ==> 0XF800611C[14:6] = 0x00000000U */
5296 /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */
5297 /* .. .. reg_phy_bist_err_clr = 0x0 */
5298 /* .. .. ==> 0XF800611C[23:15] = 0x00000000U */
5299 /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */
5300 /* .. .. reg_phy_dq_offset = 0x40 */
5301 /* .. .. ==> 0XF800611C[30:24] = 0x00000040U */
5302 /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */
5303 /* .. .. */
5304 EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU, 0x40000001U),
5305 /* .. .. reg_phy_data_slice_in_use = 0x1 */
5306 /* .. .. ==> 0XF8006120[0:0] = 0x00000001U */
5307 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
5308 /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
5309 /* .. .. ==> 0XF8006120[1:1] = 0x00000000U */
5310 /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
5311 /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
5312 /* .. .. ==> 0XF8006120[2:2] = 0x00000000U */
5313 /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
5314 /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
5315 /* .. .. ==> 0XF8006120[3:3] = 0x00000000U */
5316 /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
5317 /* .. .. reg_phy_board_lpbk_tx = 0x0 */
5318 /* .. .. ==> 0XF8006120[4:4] = 0x00000000U */
5319 /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
5320 /* .. .. reg_phy_board_lpbk_rx = 0x0 */
5321 /* .. .. ==> 0XF8006120[5:5] = 0x00000000U */
5322 /* .. .. ==> MASK : 0x00000020U VAL : 0x00000000U */
5323 /* .. .. reg_phy_bist_shift_dq = 0x0 */
5324 /* .. .. ==> 0XF8006120[14:6] = 0x00000000U */
5325 /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */
5326 /* .. .. reg_phy_bist_err_clr = 0x0 */
5327 /* .. .. ==> 0XF8006120[23:15] = 0x00000000U */
5328 /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */
5329 /* .. .. reg_phy_dq_offset = 0x40 */
5330 /* .. .. ==> 0XF8006120[30:24] = 0x00000040U */
5331 /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */
5332 /* .. .. reg_phy_data_slice_in_use = 0x1 */
5333 /* .. .. ==> 0XF8006120[0:0] = 0x00000001U */
5334 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
5335 /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
5336 /* .. .. ==> 0XF8006120[1:1] = 0x00000000U */
5337 /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
5338 /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
5339 /* .. .. ==> 0XF8006120[2:2] = 0x00000000U */
5340 /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
5341 /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
5342 /* .. .. ==> 0XF8006120[3:3] = 0x00000000U */
5343 /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
5344 /* .. .. reg_phy_board_lpbk_tx = 0x0 */
5345 /* .. .. ==> 0XF8006120[4:4] = 0x00000000U */
5346 /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
5347 /* .. .. reg_phy_board_lpbk_rx = 0x0 */
5348 /* .. .. ==> 0XF8006120[5:5] = 0x00000000U */
5349 /* .. .. ==> MASK : 0x00000020U VAL : 0x00000000U */
5350 /* .. .. reg_phy_bist_shift_dq = 0x0 */
5351 /* .. .. ==> 0XF8006120[14:6] = 0x00000000U */
5352 /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */
5353 /* .. .. reg_phy_bist_err_clr = 0x0 */
5354 /* .. .. ==> 0XF8006120[23:15] = 0x00000000U */
5355 /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */
5356 /* .. .. reg_phy_dq_offset = 0x40 */
5357 /* .. .. ==> 0XF8006120[30:24] = 0x00000040U */
5358 /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */
5359 /* .. .. */
5360 EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU, 0x40000001U),
5361 /* .. .. reg_phy_data_slice_in_use = 0x1 */
5362 /* .. .. ==> 0XF8006124[0:0] = 0x00000001U */
5363 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
5364 /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
5365 /* .. .. ==> 0XF8006124[1:1] = 0x00000000U */
5366 /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
5367 /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
5368 /* .. .. ==> 0XF8006124[2:2] = 0x00000000U */
5369 /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
5370 /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
5371 /* .. .. ==> 0XF8006124[3:3] = 0x00000000U */
5372 /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
5373 /* .. .. reg_phy_board_lpbk_tx = 0x0 */
5374 /* .. .. ==> 0XF8006124[4:4] = 0x00000000U */
5375 /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
5376 /* .. .. reg_phy_board_lpbk_rx = 0x0 */
5377 /* .. .. ==> 0XF8006124[5:5] = 0x00000000U */
5378 /* .. .. ==> MASK : 0x00000020U VAL : 0x00000000U */
5379 /* .. .. reg_phy_bist_shift_dq = 0x0 */
5380 /* .. .. ==> 0XF8006124[14:6] = 0x00000000U */
5381 /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */
5382 /* .. .. reg_phy_bist_err_clr = 0x0 */
5383 /* .. .. ==> 0XF8006124[23:15] = 0x00000000U */
5384 /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */
5385 /* .. .. reg_phy_dq_offset = 0x40 */
5386 /* .. .. ==> 0XF8006124[30:24] = 0x00000040U */
5387 /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */
5388 /* .. .. */
5389 EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU, 0x40000001U),
5390 /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
5391 /* .. .. ==> 0XF800612C[9:0] = 0x00000000U */
5392 /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */
5393 /* .. .. reg_phy_gatelvl_init_ratio = 0x8f */
5394 /* .. .. ==> 0XF800612C[19:10] = 0x0000008FU */
5395 /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00023C00U */
5396 /* .. .. */
5397 EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x00023C00U),
5398 /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
5399 /* .. .. ==> 0XF8006130[9:0] = 0x00000000U */
5400 /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */
5401 /* .. .. reg_phy_gatelvl_init_ratio = 0x8a */
5402 /* .. .. ==> 0XF8006130[19:10] = 0x0000008AU */
5403 /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00022800U */
5404 /* .. .. */
5405 EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x00022800U),
5406 /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
5407 /* .. .. ==> 0XF8006134[9:0] = 0x00000000U */
5408 /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */
5409 /* .. .. reg_phy_gatelvl_init_ratio = 0x8b */
5410 /* .. .. ==> 0XF8006134[19:10] = 0x0000008BU */
5411 /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00022C00U */
5412 /* .. .. */
5413 EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x00022C00U),
5414 /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
5415 /* .. .. ==> 0XF8006138[9:0] = 0x00000000U */
5416 /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */
5417 /* .. .. reg_phy_gatelvl_init_ratio = 0x92 */
5418 /* .. .. ==> 0XF8006138[19:10] = 0x00000092U */
5419 /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00024800U */
5420 /* .. .. */
5421 EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x00024800U),
5422 /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
5423 /* .. .. ==> 0XF8006140[9:0] = 0x00000035U */
5424 /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */
5425 /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
5426 /* .. .. ==> 0XF8006140[10:10] = 0x00000000U */
5427 /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
5428 /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
5429 /* .. .. ==> 0XF8006140[19:11] = 0x00000000U */
5430 /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
5431 /* .. .. */
5432 EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U),
5433 /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
5434 /* .. .. ==> 0XF8006144[9:0] = 0x00000035U */
5435 /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */
5436 /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
5437 /* .. .. ==> 0XF8006144[10:10] = 0x00000000U */
5438 /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
5439 /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
5440 /* .. .. ==> 0XF8006144[19:11] = 0x00000000U */
5441 /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
5442 /* .. .. */
5443 EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U),
5444 /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
5445 /* .. .. ==> 0XF8006148[9:0] = 0x00000035U */
5446 /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */
5447 /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
5448 /* .. .. ==> 0XF8006148[10:10] = 0x00000000U */
5449 /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
5450 /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
5451 /* .. .. ==> 0XF8006148[19:11] = 0x00000000U */
5452 /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
5453 /* .. .. */
5454 EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U),
5455 /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
5456 /* .. .. ==> 0XF800614C[9:0] = 0x00000035U */
5457 /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */
5458 /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
5459 /* .. .. ==> 0XF800614C[10:10] = 0x00000000U */
5460 /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
5461 /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
5462 /* .. .. ==> 0XF800614C[19:11] = 0x00000000U */
5463 /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
5464 /* .. .. */
5465 EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U),
5466 /* .. .. reg_phy_wr_dqs_slave_ratio = 0x77 */
5467 /* .. .. ==> 0XF8006154[9:0] = 0x00000077U */
5468 /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000077U */
5469 /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
5470 /* .. .. ==> 0XF8006154[10:10] = 0x00000000U */
5471 /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
5472 /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
5473 /* .. .. ==> 0XF8006154[19:11] = 0x00000000U */
5474 /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
5475 /* .. .. */
5476 EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x00000077U),
5477 /* .. .. reg_phy_wr_dqs_slave_ratio = 0x7c */
5478 /* .. .. ==> 0XF8006158[9:0] = 0x0000007CU */
5479 /* .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU */
5480 /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
5481 /* .. .. ==> 0XF8006158[10:10] = 0x00000000U */
5482 /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
5483 /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
5484 /* .. .. ==> 0XF8006158[19:11] = 0x00000000U */
5485 /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
5486 /* .. .. */
5487 EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x0000007CU),
5488 /* .. .. reg_phy_wr_dqs_slave_ratio = 0x7c */
5489 /* .. .. ==> 0XF800615C[9:0] = 0x0000007CU */
5490 /* .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU */
5491 /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
5492 /* .. .. ==> 0XF800615C[10:10] = 0x00000000U */
5493 /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
5494 /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
5495 /* .. .. ==> 0XF800615C[19:11] = 0x00000000U */
5496 /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
5497 /* .. .. */
5498 EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x0000007CU),
5499 /* .. .. reg_phy_wr_dqs_slave_ratio = 0x75 */
5500 /* .. .. ==> 0XF8006160[9:0] = 0x00000075U */
5501 /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000075U */
5502 /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
5503 /* .. .. ==> 0XF8006160[10:10] = 0x00000000U */
5504 /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
5505 /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
5506 /* .. .. ==> 0XF8006160[19:11] = 0x00000000U */
5507 /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
5508 /* .. .. */
5509 EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x00000075U),
5510 /* .. .. reg_phy_fifo_we_slave_ratio = 0xe4 */
5511 /* .. .. ==> 0XF8006168[10:0] = 0x000000E4U */
5512 /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000E4U */
5513 /* .. .. reg_phy_fifo_we_in_force = 0x0 */
5514 /* .. .. ==> 0XF8006168[11:11] = 0x00000000U */
5515 /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */
5516 /* .. .. reg_phy_fifo_we_in_delay = 0x0 */
5517 /* .. .. ==> 0XF8006168[20:12] = 0x00000000U */
5518 /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */
5519 /* .. .. */
5520 EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000E4U),
5521 /* .. .. reg_phy_fifo_we_slave_ratio = 0xdf */
5522 /* .. .. ==> 0XF800616C[10:0] = 0x000000DFU */
5523 /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000DFU */
5524 /* .. .. reg_phy_fifo_we_in_force = 0x0 */
5525 /* .. .. ==> 0XF800616C[11:11] = 0x00000000U */
5526 /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */
5527 /* .. .. reg_phy_fifo_we_in_delay = 0x0 */
5528 /* .. .. ==> 0XF800616C[20:12] = 0x00000000U */
5529 /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */
5530 /* .. .. */
5531 EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000DFU),
5532 /* .. .. reg_phy_fifo_we_slave_ratio = 0xe0 */
5533 /* .. .. ==> 0XF8006170[10:0] = 0x000000E0U */
5534 /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000E0U */
5535 /* .. .. reg_phy_fifo_we_in_force = 0x0 */
5536 /* .. .. ==> 0XF8006170[11:11] = 0x00000000U */
5537 /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */
5538 /* .. .. reg_phy_fifo_we_in_delay = 0x0 */
5539 /* .. .. ==> 0XF8006170[20:12] = 0x00000000U */
5540 /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */
5541 /* .. .. */
5542 EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000E0U),
5543 /* .. .. reg_phy_fifo_we_slave_ratio = 0xe7 */
5544 /* .. .. ==> 0XF8006174[10:0] = 0x000000E7U */
5545 /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000E7U */
5546 /* .. .. reg_phy_fifo_we_in_force = 0x0 */
5547 /* .. .. ==> 0XF8006174[11:11] = 0x00000000U */
5548 /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */
5549 /* .. .. reg_phy_fifo_we_in_delay = 0x0 */
5550 /* .. .. ==> 0XF8006174[20:12] = 0x00000000U */
5551 /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */
5552 /* .. .. */
5553 EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000E7U),
5554 /* .. .. reg_phy_wr_data_slave_ratio = 0xb7 */
5555 /* .. .. ==> 0XF800617C[9:0] = 0x000000B7U */
5556 /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000B7U */
5557 /* .. .. reg_phy_wr_data_slave_force = 0x0 */
5558 /* .. .. ==> 0XF800617C[10:10] = 0x00000000U */
5559 /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
5560 /* .. .. reg_phy_wr_data_slave_delay = 0x0 */
5561 /* .. .. ==> 0XF800617C[19:11] = 0x00000000U */
5562 /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
5563 /* .. .. */
5564 EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000B7U),
5565 /* .. .. reg_phy_wr_data_slave_ratio = 0xbc */
5566 /* .. .. ==> 0XF8006180[9:0] = 0x000000BCU */
5567 /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU */
5568 /* .. .. reg_phy_wr_data_slave_force = 0x0 */
5569 /* .. .. ==> 0XF8006180[10:10] = 0x00000000U */
5570 /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
5571 /* .. .. reg_phy_wr_data_slave_delay = 0x0 */
5572 /* .. .. ==> 0XF8006180[19:11] = 0x00000000U */
5573 /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
5574 /* .. .. */
5575 EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000BCU),
5576 /* .. .. reg_phy_wr_data_slave_ratio = 0xbc */
5577 /* .. .. ==> 0XF8006184[9:0] = 0x000000BCU */
5578 /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU */
5579 /* .. .. reg_phy_wr_data_slave_force = 0x0 */
5580 /* .. .. ==> 0XF8006184[10:10] = 0x00000000U */
5581 /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
5582 /* .. .. reg_phy_wr_data_slave_delay = 0x0 */
5583 /* .. .. ==> 0XF8006184[19:11] = 0x00000000U */
5584 /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
5585 /* .. .. */
5586 EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000BCU),
5587 /* .. .. reg_phy_wr_data_slave_ratio = 0xb5 */
5588 /* .. .. ==> 0XF8006188[9:0] = 0x000000B5U */
5589 /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000B5U */
5590 /* .. .. reg_phy_wr_data_slave_force = 0x0 */
5591 /* .. .. ==> 0XF8006188[10:10] = 0x00000000U */
5592 /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
5593 /* .. .. reg_phy_wr_data_slave_delay = 0x0 */
5594 /* .. .. ==> 0XF8006188[19:11] = 0x00000000U */
5595 /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
5596 /* .. .. */
5597 EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000B5U),
5598 /* .. .. reg_phy_loopback = 0x0 */
5599 /* .. .. ==> 0XF8006190[0:0] = 0x00000000U */
5600 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
5601 /* .. .. reg_phy_bl2 = 0x0 */
5602 /* .. .. ==> 0XF8006190[1:1] = 0x00000000U */
5603 /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
5604 /* .. .. reg_phy_at_spd_atpg = 0x0 */
5605 /* .. .. ==> 0XF8006190[2:2] = 0x00000000U */
5606 /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
5607 /* .. .. reg_phy_bist_enable = 0x0 */
5608 /* .. .. ==> 0XF8006190[3:3] = 0x00000000U */
5609 /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
5610 /* .. .. reg_phy_bist_force_err = 0x0 */
5611 /* .. .. ==> 0XF8006190[4:4] = 0x00000000U */
5612 /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
5613 /* .. .. reg_phy_bist_mode = 0x0 */
5614 /* .. .. ==> 0XF8006190[6:5] = 0x00000000U */
5615 /* .. .. ==> MASK : 0x00000060U VAL : 0x00000000U */
5616 /* .. .. reg_phy_invert_clkout = 0x1 */
5617 /* .. .. ==> 0XF8006190[7:7] = 0x00000001U */
5618 /* .. .. ==> MASK : 0x00000080U VAL : 0x00000080U */
5619 /* .. .. reg_phy_all_dq_mpr_rd_resp = 0x0 */
5620 /* .. .. ==> 0XF8006190[8:8] = 0x00000000U */
5621 /* .. .. ==> MASK : 0x00000100U VAL : 0x00000000U */
5622 /* .. .. reg_phy_sel_logic = 0x0 */
5623 /* .. .. ==> 0XF8006190[9:9] = 0x00000000U */
5624 /* .. .. ==> MASK : 0x00000200U VAL : 0x00000000U */
5625 /* .. .. reg_phy_ctrl_slave_ratio = 0x100 */
5626 /* .. .. ==> 0XF8006190[19:10] = 0x00000100U */
5627 /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U */
5628 /* .. .. reg_phy_ctrl_slave_force = 0x0 */
5629 /* .. .. ==> 0XF8006190[20:20] = 0x00000000U */
5630 /* .. .. ==> MASK : 0x00100000U VAL : 0x00000000U */
5631 /* .. .. reg_phy_ctrl_slave_delay = 0x0 */
5632 /* .. .. ==> 0XF8006190[27:21] = 0x00000000U */
5633 /* .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U */
5634 /* .. .. reg_phy_use_rank0_delays = 0x1 */
5635 /* .. .. ==> 0XF8006190[28:28] = 0x00000001U */
5636 /* .. .. ==> MASK : 0x10000000U VAL : 0x10000000U */
5637 /* .. .. reg_phy_lpddr = 0x0 */
5638 /* .. .. ==> 0XF8006190[29:29] = 0x00000000U */
5639 /* .. .. ==> MASK : 0x20000000U VAL : 0x00000000U */
5640 /* .. .. reg_phy_cmd_latency = 0x0 */
5641 /* .. .. ==> 0XF8006190[30:30] = 0x00000000U */
5642 /* .. .. ==> MASK : 0x40000000U VAL : 0x00000000U */
5643 /* .. .. reg_phy_int_lpbk = 0x0 */
5644 /* .. .. ==> 0XF8006190[31:31] = 0x00000000U */
5645 /* .. .. ==> MASK : 0x80000000U VAL : 0x00000000U */
5646 /* .. .. */
5647 EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU, 0x10040080U),
5648 /* .. .. reg_phy_wr_rl_delay = 0x2 */
5649 /* .. .. ==> 0XF8006194[4:0] = 0x00000002U */
5650 /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U */
5651 /* .. .. reg_phy_rd_rl_delay = 0x4 */
5652 /* .. .. ==> 0XF8006194[9:5] = 0x00000004U */
5653 /* .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U */
5654 /* .. .. reg_phy_dll_lock_diff = 0xf */
5655 /* .. .. ==> 0XF8006194[13:10] = 0x0000000FU */
5656 /* .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U */
5657 /* .. .. reg_phy_use_wr_level = 0x1 */
5658 /* .. .. ==> 0XF8006194[14:14] = 0x00000001U */
5659 /* .. .. ==> MASK : 0x00004000U VAL : 0x00004000U */
5660 /* .. .. reg_phy_use_rd_dqs_gate_level = 0x1 */
5661 /* .. .. ==> 0XF8006194[15:15] = 0x00000001U */
5662 /* .. .. ==> MASK : 0x00008000U VAL : 0x00008000U */
5663 /* .. .. reg_phy_use_rd_data_eye_level = 0x1 */
5664 /* .. .. ==> 0XF8006194[16:16] = 0x00000001U */
5665 /* .. .. ==> MASK : 0x00010000U VAL : 0x00010000U */
5666 /* .. .. reg_phy_dis_calib_rst = 0x0 */
5667 /* .. .. ==> 0XF8006194[17:17] = 0x00000000U */
5668 /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
5669 /* .. .. reg_phy_ctrl_slave_delay = 0x0 */
5670 /* .. .. ==> 0XF8006194[19:18] = 0x00000000U */
5671 /* .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U */
5672 /* .. .. */
5673 EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FC82U),
5674 /* .. .. reg_arb_page_addr_mask = 0x0 */
5675 /* .. .. ==> 0XF8006204[31:0] = 0x00000000U */
5676 /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */
5677 /* .. .. */
5678 EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U),
5679 /* .. .. reg_arb_pri_wr_portn = 0x3ff */
5680 /* .. .. ==> 0XF8006208[9:0] = 0x000003FFU */
5681 /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
5682 /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
5683 /* .. .. ==> 0XF8006208[16:16] = 0x00000000U */
5684 /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
5685 /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
5686 /* .. .. ==> 0XF8006208[17:17] = 0x00000000U */
5687 /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
5688 /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
5689 /* .. .. ==> 0XF8006208[18:18] = 0x00000000U */
5690 /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
5691 /* .. .. reg_arb_dis_rmw_portn = 0x1 */
5692 /* .. .. ==> 0XF8006208[19:19] = 0x00000001U */
5693 /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */
5694 /* .. .. */
5695 EMIT_MASKWRITE(0XF8006208, 0x000F03FFU, 0x000803FFU),
5696 /* .. .. reg_arb_pri_wr_portn = 0x3ff */
5697 /* .. .. ==> 0XF800620C[9:0] = 0x000003FFU */
5698 /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
5699 /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
5700 /* .. .. ==> 0XF800620C[16:16] = 0x00000000U */
5701 /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
5702 /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
5703 /* .. .. ==> 0XF800620C[17:17] = 0x00000000U */
5704 /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
5705 /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
5706 /* .. .. ==> 0XF800620C[18:18] = 0x00000000U */
5707 /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
5708 /* .. .. reg_arb_dis_rmw_portn = 0x1 */
5709 /* .. .. ==> 0XF800620C[19:19] = 0x00000001U */
5710 /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */
5711 /* .. .. */
5712 EMIT_MASKWRITE(0XF800620C, 0x000F03FFU, 0x000803FFU),
5713 /* .. .. reg_arb_pri_wr_portn = 0x3ff */
5714 /* .. .. ==> 0XF8006210[9:0] = 0x000003FFU */
5715 /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
5716 /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
5717 /* .. .. ==> 0XF8006210[16:16] = 0x00000000U */
5718 /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
5719 /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
5720 /* .. .. ==> 0XF8006210[17:17] = 0x00000000U */
5721 /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
5722 /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
5723 /* .. .. ==> 0XF8006210[18:18] = 0x00000000U */
5724 /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
5725 /* .. .. reg_arb_dis_rmw_portn = 0x1 */
5726 /* .. .. ==> 0XF8006210[19:19] = 0x00000001U */
5727 /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */
5728 /* .. .. */
5729 EMIT_MASKWRITE(0XF8006210, 0x000F03FFU, 0x000803FFU),
5730 /* .. .. reg_arb_pri_wr_portn = 0x3ff */
5731 /* .. .. ==> 0XF8006214[9:0] = 0x000003FFU */
5732 /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
5733 /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
5734 /* .. .. ==> 0XF8006214[16:16] = 0x00000000U */
5735 /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
5736 /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
5737 /* .. .. ==> 0XF8006214[17:17] = 0x00000000U */
5738 /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
5739 /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
5740 /* .. .. ==> 0XF8006214[18:18] = 0x00000000U */
5741 /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
5742 /* .. .. reg_arb_dis_rmw_portn = 0x1 */
5743 /* .. .. ==> 0XF8006214[19:19] = 0x00000001U */
5744 /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */
5745 /* .. .. */
5746 EMIT_MASKWRITE(0XF8006214, 0x000F03FFU, 0x000803FFU),
5747 /* .. .. reg_arb_pri_rd_portn = 0x3ff */
5748 /* .. .. ==> 0XF8006218[9:0] = 0x000003FFU */
5749 /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
5750 /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
5751 /* .. .. ==> 0XF8006218[16:16] = 0x00000000U */
5752 /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
5753 /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
5754 /* .. .. ==> 0XF8006218[17:17] = 0x00000000U */
5755 /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
5756 /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
5757 /* .. .. ==> 0XF8006218[18:18] = 0x00000000U */
5758 /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
5759 /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
5760 /* .. .. ==> 0XF8006218[19:19] = 0x00000000U */
5761 /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */
5762 /* .. .. */
5763 EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU),
5764 /* .. .. reg_arb_pri_rd_portn = 0x3ff */
5765 /* .. .. ==> 0XF800621C[9:0] = 0x000003FFU */
5766 /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
5767 /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
5768 /* .. .. ==> 0XF800621C[16:16] = 0x00000000U */
5769 /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
5770 /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
5771 /* .. .. ==> 0XF800621C[17:17] = 0x00000000U */
5772 /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
5773 /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
5774 /* .. .. ==> 0XF800621C[18:18] = 0x00000000U */
5775 /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
5776 /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
5777 /* .. .. ==> 0XF800621C[19:19] = 0x00000000U */
5778 /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */
5779 /* .. .. */
5780 EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU),
5781 /* .. .. reg_arb_pri_rd_portn = 0x3ff */
5782 /* .. .. ==> 0XF8006220[9:0] = 0x000003FFU */
5783 /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
5784 /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
5785 /* .. .. ==> 0XF8006220[16:16] = 0x00000000U */
5786 /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
5787 /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
5788 /* .. .. ==> 0XF8006220[17:17] = 0x00000000U */
5789 /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
5790 /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
5791 /* .. .. ==> 0XF8006220[18:18] = 0x00000000U */
5792 /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
5793 /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
5794 /* .. .. ==> 0XF8006220[19:19] = 0x00000000U */
5795 /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */
5796 /* .. .. */
5797 EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU),
5798 /* .. .. reg_arb_pri_rd_portn = 0x3ff */
5799 /* .. .. ==> 0XF8006224[9:0] = 0x000003FFU */
5800 /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
5801 /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
5802 /* .. .. ==> 0XF8006224[16:16] = 0x00000000U */
5803 /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
5804 /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
5805 /* .. .. ==> 0XF8006224[17:17] = 0x00000000U */
5806 /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
5807 /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
5808 /* .. .. ==> 0XF8006224[18:18] = 0x00000000U */
5809 /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
5810 /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
5811 /* .. .. ==> 0XF8006224[19:19] = 0x00000000U */
5812 /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */
5813 /* .. .. */
5814 EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU),
5815 /* .. .. reg_ddrc_lpddr2 = 0x0 */
5816 /* .. .. ==> 0XF80062A8[0:0] = 0x00000000U */
5817 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
5818 /* .. .. reg_ddrc_per_bank_refresh = 0x0 */
5819 /* .. .. ==> 0XF80062A8[1:1] = 0x00000000U */
5820 /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
5821 /* .. .. reg_ddrc_derate_enable = 0x0 */
5822 /* .. .. ==> 0XF80062A8[2:2] = 0x00000000U */
5823 /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
5824 /* .. .. reg_ddrc_mr4_margin = 0x0 */
5825 /* .. .. ==> 0XF80062A8[11:4] = 0x00000000U */
5826 /* .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U */
5827 /* .. .. */
5828 EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U, 0x00000000U),
5829 /* .. .. reg_ddrc_mr4_read_interval = 0x0 */
5830 /* .. .. ==> 0XF80062AC[31:0] = 0x00000000U */
5831 /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */
5832 /* .. .. */
5833 EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U),
5834 /* .. .. reg_ddrc_min_stable_clock_x1 = 0x5 */
5835 /* .. .. ==> 0XF80062B0[3:0] = 0x00000005U */
5836 /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U */
5837 /* .. .. reg_ddrc_idle_after_reset_x32 = 0x12 */
5838 /* .. .. ==> 0XF80062B0[11:4] = 0x00000012U */
5839 /* .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U */
5840 /* .. .. reg_ddrc_t_mrw = 0x5 */
5841 /* .. .. ==> 0XF80062B0[21:12] = 0x00000005U */
5842 /* .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U */
5843 /* .. .. */
5844 EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U),
5845 /* .. .. reg_ddrc_max_auto_init_x1024 = 0xa6 */
5846 /* .. .. ==> 0XF80062B4[7:0] = 0x000000A6U */
5847 /* .. .. ==> MASK : 0x000000FFU VAL : 0x000000A6U */
5848 /* .. .. reg_ddrc_dev_zqinit_x32 = 0x12 */
5849 /* .. .. ==> 0XF80062B4[17:8] = 0x00000012U */
5850 /* .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U */
5851 /* .. .. */
5852 EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A6U),
5853 /* .. .. START: POLL ON DCI STATUS */
5854 /* .. .. DONE = 1 */
5855 /* .. .. ==> 0XF8000B74[13:13] = 0x00000001U */
5856 /* .. .. ==> MASK : 0x00002000U VAL : 0x00002000U */
5857 /* .. .. */
5858 EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
5859 /* .. .. FINISH: POLL ON DCI STATUS */
5860 /* .. .. START: UNLOCK DDR */
5861 /* .. .. reg_ddrc_soft_rstb = 0x1 */
5862 /* .. .. ==> 0XF8006000[0:0] = 0x00000001U */
5863 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
5864 /* .. .. reg_ddrc_powerdown_en = 0x0 */
5865 /* .. .. ==> 0XF8006000[1:1] = 0x00000000U */
5866 /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
5867 /* .. .. reg_ddrc_data_bus_width = 0x0 */
5868 /* .. .. ==> 0XF8006000[3:2] = 0x00000000U */
5869 /* .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U */
5870 /* .. .. reg_ddrc_burst8_refresh = 0x0 */
5871 /* .. .. ==> 0XF8006000[6:4] = 0x00000000U */
5872 /* .. .. ==> MASK : 0x00000070U VAL : 0x00000000U */
5873 /* .. .. reg_ddrc_rdwr_idle_gap = 1 */
5874 /* .. .. ==> 0XF8006000[13:7] = 0x00000001U */
5875 /* .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U */
5876 /* .. .. reg_ddrc_dis_rd_bypass = 0x0 */
5877 /* .. .. ==> 0XF8006000[14:14] = 0x00000000U */
5878 /* .. .. ==> MASK : 0x00004000U VAL : 0x00000000U */
5879 /* .. .. reg_ddrc_dis_act_bypass = 0x0 */
5880 /* .. .. ==> 0XF8006000[15:15] = 0x00000000U */
5881 /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */
5882 /* .. .. reg_ddrc_dis_auto_refresh = 0x0 */
5883 /* .. .. ==> 0XF8006000[16:16] = 0x00000000U */
5884 /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
5885 /* .. .. */
5886 EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U),
5887 /* .. .. FINISH: UNLOCK DDR */
5888 /* .. .. START: CHECK DDR STATUS */
5889 /* .. .. ddrc_reg_operating_mode = 1 */
5890 /* .. .. ==> 0XF8006054[2:0] = 0x00000001U */
5891 /* .. .. ==> MASK : 0x00000007U VAL : 0x00000001U */
5892 /* .. .. */
5893 EMIT_MASKPOLL(0XF8006054, 0x00000007U),
5894 /* .. .. FINISH: CHECK DDR STATUS */
5895 /* .. FINISH: DDR INITIALIZATION */
5896 /* FINISH: top */
5897 /* */
5898 EMIT_EXIT(),
5899
5900 /* */
5901};
5902
5903unsigned long ps7_mio_init_data_2_0[] = {
5904 /* START: top */
5905 /* .. START: SLCR SETTINGS */
5906 /* .. UNLOCK_KEY = 0XDF0D */
5907 /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
5908 /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */
5909 /* .. */
5910 EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
5911 /* .. FINISH: SLCR SETTINGS */
5912 /* .. START: OCM REMAPPING */
5913 /* .. VREF_EN = 0x1 */
5914 /* .. ==> 0XF8000B00[0:0] = 0x00000001U */
5915 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
5916 /* .. VREF_PULLUP_EN = 0x0 */
5917 /* .. ==> 0XF8000B00[1:1] = 0x00000000U */
5918 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
5919 /* .. CLK_PULLUP_EN = 0x0 */
5920 /* .. ==> 0XF8000B00[8:8] = 0x00000000U */
5921 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
5922 /* .. SRSTN_PULLUP_EN = 0x0 */
5923 /* .. ==> 0XF8000B00[9:9] = 0x00000000U */
5924 /* .. ==> MASK : 0x00000200U VAL : 0x00000000U */
5925 /* .. */
5926 EMIT_MASKWRITE(0XF8000B00, 0x00000303U, 0x00000001U),
5927 /* .. FINISH: OCM REMAPPING */
5928 /* .. START: DDRIOB SETTINGS */
5929 /* .. INP_POWER = 0x0 */
5930 /* .. ==> 0XF8000B40[0:0] = 0x00000000U */
5931 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
5932 /* .. INP_TYPE = 0x0 */
5933 /* .. ==> 0XF8000B40[2:1] = 0x00000000U */
5934 /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */
5935 /* .. DCI_UPDATE = 0x0 */
5936 /* .. ==> 0XF8000B40[3:3] = 0x00000000U */
5937 /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
5938 /* .. TERM_EN = 0x0 */
5939 /* .. ==> 0XF8000B40[4:4] = 0x00000000U */
5940 /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */
5941 /* .. DCR_TYPE = 0x0 */
5942 /* .. ==> 0XF8000B40[6:5] = 0x00000000U */
5943 /* .. ==> MASK : 0x00000060U VAL : 0x00000000U */
5944 /* .. IBUF_DISABLE_MODE = 0x0 */
5945 /* .. ==> 0XF8000B40[7:7] = 0x00000000U */
5946 /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
5947 /* .. TERM_DISABLE_MODE = 0x0 */
5948 /* .. ==> 0XF8000B40[8:8] = 0x00000000U */
5949 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
5950 /* .. OUTPUT_EN = 0x3 */
5951 /* .. ==> 0XF8000B40[10:9] = 0x00000003U */
5952 /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
5953 /* .. PULLUP_EN = 0x0 */
5954 /* .. ==> 0XF8000B40[11:11] = 0x00000000U */
5955 /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
5956 /* .. */
5957 EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U),
5958 /* .. INP_POWER = 0x0 */
5959 /* .. ==> 0XF8000B44[0:0] = 0x00000000U */
5960 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
5961 /* .. INP_TYPE = 0x0 */
5962 /* .. ==> 0XF8000B44[2:1] = 0x00000000U */
5963 /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */
5964 /* .. DCI_UPDATE = 0x0 */
5965 /* .. ==> 0XF8000B44[3:3] = 0x00000000U */
5966 /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
5967 /* .. TERM_EN = 0x0 */
5968 /* .. ==> 0XF8000B44[4:4] = 0x00000000U */
5969 /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */
5970 /* .. DCR_TYPE = 0x0 */
5971 /* .. ==> 0XF8000B44[6:5] = 0x00000000U */
5972 /* .. ==> MASK : 0x00000060U VAL : 0x00000000U */
5973 /* .. IBUF_DISABLE_MODE = 0x0 */
5974 /* .. ==> 0XF8000B44[7:7] = 0x00000000U */
5975 /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
5976 /* .. TERM_DISABLE_MODE = 0x0 */
5977 /* .. ==> 0XF8000B44[8:8] = 0x00000000U */
5978 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
5979 /* .. OUTPUT_EN = 0x3 */
5980 /* .. ==> 0XF8000B44[10:9] = 0x00000003U */
5981 /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
5982 /* .. PULLUP_EN = 0x0 */
5983 /* .. ==> 0XF8000B44[11:11] = 0x00000000U */
5984 /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
5985 /* .. */
5986 EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U),
5987 /* .. INP_POWER = 0x0 */
5988 /* .. ==> 0XF8000B48[0:0] = 0x00000000U */
5989 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
5990 /* .. INP_TYPE = 0x1 */
5991 /* .. ==> 0XF8000B48[2:1] = 0x00000001U */
5992 /* .. ==> MASK : 0x00000006U VAL : 0x00000002U */
5993 /* .. DCI_UPDATE = 0x0 */
5994 /* .. ==> 0XF8000B48[3:3] = 0x00000000U */
5995 /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
5996 /* .. TERM_EN = 0x1 */
5997 /* .. ==> 0XF8000B48[4:4] = 0x00000001U */
5998 /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */
5999 /* .. DCR_TYPE = 0x3 */
6000 /* .. ==> 0XF8000B48[6:5] = 0x00000003U */
6001 /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */
6002 /* .. IBUF_DISABLE_MODE = 0 */
6003 /* .. ==> 0XF8000B48[7:7] = 0x00000000U */
6004 /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
6005 /* .. TERM_DISABLE_MODE = 0 */
6006 /* .. ==> 0XF8000B48[8:8] = 0x00000000U */
6007 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
6008 /* .. OUTPUT_EN = 0x3 */
6009 /* .. ==> 0XF8000B48[10:9] = 0x00000003U */
6010 /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
6011 /* .. PULLUP_EN = 0x0 */
6012 /* .. ==> 0XF8000B48[11:11] = 0x00000000U */
6013 /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
6014 /* .. */
6015 EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U),
6016 /* .. INP_POWER = 0x0 */
6017 /* .. ==> 0XF8000B4C[0:0] = 0x00000000U */
6018 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
6019 /* .. INP_TYPE = 0x1 */
6020 /* .. ==> 0XF8000B4C[2:1] = 0x00000001U */
6021 /* .. ==> MASK : 0x00000006U VAL : 0x00000002U */
6022 /* .. DCI_UPDATE = 0x0 */
6023 /* .. ==> 0XF8000B4C[3:3] = 0x00000000U */
6024 /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
6025 /* .. TERM_EN = 0x1 */
6026 /* .. ==> 0XF8000B4C[4:4] = 0x00000001U */
6027 /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */
6028 /* .. DCR_TYPE = 0x3 */
6029 /* .. ==> 0XF8000B4C[6:5] = 0x00000003U */
6030 /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */
6031 /* .. IBUF_DISABLE_MODE = 0 */
6032 /* .. ==> 0XF8000B4C[7:7] = 0x00000000U */
6033 /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
6034 /* .. TERM_DISABLE_MODE = 0 */
6035 /* .. ==> 0XF8000B4C[8:8] = 0x00000000U */
6036 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
6037 /* .. OUTPUT_EN = 0x3 */
6038 /* .. ==> 0XF8000B4C[10:9] = 0x00000003U */
6039 /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
6040 /* .. PULLUP_EN = 0x0 */
6041 /* .. ==> 0XF8000B4C[11:11] = 0x00000000U */
6042 /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
6043 /* .. */
6044 EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U),
6045 /* .. INP_POWER = 0x0 */
6046 /* .. ==> 0XF8000B50[0:0] = 0x00000000U */
6047 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
6048 /* .. INP_TYPE = 0x2 */
6049 /* .. ==> 0XF8000B50[2:1] = 0x00000002U */
6050 /* .. ==> MASK : 0x00000006U VAL : 0x00000004U */
6051 /* .. DCI_UPDATE = 0x0 */
6052 /* .. ==> 0XF8000B50[3:3] = 0x00000000U */
6053 /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
6054 /* .. TERM_EN = 0x1 */
6055 /* .. ==> 0XF8000B50[4:4] = 0x00000001U */
6056 /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */
6057 /* .. DCR_TYPE = 0x3 */
6058 /* .. ==> 0XF8000B50[6:5] = 0x00000003U */
6059 /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */
6060 /* .. IBUF_DISABLE_MODE = 0 */
6061 /* .. ==> 0XF8000B50[7:7] = 0x00000000U */
6062 /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
6063 /* .. TERM_DISABLE_MODE = 0 */
6064 /* .. ==> 0XF8000B50[8:8] = 0x00000000U */
6065 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
6066 /* .. OUTPUT_EN = 0x3 */
6067 /* .. ==> 0XF8000B50[10:9] = 0x00000003U */
6068 /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
6069 /* .. PULLUP_EN = 0x0 */
6070 /* .. ==> 0XF8000B50[11:11] = 0x00000000U */
6071 /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
6072 /* .. */
6073 EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U),
6074 /* .. INP_POWER = 0x0 */
6075 /* .. ==> 0XF8000B54[0:0] = 0x00000000U */
6076 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
6077 /* .. INP_TYPE = 0x2 */
6078 /* .. ==> 0XF8000B54[2:1] = 0x00000002U */
6079 /* .. ==> MASK : 0x00000006U VAL : 0x00000004U */
6080 /* .. DCI_UPDATE = 0x0 */
6081 /* .. ==> 0XF8000B54[3:3] = 0x00000000U */
6082 /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
6083 /* .. TERM_EN = 0x1 */
6084 /* .. ==> 0XF8000B54[4:4] = 0x00000001U */
6085 /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */
6086 /* .. DCR_TYPE = 0x3 */
6087 /* .. ==> 0XF8000B54[6:5] = 0x00000003U */
6088 /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */
6089 /* .. IBUF_DISABLE_MODE = 0 */
6090 /* .. ==> 0XF8000B54[7:7] = 0x00000000U */
6091 /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
6092 /* .. TERM_DISABLE_MODE = 0 */
6093 /* .. ==> 0XF8000B54[8:8] = 0x00000000U */
6094 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
6095 /* .. OUTPUT_EN = 0x3 */
6096 /* .. ==> 0XF8000B54[10:9] = 0x00000003U */
6097 /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
6098 /* .. PULLUP_EN = 0x0 */
6099 /* .. ==> 0XF8000B54[11:11] = 0x00000000U */
6100 /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
6101 /* .. */
6102 EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U),
6103 /* .. INP_POWER = 0x0 */
6104 /* .. ==> 0XF8000B58[0:0] = 0x00000000U */
6105 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
6106 /* .. INP_TYPE = 0x0 */
6107 /* .. ==> 0XF8000B58[2:1] = 0x00000000U */
6108 /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */
6109 /* .. DCI_UPDATE = 0x0 */
6110 /* .. ==> 0XF8000B58[3:3] = 0x00000000U */
6111 /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
6112 /* .. TERM_EN = 0x0 */
6113 /* .. ==> 0XF8000B58[4:4] = 0x00000000U */
6114 /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */
6115 /* .. DCR_TYPE = 0x0 */
6116 /* .. ==> 0XF8000B58[6:5] = 0x00000000U */
6117 /* .. ==> MASK : 0x00000060U VAL : 0x00000000U */
6118 /* .. IBUF_DISABLE_MODE = 0x0 */
6119 /* .. ==> 0XF8000B58[7:7] = 0x00000000U */
6120 /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
6121 /* .. TERM_DISABLE_MODE = 0x0 */
6122 /* .. ==> 0XF8000B58[8:8] = 0x00000000U */
6123 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
6124 /* .. OUTPUT_EN = 0x3 */
6125 /* .. ==> 0XF8000B58[10:9] = 0x00000003U */
6126 /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
6127 /* .. PULLUP_EN = 0x0 */
6128 /* .. ==> 0XF8000B58[11:11] = 0x00000000U */
6129 /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
6130 /* .. */
6131 EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U),
6132 /* .. DRIVE_P = 0x1c */
6133 /* .. ==> 0XF8000B5C[6:0] = 0x0000001CU */
6134 /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */
6135 /* .. DRIVE_N = 0xc */
6136 /* .. ==> 0XF8000B5C[13:7] = 0x0000000CU */
6137 /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */
6138 /* .. SLEW_P = 0x3 */
6139 /* .. ==> 0XF8000B5C[18:14] = 0x00000003U */
6140 /* .. ==> MASK : 0x0007C000U VAL : 0x0000C000U */
6141 /* .. SLEW_N = 0x3 */
6142 /* .. ==> 0XF8000B5C[23:19] = 0x00000003U */
6143 /* .. ==> MASK : 0x00F80000U VAL : 0x00180000U */
6144 /* .. GTL = 0x0 */
6145 /* .. ==> 0XF8000B5C[26:24] = 0x00000000U */
6146 /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */
6147 /* .. RTERM = 0x0 */
6148 /* .. ==> 0XF8000B5C[31:27] = 0x00000000U */
6149 /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */
6150 /* .. */
6151 EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
6152 /* .. DRIVE_P = 0x1c */
6153 /* .. ==> 0XF8000B60[6:0] = 0x0000001CU */
6154 /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */
6155 /* .. DRIVE_N = 0xc */
6156 /* .. ==> 0XF8000B60[13:7] = 0x0000000CU */
6157 /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */
6158 /* .. SLEW_P = 0x6 */
6159 /* .. ==> 0XF8000B60[18:14] = 0x00000006U */
6160 /* .. ==> MASK : 0x0007C000U VAL : 0x00018000U */
6161 /* .. SLEW_N = 0x1f */
6162 /* .. ==> 0XF8000B60[23:19] = 0x0000001FU */
6163 /* .. ==> MASK : 0x00F80000U VAL : 0x00F80000U */
6164 /* .. GTL = 0x0 */
6165 /* .. ==> 0XF8000B60[26:24] = 0x00000000U */
6166 /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */
6167 /* .. RTERM = 0x0 */
6168 /* .. ==> 0XF8000B60[31:27] = 0x00000000U */
6169 /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */
6170 /* .. */
6171 EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
6172 /* .. DRIVE_P = 0x1c */
6173 /* .. ==> 0XF8000B64[6:0] = 0x0000001CU */
6174 /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */
6175 /* .. DRIVE_N = 0xc */
6176 /* .. ==> 0XF8000B64[13:7] = 0x0000000CU */
6177 /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */
6178 /* .. SLEW_P = 0x6 */
6179 /* .. ==> 0XF8000B64[18:14] = 0x00000006U */
6180 /* .. ==> MASK : 0x0007C000U VAL : 0x00018000U */
6181 /* .. SLEW_N = 0x1f */
6182 /* .. ==> 0XF8000B64[23:19] = 0x0000001FU */
6183 /* .. ==> MASK : 0x00F80000U VAL : 0x00F80000U */
6184 /* .. GTL = 0x0 */
6185 /* .. ==> 0XF8000B64[26:24] = 0x00000000U */
6186 /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */
6187 /* .. RTERM = 0x0 */
6188 /* .. ==> 0XF8000B64[31:27] = 0x00000000U */
6189 /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */
6190 /* .. */
6191 EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
6192 /* .. DRIVE_P = 0x1c */
6193 /* .. ==> 0XF8000B68[6:0] = 0x0000001CU */
6194 /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */
6195 /* .. DRIVE_N = 0xc */
6196 /* .. ==> 0XF8000B68[13:7] = 0x0000000CU */
6197 /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */
6198 /* .. SLEW_P = 0x6 */
6199 /* .. ==> 0XF8000B68[18:14] = 0x00000006U */
6200 /* .. ==> MASK : 0x0007C000U VAL : 0x00018000U */
6201 /* .. SLEW_N = 0x1f */
6202 /* .. ==> 0XF8000B68[23:19] = 0x0000001FU */
6203 /* .. ==> MASK : 0x00F80000U VAL : 0x00F80000U */
6204 /* .. GTL = 0x0 */
6205 /* .. ==> 0XF8000B68[26:24] = 0x00000000U */
6206 /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */
6207 /* .. RTERM = 0x0 */
6208 /* .. ==> 0XF8000B68[31:27] = 0x00000000U */
6209 /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */
6210 /* .. */
6211 EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
6212 /* .. VREF_INT_EN = 0x0 */
6213 /* .. ==> 0XF8000B6C[0:0] = 0x00000000U */
6214 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
6215 /* .. VREF_SEL = 0x0 */
6216 /* .. ==> 0XF8000B6C[4:1] = 0x00000000U */
6217 /* .. ==> MASK : 0x0000001EU VAL : 0x00000000U */
6218 /* .. VREF_EXT_EN = 0x3 */
6219 /* .. ==> 0XF8000B6C[6:5] = 0x00000003U */
6220 /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */
6221 /* .. VREF_PULLUP_EN = 0x0 */
6222 /* .. ==> 0XF8000B6C[8:7] = 0x00000000U */
6223 /* .. ==> MASK : 0x00000180U VAL : 0x00000000U */
6224 /* .. REFIO_EN = 0x1 */
6225 /* .. ==> 0XF8000B6C[9:9] = 0x00000001U */
6226 /* .. ==> MASK : 0x00000200U VAL : 0x00000200U */
6227 /* .. REFIO_TEST = 0x0 */
6228 /* .. ==> 0XF8000B6C[11:10] = 0x00000000U */
6229 /* .. ==> MASK : 0x00000C00U VAL : 0x00000000U */
6230 /* .. REFIO_PULLUP_EN = 0x0 */
6231 /* .. ==> 0XF8000B6C[12:12] = 0x00000000U */
6232 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
6233 /* .. DRST_B_PULLUP_EN = 0x0 */
6234 /* .. ==> 0XF8000B6C[13:13] = 0x00000000U */
6235 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
6236 /* .. CKE_PULLUP_EN = 0x0 */
6237 /* .. ==> 0XF8000B6C[14:14] = 0x00000000U */
6238 /* .. ==> MASK : 0x00004000U VAL : 0x00000000U */
6239 /* .. */
6240 EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU, 0x00000260U),
6241 /* .. .. START: ASSERT RESET */
6242 /* .. .. RESET = 1 */
6243 /* .. .. ==> 0XF8000B70[0:0] = 0x00000001U */
6244 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
6245 /* .. .. VRN_OUT = 0x1 */
6246 /* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */
6247 /* .. .. ==> MASK : 0x00000020U VAL : 0x00000020U */
6248 /* .. .. */
6249 EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000021U),
6250 /* .. .. FINISH: ASSERT RESET */
6251 /* .. .. START: DEASSERT RESET */
6252 /* .. .. RESET = 0 */
6253 /* .. .. ==> 0XF8000B70[0:0] = 0x00000000U */
6254 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
6255 /* .. .. VRN_OUT = 0x1 */
6256 /* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */
6257 /* .. .. ==> MASK : 0x00000020U VAL : 0x00000020U */
6258 /* .. .. */
6259 EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U),
6260 /* .. .. FINISH: DEASSERT RESET */
6261 /* .. .. RESET = 0x1 */
6262 /* .. .. ==> 0XF8000B70[0:0] = 0x00000001U */
6263 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
6264 /* .. .. ENABLE = 0x1 */
6265 /* .. .. ==> 0XF8000B70[1:1] = 0x00000001U */
6266 /* .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */
6267 /* .. .. VRP_TRI = 0x0 */
6268 /* .. .. ==> 0XF8000B70[2:2] = 0x00000000U */
6269 /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
6270 /* .. .. VRN_TRI = 0x0 */
6271 /* .. .. ==> 0XF8000B70[3:3] = 0x00000000U */
6272 /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
6273 /* .. .. VRP_OUT = 0x0 */
6274 /* .. .. ==> 0XF8000B70[4:4] = 0x00000000U */
6275 /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
6276 /* .. .. VRN_OUT = 0x1 */
6277 /* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */
6278 /* .. .. ==> MASK : 0x00000020U VAL : 0x00000020U */
6279 /* .. .. NREF_OPT1 = 0x0 */
6280 /* .. .. ==> 0XF8000B70[7:6] = 0x00000000U */
6281 /* .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U */
6282 /* .. .. NREF_OPT2 = 0x0 */
6283 /* .. .. ==> 0XF8000B70[10:8] = 0x00000000U */
6284 /* .. .. ==> MASK : 0x00000700U VAL : 0x00000000U */
6285 /* .. .. NREF_OPT4 = 0x1 */
6286 /* .. .. ==> 0XF8000B70[13:11] = 0x00000001U */
6287 /* .. .. ==> MASK : 0x00003800U VAL : 0x00000800U */
6288 /* .. .. PREF_OPT1 = 0x0 */
6289 /* .. .. ==> 0XF8000B70[16:14] = 0x00000000U */
6290 /* .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U */
6291 /* .. .. PREF_OPT2 = 0x0 */
6292 /* .. .. ==> 0XF8000B70[19:17] = 0x00000000U */
6293 /* .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U */
6294 /* .. .. UPDATE_CONTROL = 0x0 */
6295 /* .. .. ==> 0XF8000B70[20:20] = 0x00000000U */
6296 /* .. .. ==> MASK : 0x00100000U VAL : 0x00000000U */
6297 /* .. .. INIT_COMPLETE = 0x0 */
6298 /* .. .. ==> 0XF8000B70[21:21] = 0x00000000U */
6299 /* .. .. ==> MASK : 0x00200000U VAL : 0x00000000U */
6300 /* .. .. TST_CLK = 0x0 */
6301 /* .. .. ==> 0XF8000B70[22:22] = 0x00000000U */
6302 /* .. .. ==> MASK : 0x00400000U VAL : 0x00000000U */
6303 /* .. .. TST_HLN = 0x0 */
6304 /* .. .. ==> 0XF8000B70[23:23] = 0x00000000U */
6305 /* .. .. ==> MASK : 0x00800000U VAL : 0x00000000U */
6306 /* .. .. TST_HLP = 0x0 */
6307 /* .. .. ==> 0XF8000B70[24:24] = 0x00000000U */
6308 /* .. .. ==> MASK : 0x01000000U VAL : 0x00000000U */
6309 /* .. .. TST_RST = 0x0 */
6310 /* .. .. ==> 0XF8000B70[25:25] = 0x00000000U */
6311 /* .. .. ==> MASK : 0x02000000U VAL : 0x00000000U */
6312 /* .. .. INT_DCI_EN = 0x0 */
6313 /* .. .. ==> 0XF8000B70[26:26] = 0x00000000U */
6314 /* .. .. ==> MASK : 0x04000000U VAL : 0x00000000U */
6315 /* .. .. */
6316 EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU, 0x00000823U),
6317 /* .. FINISH: DDRIOB SETTINGS */
6318 /* .. START: MIO PROGRAMMING */
6319 /* .. TRI_ENABLE = 0 */
Michal Simek264065f2016-03-03 13:25:03 +0100[diff] [blame]6320 /* .. ==> 0XF8000700[0:0] = 0x00000000U */
6321 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
6322 /* .. L0_SEL = 0 */
6323 /* .. ==> 0XF8000700[1:1] = 0x00000000U */
6324 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
6325 /* .. L1_SEL = 0 */
6326 /* .. ==> 0XF8000700[2:2] = 0x00000000U */
6327 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
6328 /* .. L2_SEL = 0 */
6329 /* .. ==> 0XF8000700[4:3] = 0x00000000U */
6330 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
6331 /* .. L3_SEL = 0 */
6332 /* .. ==> 0XF8000700[7:5] = 0x00000000U */
6333 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
6334 /* .. Speed = 0 */
6335 /* .. ==> 0XF8000700[8:8] = 0x00000000U */
6336 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
6337 /* .. IO_Type = 3 */
6338 /* .. ==> 0XF8000700[11:9] = 0x00000003U */
6339 /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
6340 /* .. PULLUP = 1 */
6341 /* .. ==> 0XF8000700[12:12] = 0x00000001U */
6342 /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
6343 /* .. DisableRcvr = 0 */
6344 /* .. ==> 0XF8000700[13:13] = 0x00000000U */
6345 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
6346 /* .. */
6347 EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00001600U),
6348 /* .. TRI_ENABLE = 0 */
Nathan Rossi4eeed0e2015-11-24 19:34:09 +1000[diff] [blame]6349 /* .. ==> 0XF8000704[0:0] = 0x00000000U */
6350 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
6351 /* .. L0_SEL = 1 */
6352 /* .. ==> 0XF8000704[1:1] = 0x00000001U */
6353 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
6354 /* .. L1_SEL = 0 */
6355 /* .. ==> 0XF8000704[2:2] = 0x00000000U */
6356 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
6357 /* .. L2_SEL = 0 */
6358 /* .. ==> 0XF8000704[4:3] = 0x00000000U */
6359 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
6360 /* .. L3_SEL = 0 */
6361 /* .. ==> 0XF8000704[7:5] = 0x00000000U */
6362 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
6363 /* .. Speed = 1 */
6364 /* .. ==> 0XF8000704[8:8] = 0x00000001U */
6365 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
6366 /* .. IO_Type = 3 */
6367 /* .. ==> 0XF8000704[11:9] = 0x00000003U */
6368 /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
6369 /* .. PULLUP = 0 */
6370 /* .. ==> 0XF8000704[12:12] = 0x00000000U */
6371 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
6372 /* .. DisableRcvr = 0 */
6373 /* .. ==> 0XF8000704[13:13] = 0x00000000U */
6374 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
6375 /* .. */
6376 EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00000702U),
6377 /* .. TRI_ENABLE = 0 */
6378 /* .. ==> 0XF8000708[0:0] = 0x00000000U */
6379 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
6380 /* .. L0_SEL = 1 */
6381 /* .. ==> 0XF8000708[1:1] = 0x00000001U */
6382 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
6383 /* .. L1_SEL = 0 */
6384 /* .. ==> 0XF8000708[2:2] = 0x00000000U */
6385 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
6386 /* .. L2_SEL = 0 */
6387 /* .. ==> 0XF8000708[4:3] = 0x00000000U */
6388 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
6389 /* .. L3_SEL = 0 */
6390 /* .. ==> 0XF8000708[7:5] = 0x00000000U */
6391 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
6392 /* .. Speed = 1 */
6393 /* .. ==> 0XF8000708[8:8] = 0x00000001U */
6394 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
6395 /* .. IO_Type = 3 */
6396 /* .. ==> 0XF8000708[11:9] = 0x00000003U */
6397 /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
6398 /* .. PULLUP = 0 */
6399 /* .. ==> 0XF8000708[12:12] = 0x00000000U */
6400 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
6401 /* .. DisableRcvr = 0 */
6402 /* .. ==> 0XF8000708[13:13] = 0x00000000U */
6403 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
6404 /* .. */
6405 EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000702U),
6406 /* .. TRI_ENABLE = 0 */
6407 /* .. ==> 0XF800070C[0:0] = 0x00000000U */
6408 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
6409 /* .. L0_SEL = 1 */
6410 /* .. ==> 0XF800070C[1:1] = 0x00000001U */
6411 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
6412 /* .. L1_SEL = 0 */
6413 /* .. ==> 0XF800070C[2:2] = 0x00000000U */
6414 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
6415 /* .. L2_SEL = 0 */
6416 /* .. ==> 0XF800070C[4:3] = 0x00000000U */
6417 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
6418 /* .. L3_SEL = 0 */
6419 /* .. ==> 0XF800070C[7:5] = 0x00000000U */
6420 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
6421 /* .. Speed = 1 */
6422 /* .. ==> 0XF800070C[8:8] = 0x00000001U */
6423 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
6424 /* .. IO_Type = 3 */
6425 /* .. ==> 0XF800070C[11:9] = 0x00000003U */
6426 /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
6427 /* .. PULLUP = 0 */
6428 /* .. ==> 0XF800070C[12:12] = 0x00000000U */
6429 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
6430 /* .. DisableRcvr = 0 */
6431 /* .. ==> 0XF800070C[13:13] = 0x00000000U */
6432 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
6433 /* .. */
6434 EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000702U),
6435 /* .. TRI_ENABLE = 0 */
6436 /* .. ==> 0XF8000710[0:0] = 0x00000000U */
6437 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
6438 /* .. L0_SEL = 1 */
6439 /* .. ==> 0XF8000710[1:1] = 0x00000001U */
6440 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
6441 /* .. L1_SEL = 0 */
6442 /* .. ==> 0XF8000710[2:2] = 0x00000000U */
6443 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
6444 /* .. L2_SEL = 0 */
6445 /* .. ==> 0XF8000710[4:3] = 0x00000000U */
6446 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
6447 /* .. L3_SEL = 0 */
6448 /* .. ==> 0XF8000710[7:5] = 0x00000000U */
6449 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
6450 /* .. Speed = 1 */
6451 /* .. ==> 0XF8000710[8:8] = 0x00000001U */
6452 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
6453 /* .. IO_Type = 3 */
6454 /* .. ==> 0XF8000710[11:9] = 0x00000003U */
6455 /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
6456 /* .. PULLUP = 0 */
6457 /* .. ==> 0XF8000710[12:12] = 0x00000000U */
6458 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
6459 /* .. DisableRcvr = 0 */
6460 /* .. ==> 0XF8000710[13:13] = 0x00000000U */
6461 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
6462 /* .. */
6463 EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000702U),
6464 /* .. TRI_ENABLE = 0 */
6465 /* .. ==> 0XF8000714[0:0] = 0x00000000U */
6466 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
6467 /* .. L0_SEL = 1 */
6468 /* .. ==> 0XF8000714[1:1] = 0x00000001U */
6469 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
6470 /* .. L1_SEL = 0 */
6471 /* .. ==> 0XF8000714[2:2] = 0x00000000U */
6472 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
6473 /* .. L2_SEL = 0 */
6474 /* .. ==> 0XF8000714[4:3] = 0x00000000U */
6475 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
6476 /* .. L3_SEL = 0 */
6477 /* .. ==> 0XF8000714[7:5] = 0x00000000U */
6478 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
6479 /* .. Speed = 1 */
6480 /* .. ==> 0XF8000714[8:8] = 0x00000001U */
6481 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
6482 /* .. IO_Type = 3 */
6483 /* .. ==> 0XF8000714[11:9] = 0x00000003U */
6484 /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
6485 /* .. PULLUP = 0 */
6486 /* .. ==> 0XF8000714[12:12] = 0x00000000U */
6487 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
6488 /* .. DisableRcvr = 0 */
6489 /* .. ==> 0XF8000714[13:13] = 0x00000000U */
6490 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
6491 /* .. */
6492 EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000702U),
6493 /* .. TRI_ENABLE = 0 */
6494 /* .. ==> 0XF8000718[0:0] = 0x00000000U */
6495 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
6496 /* .. L0_SEL = 1 */
6497 /* .. ==> 0XF8000718[1:1] = 0x00000001U */
6498 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
6499 /* .. L1_SEL = 0 */
6500 /* .. ==> 0XF8000718[2:2] = 0x00000000U */
6501 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
6502 /* .. L2_SEL = 0 */
6503 /* .. ==> 0XF8000718[4:3] = 0x00000000U */
6504 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
6505 /* .. L3_SEL = 0 */
6506 /* .. ==> 0XF8000718[7:5] = 0x00000000U */
6507 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
6508 /* .. Speed = 1 */
6509 /* .. ==> 0XF8000718[8:8] = 0x00000001U */
6510 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
6511 /* .. IO_Type = 3 */
6512 /* .. ==> 0XF8000718[11:9] = 0x00000003U */
6513 /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
6514 /* .. PULLUP = 0 */
6515 /* .. ==> 0XF8000718[12:12] = 0x00000000U */
6516 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
6517 /* .. DisableRcvr = 0 */
6518 /* .. ==> 0XF8000718[13:13] = 0x00000000U */
6519 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
6520 /* .. */
6521 EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000702U),
6522 /* .. TRI_ENABLE = 0 */
Michal Simek264065f2016-03-03 13:25:03 +0100[diff] [blame]6523 /* .. ==> 0XF800071C[0:0] = 0x00000000U */
6524 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
6525 /* .. L0_SEL = 0 */
6526 /* .. ==> 0XF800071C[1:1] = 0x00000000U */
6527 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
6528 /* .. L1_SEL = 0 */
6529 /* .. ==> 0XF800071C[2:2] = 0x00000000U */
6530 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
6531 /* .. L2_SEL = 0 */
6532 /* .. ==> 0XF800071C[4:3] = 0x00000000U */
6533 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
6534 /* .. L3_SEL = 0 */
6535 /* .. ==> 0XF800071C[7:5] = 0x00000000U */
6536 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
6537 /* .. Speed = 0 */
6538 /* .. ==> 0XF800071C[8:8] = 0x00000000U */
6539 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
6540 /* .. IO_Type = 3 */
6541 /* .. ==> 0XF800071C[11:9] = 0x00000003U */
6542 /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
6543 /* .. PULLUP = 0 */
6544 /* .. ==> 0XF800071C[12:12] = 0x00000000U */
6545 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
6546 /* .. DisableRcvr = 0 */
6547 /* .. ==> 0XF800071C[13:13] = 0x00000000U */
6548 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
6549 /* .. */
6550 EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000600U),
6551 /* .. TRI_ENABLE = 0 */
6552 /* .. ==> 0XF8000720[0:0] = 0x00000000U */
6553 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
6554 /* .. L0_SEL = 1 */
6555 /* .. ==> 0XF8000720[1:1] = 0x00000001U */
6556 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
6557 /* .. L1_SEL = 0 */
6558 /* .. ==> 0XF8000720[2:2] = 0x00000000U */
6559 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
6560 /* .. L2_SEL = 0 */
6561 /* .. ==> 0XF8000720[4:3] = 0x00000000U */
6562 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
6563 /* .. L3_SEL = 0 */
6564 /* .. ==> 0XF8000720[7:5] = 0x00000000U */
6565 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
6566 /* .. Speed = 1 */
6567 /* .. ==> 0XF8000720[8:8] = 0x00000001U */
6568 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
6569 /* .. IO_Type = 3 */
6570 /* .. ==> 0XF8000720[11:9] = 0x00000003U */
6571 /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
6572 /* .. PULLUP = 0 */
6573 /* .. ==> 0XF8000720[12:12] = 0x00000000U */
6574 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
6575 /* .. DisableRcvr = 0 */
6576 /* .. ==> 0XF8000720[13:13] = 0x00000000U */
6577 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
6578 /* .. */
6579 EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000702U),
6580 /* .. TRI_ENABLE = 0 */
6581 /* .. ==> 0XF8000724[0:0] = 0x00000000U */
6582 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
6583 /* .. L0_SEL = 0 */
6584 /* .. ==> 0XF8000724[1:1] = 0x00000000U */
6585 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
6586 /* .. L1_SEL = 0 */
6587 /* .. ==> 0XF8000724[2:2] = 0x00000000U */
6588 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
6589 /* .. L2_SEL = 0 */
6590 /* .. ==> 0XF8000724[4:3] = 0x00000000U */
6591 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
6592 /* .. L3_SEL = 0 */
6593 /* .. ==> 0XF8000724[7:5] = 0x00000000U */
6594 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
6595 /* .. Speed = 0 */
6596 /* .. ==> 0XF8000724[8:8] = 0x00000000U */
6597 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
6598 /* .. IO_Type = 3 */
6599 /* .. ==> 0XF8000724[11:9] = 0x00000003U */
6600 /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
6601 /* .. PULLUP = 1 */
6602 /* .. ==> 0XF8000724[12:12] = 0x00000001U */
6603 /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
6604 /* .. DisableRcvr = 0 */
6605 /* .. ==> 0XF8000724[13:13] = 0x00000000U */
6606 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
6607 /* .. */
6608 EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00001600U),
6609 /* .. TRI_ENABLE = 0 */
6610 /* .. ==> 0XF8000728[0:0] = 0x00000000U */
6611 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
6612 /* .. L0_SEL = 0 */
6613 /* .. ==> 0XF8000728[1:1] = 0x00000000U */
6614 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
6615 /* .. L1_SEL = 0 */
6616 /* .. ==> 0XF8000728[2:2] = 0x00000000U */
6617 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
6618 /* .. L2_SEL = 0 */
6619 /* .. ==> 0XF8000728[4:3] = 0x00000000U */
6620 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
6621 /* .. L3_SEL = 0 */
6622 /* .. ==> 0XF8000728[7:5] = 0x00000000U */
6623 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
6624 /* .. Speed = 0 */
6625 /* .. ==> 0XF8000728[8:8] = 0x00000000U */
6626 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
6627 /* .. IO_Type = 3 */
6628 /* .. ==> 0XF8000728[11:9] = 0x00000003U */
6629 /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
6630 /* .. PULLUP = 1 */
6631 /* .. ==> 0XF8000728[12:12] = 0x00000001U */
6632 /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
6633 /* .. DisableRcvr = 0 */
6634 /* .. ==> 0XF8000728[13:13] = 0x00000000U */
6635 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
6636 /* .. */
6637 EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x00001600U),
6638 /* .. TRI_ENABLE = 0 */
6639 /* .. ==> 0XF800072C[0:0] = 0x00000000U */
6640 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
6641 /* .. L0_SEL = 0 */
6642 /* .. ==> 0XF800072C[1:1] = 0x00000000U */
6643 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
6644 /* .. L1_SEL = 0 */
6645 /* .. ==> 0XF800072C[2:2] = 0x00000000U */
6646 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
6647 /* .. L2_SEL = 0 */
6648 /* .. ==> 0XF800072C[4:3] = 0x00000000U */
6649 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
6650 /* .. L3_SEL = 0 */
6651 /* .. ==> 0XF800072C[7:5] = 0x00000000U */
6652 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
6653 /* .. Speed = 0 */
6654 /* .. ==> 0XF800072C[8:8] = 0x00000000U */
6655 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
6656 /* .. IO_Type = 3 */
6657 /* .. ==> 0XF800072C[11:9] = 0x00000003U */
6658 /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
6659 /* .. PULLUP = 1 */
6660 /* .. ==> 0XF800072C[12:12] = 0x00000001U */
6661 /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
6662 /* .. DisableRcvr = 0 */
6663 /* .. ==> 0XF800072C[13:13] = 0x00000000U */
6664 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
6665 /* .. */
6666 EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x00001600U),
6667 /* .. TRI_ENABLE = 0 */
6668 /* .. ==> 0XF8000730[0:0] = 0x00000000U */
6669 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
6670 /* .. L0_SEL = 0 */
6671 /* .. ==> 0XF8000730[1:1] = 0x00000000U */
6672 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
6673 /* .. L1_SEL = 0 */
6674 /* .. ==> 0XF8000730[2:2] = 0x00000000U */
6675 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
6676 /* .. L2_SEL = 0 */
6677 /* .. ==> 0XF8000730[4:3] = 0x00000000U */
6678 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
6679 /* .. L3_SEL = 0 */
6680 /* .. ==> 0XF8000730[7:5] = 0x00000000U */
6681 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
6682 /* .. Speed = 0 */
6683 /* .. ==> 0XF8000730[8:8] = 0x00000000U */
6684 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
6685 /* .. IO_Type = 3 */
6686 /* .. ==> 0XF8000730[11:9] = 0x00000003U */
6687 /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
6688 /* .. PULLUP = 1 */
6689 /* .. ==> 0XF8000730[12:12] = 0x00000001U */
6690 /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
6691 /* .. DisableRcvr = 0 */
6692 /* .. ==> 0XF8000730[13:13] = 0x00000000U */
6693 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
6694 /* .. */
6695 EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x00001600U),
6696 /* .. TRI_ENABLE = 0 */
6697 /* .. ==> 0XF8000734[0:0] = 0x00000000U */
6698 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
6699 /* .. L0_SEL = 0 */
6700 /* .. ==> 0XF8000734[1:1] = 0x00000000U */
6701 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
6702 /* .. L1_SEL = 0 */
6703 /* .. ==> 0XF8000734[2:2] = 0x00000000U */
6704 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
6705 /* .. L2_SEL = 0 */
6706 /* .. ==> 0XF8000734[4:3] = 0x00000000U */
6707 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
6708 /* .. L3_SEL = 0 */
6709 /* .. ==> 0XF8000734[7:5] = 0x00000000U */
6710 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
6711 /* .. Speed = 0 */
6712 /* .. ==> 0XF8000734[8:8] = 0x00000000U */
6713 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
6714 /* .. IO_Type = 3 */
6715 /* .. ==> 0XF8000734[11:9] = 0x00000003U */
6716 /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
6717 /* .. PULLUP = 1 */
6718 /* .. ==> 0XF8000734[12:12] = 0x00000001U */
6719 /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
6720 /* .. DisableRcvr = 0 */
6721 /* .. ==> 0XF8000734[13:13] = 0x00000000U */
6722 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
6723 /* .. */
6724 EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x00001600U),
6725 /* .. TRI_ENABLE = 0 */
6726 /* .. ==> 0XF8000738[0:0] = 0x00000000U */
6727 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
6728 /* .. L0_SEL = 0 */
6729 /* .. ==> 0XF8000738[1:1] = 0x00000000U */
6730 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
6731 /* .. L1_SEL = 0 */
6732 /* .. ==> 0XF8000738[2:2] = 0x00000000U */
6733 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
6734 /* .. L2_SEL = 0 */
6735 /* .. ==> 0XF8000738[4:3] = 0x00000000U */
6736 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
6737 /* .. L3_SEL = 0 */
6738 /* .. ==> 0XF8000738[7:5] = 0x00000000U */
6739 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
6740 /* .. Speed = 0 */
6741 /* .. ==> 0XF8000738[8:8] = 0x00000000U */
6742 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
6743 /* .. IO_Type = 3 */
6744 /* .. ==> 0XF8000738[11:9] = 0x00000003U */
6745 /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
6746 /* .. PULLUP = 1 */
6747 /* .. ==> 0XF8000738[12:12] = 0x00000001U */
6748 /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
6749 /* .. DisableRcvr = 0 */
6750 /* .. ==> 0XF8000738[13:13] = 0x00000000U */
6751 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
6752 /* .. */
6753 EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x00001600U),
6754 /* .. TRI_ENABLE = 0 */
6755 /* .. ==> 0XF800073C[0:0] = 0x00000000U */
6756 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
6757 /* .. L0_SEL = 0 */
6758 /* .. ==> 0XF800073C[1:1] = 0x00000000U */
6759 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
6760 /* .. L1_SEL = 0 */
6761 /* .. ==> 0XF800073C[2:2] = 0x00000000U */
6762 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
6763 /* .. L2_SEL = 0 */
6764 /* .. ==> 0XF800073C[4:3] = 0x00000000U */
6765 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
6766 /* .. L3_SEL = 0 */
6767 /* .. ==> 0XF800073C[7:5] = 0x00000000U */
6768 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
6769 /* .. Speed = 0 */
6770 /* .. ==> 0XF800073C[8:8] = 0x00000000U */
6771 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
6772 /* .. IO_Type = 3 */
6773 /* .. ==> 0XF800073C[11:9] = 0x00000003U */
6774 /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
6775 /* .. PULLUP = 1 */
6776 /* .. ==> 0XF800073C[12:12] = 0x00000001U */
6777 /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
6778 /* .. DisableRcvr = 0 */
6779 /* .. ==> 0XF800073C[13:13] = 0x00000000U */
6780 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
6781 /* .. */
6782 EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x00001600U),
6783 /* .. TRI_ENABLE = 0 */
Nathan Rossi4eeed0e2015-11-24 19:34:09 +1000[diff] [blame]6784 /* .. ==> 0XF8000740[0:0] = 0x00000000U */
6785 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
6786 /* .. L0_SEL = 1 */
6787 /* .. ==> 0XF8000740[1:1] = 0x00000001U */
6788 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
6789 /* .. L1_SEL = 0 */
6790 /* .. ==> 0XF8000740[2:2] = 0x00000000U */
6791 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
6792 /* .. L2_SEL = 0 */
6793 /* .. ==> 0XF8000740[4:3] = 0x00000000U */
6794 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
6795 /* .. L3_SEL = 0 */
6796 /* .. ==> 0XF8000740[7:5] = 0x00000000U */
6797 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
6798 /* .. Speed = 1 */
6799 /* .. ==> 0XF8000740[8:8] = 0x00000001U */
6800 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
6801 /* .. IO_Type = 4 */
6802 /* .. ==> 0XF8000740[11:9] = 0x00000004U */
6803 /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
6804 /* .. PULLUP = 0 */
6805 /* .. ==> 0XF8000740[12:12] = 0x00000000U */
6806 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
6807 /* .. DisableRcvr = 1 */
6808 /* .. ==> 0XF8000740[13:13] = 0x00000001U */
6809 /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
6810 /* .. */
6811 EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x00002902U),
6812 /* .. TRI_ENABLE = 0 */
6813 /* .. ==> 0XF8000744[0:0] = 0x00000000U */
6814 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
6815 /* .. L0_SEL = 1 */
6816 /* .. ==> 0XF8000744[1:1] = 0x00000001U */
6817 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
6818 /* .. L1_SEL = 0 */
6819 /* .. ==> 0XF8000744[2:2] = 0x00000000U */
6820 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
6821 /* .. L2_SEL = 0 */
6822 /* .. ==> 0XF8000744[4:3] = 0x00000000U */
6823 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
6824 /* .. L3_SEL = 0 */
6825 /* .. ==> 0XF8000744[7:5] = 0x00000000U */
6826 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
6827 /* .. Speed = 1 */
6828 /* .. ==> 0XF8000744[8:8] = 0x00000001U */
6829 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
6830 /* .. IO_Type = 4 */
6831 /* .. ==> 0XF8000744[11:9] = 0x00000004U */
6832 /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
6833 /* .. PULLUP = 0 */
6834 /* .. ==> 0XF8000744[12:12] = 0x00000000U */
6835 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
6836 /* .. DisableRcvr = 1 */
6837 /* .. ==> 0XF8000744[13:13] = 0x00000001U */
6838 /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
6839 /* .. */
6840 EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x00002902U),
6841 /* .. TRI_ENABLE = 0 */
6842 /* .. ==> 0XF8000748[0:0] = 0x00000000U */
6843 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
6844 /* .. L0_SEL = 1 */
6845 /* .. ==> 0XF8000748[1:1] = 0x00000001U */
6846 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
6847 /* .. L1_SEL = 0 */
6848 /* .. ==> 0XF8000748[2:2] = 0x00000000U */
6849 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
6850 /* .. L2_SEL = 0 */
6851 /* .. ==> 0XF8000748[4:3] = 0x00000000U */
6852 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
6853 /* .. L3_SEL = 0 */
6854 /* .. ==> 0XF8000748[7:5] = 0x00000000U */
6855 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
6856 /* .. Speed = 1 */
6857 /* .. ==> 0XF8000748[8:8] = 0x00000001U */
6858 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
6859 /* .. IO_Type = 4 */
6860 /* .. ==> 0XF8000748[11:9] = 0x00000004U */
6861 /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
6862 /* .. PULLUP = 0 */
6863 /* .. ==> 0XF8000748[12:12] = 0x00000000U */
6864 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
6865 /* .. DisableRcvr = 1 */
6866 /* .. ==> 0XF8000748[13:13] = 0x00000001U */
6867 /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
6868 /* .. */
6869 EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00002902U),
6870 /* .. TRI_ENABLE = 0 */
6871 /* .. ==> 0XF800074C[0:0] = 0x00000000U */
6872 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
6873 /* .. L0_SEL = 1 */
6874 /* .. ==> 0XF800074C[1:1] = 0x00000001U */
6875 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
6876 /* .. L1_SEL = 0 */
6877 /* .. ==> 0XF800074C[2:2] = 0x00000000U */
6878 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
6879 /* .. L2_SEL = 0 */
6880 /* .. ==> 0XF800074C[4:3] = 0x00000000U */
6881 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
6882 /* .. L3_SEL = 0 */
6883 /* .. ==> 0XF800074C[7:5] = 0x00000000U */
6884 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
6885 /* .. Speed = 1 */
6886 /* .. ==> 0XF800074C[8:8] = 0x00000001U */
6887 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
6888 /* .. IO_Type = 4 */
6889 /* .. ==> 0XF800074C[11:9] = 0x00000004U */
6890 /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
6891 /* .. PULLUP = 0 */
6892 /* .. ==> 0XF800074C[12:12] = 0x00000000U */
6893 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
6894 /* .. DisableRcvr = 1 */
6895 /* .. ==> 0XF800074C[13:13] = 0x00000001U */
6896 /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
6897 /* .. */
6898 EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00002902U),
6899 /* .. TRI_ENABLE = 0 */
6900 /* .. ==> 0XF8000750[0:0] = 0x00000000U */
6901 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
6902 /* .. L0_SEL = 1 */
6903 /* .. ==> 0XF8000750[1:1] = 0x00000001U */
6904 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
6905 /* .. L1_SEL = 0 */
6906 /* .. ==> 0XF8000750[2:2] = 0x00000000U */
6907 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
6908 /* .. L2_SEL = 0 */
6909 /* .. ==> 0XF8000750[4:3] = 0x00000000U */
6910 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
6911 /* .. L3_SEL = 0 */
6912 /* .. ==> 0XF8000750[7:5] = 0x00000000U */
6913 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
6914 /* .. Speed = 1 */
6915 /* .. ==> 0XF8000750[8:8] = 0x00000001U */
6916 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
6917 /* .. IO_Type = 4 */
6918 /* .. ==> 0XF8000750[11:9] = 0x00000004U */
6919 /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
6920 /* .. PULLUP = 0 */
6921 /* .. ==> 0XF8000750[12:12] = 0x00000000U */
6922 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
6923 /* .. DisableRcvr = 1 */
6924 /* .. ==> 0XF8000750[13:13] = 0x00000001U */
6925 /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
6926 /* .. */
6927 EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00002902U),
6928 /* .. TRI_ENABLE = 0 */
6929 /* .. ==> 0XF8000754[0:0] = 0x00000000U */
6930 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
6931 /* .. L0_SEL = 1 */
6932 /* .. ==> 0XF8000754[1:1] = 0x00000001U */
6933 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
6934 /* .. L1_SEL = 0 */
6935 /* .. ==> 0XF8000754[2:2] = 0x00000000U */
6936 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
6937 /* .. L2_SEL = 0 */
6938 /* .. ==> 0XF8000754[4:3] = 0x00000000U */
6939 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
6940 /* .. L3_SEL = 0 */
6941 /* .. ==> 0XF8000754[7:5] = 0x00000000U */
6942 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
6943 /* .. Speed = 1 */
6944 /* .. ==> 0XF8000754[8:8] = 0x00000001U */
6945 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
6946 /* .. IO_Type = 4 */
6947 /* .. ==> 0XF8000754[11:9] = 0x00000004U */
6948 /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
6949 /* .. PULLUP = 0 */
6950 /* .. ==> 0XF8000754[12:12] = 0x00000000U */
6951 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
6952 /* .. DisableRcvr = 1 */
6953 /* .. ==> 0XF8000754[13:13] = 0x00000001U */
6954 /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
6955 /* .. */
6956 EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00002902U),
6957 /* .. TRI_ENABLE = 1 */
6958 /* .. ==> 0XF8000758[0:0] = 0x00000001U */
6959 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
6960 /* .. L0_SEL = 1 */
6961 /* .. ==> 0XF8000758[1:1] = 0x00000001U */
6962 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
6963 /* .. L1_SEL = 0 */
6964 /* .. ==> 0XF8000758[2:2] = 0x00000000U */
6965 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
6966 /* .. L2_SEL = 0 */
6967 /* .. ==> 0XF8000758[4:3] = 0x00000000U */
6968 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
6969 /* .. L3_SEL = 0 */
6970 /* .. ==> 0XF8000758[7:5] = 0x00000000U */
6971 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
6972 /* .. Speed = 1 */
6973 /* .. ==> 0XF8000758[8:8] = 0x00000001U */
6974 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
6975 /* .. IO_Type = 4 */
6976 /* .. ==> 0XF8000758[11:9] = 0x00000004U */
6977 /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
6978 /* .. PULLUP = 0 */
6979 /* .. ==> 0XF8000758[12:12] = 0x00000000U */
6980 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
6981 /* .. DisableRcvr = 0 */
6982 /* .. ==> 0XF8000758[13:13] = 0x00000000U */
6983 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
6984 /* .. */
6985 EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00000903U),
6986 /* .. TRI_ENABLE = 1 */
6987 /* .. ==> 0XF800075C[0:0] = 0x00000001U */
6988 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
6989 /* .. L0_SEL = 1 */
6990 /* .. ==> 0XF800075C[1:1] = 0x00000001U */
6991 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
6992 /* .. L1_SEL = 0 */
6993 /* .. ==> 0XF800075C[2:2] = 0x00000000U */
6994 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
6995 /* .. L2_SEL = 0 */
6996 /* .. ==> 0XF800075C[4:3] = 0x00000000U */
6997 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
6998 /* .. L3_SEL = 0 */
6999 /* .. ==> 0XF800075C[7:5] = 0x00000000U */
7000 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
7001 /* .. Speed = 1 */
7002 /* .. ==> 0XF800075C[8:8] = 0x00000001U */
7003 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
7004 /* .. IO_Type = 4 */
7005 /* .. ==> 0XF800075C[11:9] = 0x00000004U */
7006 /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
7007 /* .. PULLUP = 0 */
7008 /* .. ==> 0XF800075C[12:12] = 0x00000000U */
7009 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
7010 /* .. DisableRcvr = 0 */
7011 /* .. ==> 0XF800075C[13:13] = 0x00000000U */
7012 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
7013 /* .. */
7014 EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00000903U),
7015 /* .. TRI_ENABLE = 1 */
7016 /* .. ==> 0XF8000760[0:0] = 0x00000001U */
7017 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
7018 /* .. L0_SEL = 1 */
7019 /* .. ==> 0XF8000760[1:1] = 0x00000001U */
7020 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
7021 /* .. L1_SEL = 0 */
7022 /* .. ==> 0XF8000760[2:2] = 0x00000000U */
7023 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
7024 /* .. L2_SEL = 0 */
7025 /* .. ==> 0XF8000760[4:3] = 0x00000000U */
7026 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
7027 /* .. L3_SEL = 0 */
7028 /* .. ==> 0XF8000760[7:5] = 0x00000000U */
7029 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
7030 /* .. Speed = 1 */
7031 /* .. ==> 0XF8000760[8:8] = 0x00000001U */
7032 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
7033 /* .. IO_Type = 4 */
7034 /* .. ==> 0XF8000760[11:9] = 0x00000004U */
7035 /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
7036 /* .. PULLUP = 0 */
7037 /* .. ==> 0XF8000760[12:12] = 0x00000000U */
7038 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
7039 /* .. DisableRcvr = 0 */
7040 /* .. ==> 0XF8000760[13:13] = 0x00000000U */
7041 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
7042 /* .. */
7043 EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00000903U),
7044 /* .. TRI_ENABLE = 1 */
7045 /* .. ==> 0XF8000764[0:0] = 0x00000001U */
7046 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
7047 /* .. L0_SEL = 1 */
7048 /* .. ==> 0XF8000764[1:1] = 0x00000001U */
7049 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
7050 /* .. L1_SEL = 0 */
7051 /* .. ==> 0XF8000764[2:2] = 0x00000000U */
7052 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
7053 /* .. L2_SEL = 0 */
7054 /* .. ==> 0XF8000764[4:3] = 0x00000000U */
7055 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
7056 /* .. L3_SEL = 0 */
7057 /* .. ==> 0XF8000764[7:5] = 0x00000000U */
7058 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
7059 /* .. Speed = 1 */
7060 /* .. ==> 0XF8000764[8:8] = 0x00000001U */
7061 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
7062 /* .. IO_Type = 4 */
7063 /* .. ==> 0XF8000764[11:9] = 0x00000004U */
7064 /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
7065 /* .. PULLUP = 0 */
7066 /* .. ==> 0XF8000764[12:12] = 0x00000000U */
7067 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
7068 /* .. DisableRcvr = 0 */
7069 /* .. ==> 0XF8000764[13:13] = 0x00000000U */
7070 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
7071 /* .. */
7072 EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00000903U),
7073 /* .. TRI_ENABLE = 1 */
7074 /* .. ==> 0XF8000768[0:0] = 0x00000001U */
7075 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
7076 /* .. L0_SEL = 1 */
7077 /* .. ==> 0XF8000768[1:1] = 0x00000001U */
7078 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
7079 /* .. L1_SEL = 0 */
7080 /* .. ==> 0XF8000768[2:2] = 0x00000000U */
7081 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
7082 /* .. L2_SEL = 0 */
7083 /* .. ==> 0XF8000768[4:3] = 0x00000000U */
7084 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
7085 /* .. L3_SEL = 0 */
7086 /* .. ==> 0XF8000768[7:5] = 0x00000000U */
7087 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
7088 /* .. Speed = 1 */
7089 /* .. ==> 0XF8000768[8:8] = 0x00000001U */
7090 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
7091 /* .. IO_Type = 4 */
7092 /* .. ==> 0XF8000768[11:9] = 0x00000004U */
7093 /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
7094 /* .. PULLUP = 0 */
7095 /* .. ==> 0XF8000768[12:12] = 0x00000000U */
7096 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
7097 /* .. DisableRcvr = 0 */
7098 /* .. ==> 0XF8000768[13:13] = 0x00000000U */
7099 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
7100 /* .. */
7101 EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00000903U),
7102 /* .. TRI_ENABLE = 1 */
7103 /* .. ==> 0XF800076C[0:0] = 0x00000001U */
7104 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
7105 /* .. L0_SEL = 1 */
7106 /* .. ==> 0XF800076C[1:1] = 0x00000001U */
7107 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
7108 /* .. L1_SEL = 0 */
7109 /* .. ==> 0XF800076C[2:2] = 0x00000000U */
7110 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
7111 /* .. L2_SEL = 0 */
7112 /* .. ==> 0XF800076C[4:3] = 0x00000000U */
7113 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
7114 /* .. L3_SEL = 0 */
7115 /* .. ==> 0XF800076C[7:5] = 0x00000000U */
7116 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
7117 /* .. Speed = 1 */
7118 /* .. ==> 0XF800076C[8:8] = 0x00000001U */
7119 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
7120 /* .. IO_Type = 4 */
7121 /* .. ==> 0XF800076C[11:9] = 0x00000004U */
7122 /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
7123 /* .. PULLUP = 0 */
7124 /* .. ==> 0XF800076C[12:12] = 0x00000000U */
7125 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
7126 /* .. DisableRcvr = 0 */
7127 /* .. ==> 0XF800076C[13:13] = 0x00000000U */
7128 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
7129 /* .. */
7130 EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00000903U),
7131 /* .. TRI_ENABLE = 0 */
7132 /* .. ==> 0XF8000770[0:0] = 0x00000000U */
7133 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
7134 /* .. L0_SEL = 0 */
7135 /* .. ==> 0XF8000770[1:1] = 0x00000000U */
7136 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
7137 /* .. L1_SEL = 1 */
7138 /* .. ==> 0XF8000770[2:2] = 0x00000001U */
7139 /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
7140 /* .. L2_SEL = 0 */
7141 /* .. ==> 0XF8000770[4:3] = 0x00000000U */
7142 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
7143 /* .. L3_SEL = 0 */
7144 /* .. ==> 0XF8000770[7:5] = 0x00000000U */
7145 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
7146 /* .. Speed = 1 */
7147 /* .. ==> 0XF8000770[8:8] = 0x00000001U */
7148 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
7149 /* .. IO_Type = 1 */
7150 /* .. ==> 0XF8000770[11:9] = 0x00000001U */
7151 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
7152 /* .. PULLUP = 0 */
7153 /* .. ==> 0XF8000770[12:12] = 0x00000000U */
7154 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
7155 /* .. DisableRcvr = 0 */
7156 /* .. ==> 0XF8000770[13:13] = 0x00000000U */
7157 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
7158 /* .. */
7159 EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00000304U),
7160 /* .. TRI_ENABLE = 1 */
7161 /* .. ==> 0XF8000774[0:0] = 0x00000001U */
7162 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
7163 /* .. L0_SEL = 0 */
7164 /* .. ==> 0XF8000774[1:1] = 0x00000000U */
7165 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
7166 /* .. L1_SEL = 1 */
7167 /* .. ==> 0XF8000774[2:2] = 0x00000001U */
7168 /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
7169 /* .. L2_SEL = 0 */
7170 /* .. ==> 0XF8000774[4:3] = 0x00000000U */
7171 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
7172 /* .. L3_SEL = 0 */
7173 /* .. ==> 0XF8000774[7:5] = 0x00000000U */
7174 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
7175 /* .. Speed = 1 */
7176 /* .. ==> 0XF8000774[8:8] = 0x00000001U */
7177 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
7178 /* .. IO_Type = 1 */
7179 /* .. ==> 0XF8000774[11:9] = 0x00000001U */
7180 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
7181 /* .. PULLUP = 0 */
7182 /* .. ==> 0XF8000774[12:12] = 0x00000000U */
7183 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
7184 /* .. DisableRcvr = 0 */
7185 /* .. ==> 0XF8000774[13:13] = 0x00000000U */
7186 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
7187 /* .. */
7188 EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00000305U),
7189 /* .. TRI_ENABLE = 0 */
7190 /* .. ==> 0XF8000778[0:0] = 0x00000000U */
7191 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
7192 /* .. L0_SEL = 0 */
7193 /* .. ==> 0XF8000778[1:1] = 0x00000000U */
7194 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
7195 /* .. L1_SEL = 1 */
7196 /* .. ==> 0XF8000778[2:2] = 0x00000001U */
7197 /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
7198 /* .. L2_SEL = 0 */
7199 /* .. ==> 0XF8000778[4:3] = 0x00000000U */
7200 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
7201 /* .. L3_SEL = 0 */
7202 /* .. ==> 0XF8000778[7:5] = 0x00000000U */
7203 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
7204 /* .. Speed = 1 */
7205 /* .. ==> 0XF8000778[8:8] = 0x00000001U */
7206 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
7207 /* .. IO_Type = 1 */
7208 /* .. ==> 0XF8000778[11:9] = 0x00000001U */
7209 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
7210 /* .. PULLUP = 0 */
7211 /* .. ==> 0XF8000778[12:12] = 0x00000000U */
7212 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
7213 /* .. DisableRcvr = 0 */
7214 /* .. ==> 0XF8000778[13:13] = 0x00000000U */
7215 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
7216 /* .. */
7217 EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00000304U),
7218 /* .. TRI_ENABLE = 1 */
7219 /* .. ==> 0XF800077C[0:0] = 0x00000001U */
7220 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
7221 /* .. L0_SEL = 0 */
7222 /* .. ==> 0XF800077C[1:1] = 0x00000000U */
7223 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
7224 /* .. L1_SEL = 1 */
7225 /* .. ==> 0XF800077C[2:2] = 0x00000001U */
7226 /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
7227 /* .. L2_SEL = 0 */
7228 /* .. ==> 0XF800077C[4:3] = 0x00000000U */
7229 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
7230 /* .. L3_SEL = 0 */
7231 /* .. ==> 0XF800077C[7:5] = 0x00000000U */
7232 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
7233 /* .. Speed = 1 */
7234 /* .. ==> 0XF800077C[8:8] = 0x00000001U */
7235 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
7236 /* .. IO_Type = 1 */
7237 /* .. ==> 0XF800077C[11:9] = 0x00000001U */
7238 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
7239 /* .. PULLUP = 0 */
7240 /* .. ==> 0XF800077C[12:12] = 0x00000000U */
7241 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
7242 /* .. DisableRcvr = 0 */
7243 /* .. ==> 0XF800077C[13:13] = 0x00000000U */
7244 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
7245 /* .. */
7246 EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00000305U),
7247 /* .. TRI_ENABLE = 0 */
7248 /* .. ==> 0XF8000780[0:0] = 0x00000000U */
7249 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
7250 /* .. L0_SEL = 0 */
7251 /* .. ==> 0XF8000780[1:1] = 0x00000000U */
7252 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
7253 /* .. L1_SEL = 1 */
7254 /* .. ==> 0XF8000780[2:2] = 0x00000001U */
7255 /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
7256 /* .. L2_SEL = 0 */
7257 /* .. ==> 0XF8000780[4:3] = 0x00000000U */
7258 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
7259 /* .. L3_SEL = 0 */
7260 /* .. ==> 0XF8000780[7:5] = 0x00000000U */
7261 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
7262 /* .. Speed = 1 */
7263 /* .. ==> 0XF8000780[8:8] = 0x00000001U */
7264 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
7265 /* .. IO_Type = 1 */
7266 /* .. ==> 0XF8000780[11:9] = 0x00000001U */
7267 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
7268 /* .. PULLUP = 0 */
7269 /* .. ==> 0XF8000780[12:12] = 0x00000000U */
7270 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
7271 /* .. DisableRcvr = 0 */
7272 /* .. ==> 0XF8000780[13:13] = 0x00000000U */
7273 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
7274 /* .. */
7275 EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00000304U),
7276 /* .. TRI_ENABLE = 0 */
7277 /* .. ==> 0XF8000784[0:0] = 0x00000000U */
7278 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
7279 /* .. L0_SEL = 0 */
7280 /* .. ==> 0XF8000784[1:1] = 0x00000000U */
7281 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
7282 /* .. L1_SEL = 1 */
7283 /* .. ==> 0XF8000784[2:2] = 0x00000001U */
7284 /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
7285 /* .. L2_SEL = 0 */
7286 /* .. ==> 0XF8000784[4:3] = 0x00000000U */
7287 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
7288 /* .. L3_SEL = 0 */
7289 /* .. ==> 0XF8000784[7:5] = 0x00000000U */
7290 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
7291 /* .. Speed = 1 */
7292 /* .. ==> 0XF8000784[8:8] = 0x00000001U */
7293 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
7294 /* .. IO_Type = 1 */
7295 /* .. ==> 0XF8000784[11:9] = 0x00000001U */
7296 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
7297 /* .. PULLUP = 0 */
7298 /* .. ==> 0XF8000784[12:12] = 0x00000000U */
7299 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
7300 /* .. DisableRcvr = 0 */
7301 /* .. ==> 0XF8000784[13:13] = 0x00000000U */
7302 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
7303 /* .. */
7304 EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00000304U),
7305 /* .. TRI_ENABLE = 0 */
7306 /* .. ==> 0XF8000788[0:0] = 0x00000000U */
7307 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
7308 /* .. L0_SEL = 0 */
7309 /* .. ==> 0XF8000788[1:1] = 0x00000000U */
7310 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
7311 /* .. L1_SEL = 1 */
7312 /* .. ==> 0XF8000788[2:2] = 0x00000001U */
7313 /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
7314 /* .. L2_SEL = 0 */
7315 /* .. ==> 0XF8000788[4:3] = 0x00000000U */
7316 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
7317 /* .. L3_SEL = 0 */
7318 /* .. ==> 0XF8000788[7:5] = 0x00000000U */
7319 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
7320 /* .. Speed = 1 */
7321 /* .. ==> 0XF8000788[8:8] = 0x00000001U */
7322 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
7323 /* .. IO_Type = 1 */
7324 /* .. ==> 0XF8000788[11:9] = 0x00000001U */
7325 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
7326 /* .. PULLUP = 0 */
7327 /* .. ==> 0XF8000788[12:12] = 0x00000000U */
7328 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
7329 /* .. DisableRcvr = 0 */
7330 /* .. ==> 0XF8000788[13:13] = 0x00000000U */
7331 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
7332 /* .. */
7333 EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00000304U),
7334 /* .. TRI_ENABLE = 0 */
7335 /* .. ==> 0XF800078C[0:0] = 0x00000000U */
7336 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
7337 /* .. L0_SEL = 0 */
7338 /* .. ==> 0XF800078C[1:1] = 0x00000000U */
7339 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
7340 /* .. L1_SEL = 1 */
7341 /* .. ==> 0XF800078C[2:2] = 0x00000001U */
7342 /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
7343 /* .. L2_SEL = 0 */
7344 /* .. ==> 0XF800078C[4:3] = 0x00000000U */
7345 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
7346 /* .. L3_SEL = 0 */
7347 /* .. ==> 0XF800078C[7:5] = 0x00000000U */
7348 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
7349 /* .. Speed = 1 */
7350 /* .. ==> 0XF800078C[8:8] = 0x00000001U */
7351 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
7352 /* .. IO_Type = 1 */
7353 /* .. ==> 0XF800078C[11:9] = 0x00000001U */
7354 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
7355 /* .. PULLUP = 0 */
7356 /* .. ==> 0XF800078C[12:12] = 0x00000000U */
7357 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
7358 /* .. DisableRcvr = 0 */
7359 /* .. ==> 0XF800078C[13:13] = 0x00000000U */
7360 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
7361 /* .. */
7362 EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00000304U),
7363 /* .. TRI_ENABLE = 1 */
7364 /* .. ==> 0XF8000790[0:0] = 0x00000001U */
7365 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
7366 /* .. L0_SEL = 0 */
7367 /* .. ==> 0XF8000790[1:1] = 0x00000000U */
7368 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
7369 /* .. L1_SEL = 1 */
7370 /* .. ==> 0XF8000790[2:2] = 0x00000001U */
7371 /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
7372 /* .. L2_SEL = 0 */
7373 /* .. ==> 0XF8000790[4:3] = 0x00000000U */
7374 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
7375 /* .. L3_SEL = 0 */
7376 /* .. ==> 0XF8000790[7:5] = 0x00000000U */
7377 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
7378 /* .. Speed = 1 */
7379 /* .. ==> 0XF8000790[8:8] = 0x00000001U */
7380 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
7381 /* .. IO_Type = 1 */
7382 /* .. ==> 0XF8000790[11:9] = 0x00000001U */
7383 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
7384 /* .. PULLUP = 0 */
7385 /* .. ==> 0XF8000790[12:12] = 0x00000000U */
7386 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
7387 /* .. DisableRcvr = 0 */
7388 /* .. ==> 0XF8000790[13:13] = 0x00000000U */
7389 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
7390 /* .. */
7391 EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00000305U),
7392 /* .. TRI_ENABLE = 0 */
7393 /* .. ==> 0XF8000794[0:0] = 0x00000000U */
7394 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
7395 /* .. L0_SEL = 0 */
7396 /* .. ==> 0XF8000794[1:1] = 0x00000000U */
7397 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
7398 /* .. L1_SEL = 1 */
7399 /* .. ==> 0XF8000794[2:2] = 0x00000001U */
7400 /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
7401 /* .. L2_SEL = 0 */
7402 /* .. ==> 0XF8000794[4:3] = 0x00000000U */
7403 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
7404 /* .. L3_SEL = 0 */
7405 /* .. ==> 0XF8000794[7:5] = 0x00000000U */
7406 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
7407 /* .. Speed = 1 */
7408 /* .. ==> 0XF8000794[8:8] = 0x00000001U */
7409 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
7410 /* .. IO_Type = 1 */
7411 /* .. ==> 0XF8000794[11:9] = 0x00000001U */
7412 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
7413 /* .. PULLUP = 0 */
7414 /* .. ==> 0XF8000794[12:12] = 0x00000000U */
7415 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
7416 /* .. DisableRcvr = 0 */
7417 /* .. ==> 0XF8000794[13:13] = 0x00000000U */
7418 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
7419 /* .. */
7420 EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00000304U),
7421 /* .. TRI_ENABLE = 0 */
7422 /* .. ==> 0XF8000798[0:0] = 0x00000000U */
7423 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
7424 /* .. L0_SEL = 0 */
7425 /* .. ==> 0XF8000798[1:1] = 0x00000000U */
7426 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
7427 /* .. L1_SEL = 1 */
7428 /* .. ==> 0XF8000798[2:2] = 0x00000001U */
7429 /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
7430 /* .. L2_SEL = 0 */
7431 /* .. ==> 0XF8000798[4:3] = 0x00000000U */
7432 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
7433 /* .. L3_SEL = 0 */
7434 /* .. ==> 0XF8000798[7:5] = 0x00000000U */
7435 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
7436 /* .. Speed = 1 */
7437 /* .. ==> 0XF8000798[8:8] = 0x00000001U */
7438 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
7439 /* .. IO_Type = 1 */
7440 /* .. ==> 0XF8000798[11:9] = 0x00000001U */
7441 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
7442 /* .. PULLUP = 0 */
7443 /* .. ==> 0XF8000798[12:12] = 0x00000000U */
7444 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
7445 /* .. DisableRcvr = 0 */
7446 /* .. ==> 0XF8000798[13:13] = 0x00000000U */
7447 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
7448 /* .. */
7449 EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00000304U),
7450 /* .. TRI_ENABLE = 0 */
7451 /* .. ==> 0XF800079C[0:0] = 0x00000000U */
7452 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
7453 /* .. L0_SEL = 0 */
7454 /* .. ==> 0XF800079C[1:1] = 0x00000000U */
7455 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
7456 /* .. L1_SEL = 1 */
7457 /* .. ==> 0XF800079C[2:2] = 0x00000001U */
7458 /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
7459 /* .. L2_SEL = 0 */
7460 /* .. ==> 0XF800079C[4:3] = 0x00000000U */
7461 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
7462 /* .. L3_SEL = 0 */
7463 /* .. ==> 0XF800079C[7:5] = 0x00000000U */
7464 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
7465 /* .. Speed = 1 */
7466 /* .. ==> 0XF800079C[8:8] = 0x00000001U */
7467 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
7468 /* .. IO_Type = 1 */
7469 /* .. ==> 0XF800079C[11:9] = 0x00000001U */
7470 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
7471 /* .. PULLUP = 0 */
7472 /* .. ==> 0XF800079C[12:12] = 0x00000000U */
7473 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
7474 /* .. DisableRcvr = 0 */
7475 /* .. ==> 0XF800079C[13:13] = 0x00000000U */
7476 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
7477 /* .. */
7478 EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00000304U),
7479 /* .. TRI_ENABLE = 0 */
7480 /* .. ==> 0XF80007A0[0:0] = 0x00000000U */
7481 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
7482 /* .. L0_SEL = 0 */
7483 /* .. ==> 0XF80007A0[1:1] = 0x00000000U */
7484 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
7485 /* .. L1_SEL = 0 */
7486 /* .. ==> 0XF80007A0[2:2] = 0x00000000U */
7487 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
7488 /* .. L2_SEL = 0 */
7489 /* .. ==> 0XF80007A0[4:3] = 0x00000000U */
7490 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
7491 /* .. L3_SEL = 4 */
7492 /* .. ==> 0XF80007A0[7:5] = 0x00000004U */
7493 /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
7494 /* .. Speed = 1 */
7495 /* .. ==> 0XF80007A0[8:8] = 0x00000001U */
7496 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
7497 /* .. IO_Type = 1 */
7498 /* .. ==> 0XF80007A0[11:9] = 0x00000001U */
7499 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
7500 /* .. PULLUP = 0 */
7501 /* .. ==> 0XF80007A0[12:12] = 0x00000000U */
7502 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
7503 /* .. DisableRcvr = 0 */
7504 /* .. ==> 0XF80007A0[13:13] = 0x00000000U */
7505 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
7506 /* .. */
7507 EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00000380U),
7508 /* .. TRI_ENABLE = 0 */
7509 /* .. ==> 0XF80007A4[0:0] = 0x00000000U */
7510 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
7511 /* .. L0_SEL = 0 */
7512 /* .. ==> 0XF80007A4[1:1] = 0x00000000U */
7513 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
7514 /* .. L1_SEL = 0 */
7515 /* .. ==> 0XF80007A4[2:2] = 0x00000000U */
7516 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
7517 /* .. L2_SEL = 0 */
7518 /* .. ==> 0XF80007A4[4:3] = 0x00000000U */
7519 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
7520 /* .. L3_SEL = 4 */
7521 /* .. ==> 0XF80007A4[7:5] = 0x00000004U */
7522 /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
7523 /* .. Speed = 1 */
7524 /* .. ==> 0XF80007A4[8:8] = 0x00000001U */
7525 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
7526 /* .. IO_Type = 1 */
7527 /* .. ==> 0XF80007A4[11:9] = 0x00000001U */
7528 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
7529 /* .. PULLUP = 0 */
7530 /* .. ==> 0XF80007A4[12:12] = 0x00000000U */
7531 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
7532 /* .. DisableRcvr = 0 */
7533 /* .. ==> 0XF80007A4[13:13] = 0x00000000U */
7534 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
7535 /* .. */
7536 EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00000380U),
7537 /* .. TRI_ENABLE = 0 */
7538 /* .. ==> 0XF80007A8[0:0] = 0x00000000U */
7539 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
7540 /* .. L0_SEL = 0 */
7541 /* .. ==> 0XF80007A8[1:1] = 0x00000000U */
7542 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
7543 /* .. L1_SEL = 0 */
7544 /* .. ==> 0XF80007A8[2:2] = 0x00000000U */
7545 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
7546 /* .. L2_SEL = 0 */
7547 /* .. ==> 0XF80007A8[4:3] = 0x00000000U */
7548 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
7549 /* .. L3_SEL = 4 */
7550 /* .. ==> 0XF80007A8[7:5] = 0x00000004U */
7551 /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
7552 /* .. Speed = 1 */
7553 /* .. ==> 0XF80007A8[8:8] = 0x00000001U */
7554 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
7555 /* .. IO_Type = 1 */
7556 /* .. ==> 0XF80007A8[11:9] = 0x00000001U */
7557 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
7558 /* .. PULLUP = 0 */
7559 /* .. ==> 0XF80007A8[12:12] = 0x00000000U */
7560 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
7561 /* .. DisableRcvr = 0 */
7562 /* .. ==> 0XF80007A8[13:13] = 0x00000000U */
7563 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
7564 /* .. */
7565 EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00000380U),
7566 /* .. TRI_ENABLE = 0 */
7567 /* .. ==> 0XF80007AC[0:0] = 0x00000000U */
7568 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
7569 /* .. L0_SEL = 0 */
7570 /* .. ==> 0XF80007AC[1:1] = 0x00000000U */
7571 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
7572 /* .. L1_SEL = 0 */
7573 /* .. ==> 0XF80007AC[2:2] = 0x00000000U */
7574 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
7575 /* .. L2_SEL = 0 */
7576 /* .. ==> 0XF80007AC[4:3] = 0x00000000U */
7577 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
7578 /* .. L3_SEL = 4 */
7579 /* .. ==> 0XF80007AC[7:5] = 0x00000004U */
7580 /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
7581 /* .. Speed = 1 */
7582 /* .. ==> 0XF80007AC[8:8] = 0x00000001U */
7583 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
7584 /* .. IO_Type = 1 */
7585 /* .. ==> 0XF80007AC[11:9] = 0x00000001U */
7586 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
7587 /* .. PULLUP = 0 */
7588 /* .. ==> 0XF80007AC[12:12] = 0x00000000U */
7589 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
7590 /* .. DisableRcvr = 0 */
7591 /* .. ==> 0XF80007AC[13:13] = 0x00000000U */
7592 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
7593 /* .. */
7594 EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00000380U),
7595 /* .. TRI_ENABLE = 0 */
7596 /* .. ==> 0XF80007B0[0:0] = 0x00000000U */
7597 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
7598 /* .. L0_SEL = 0 */
7599 /* .. ==> 0XF80007B0[1:1] = 0x00000000U */
7600 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
7601 /* .. L1_SEL = 0 */
7602 /* .. ==> 0XF80007B0[2:2] = 0x00000000U */
7603 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
7604 /* .. L2_SEL = 0 */
7605 /* .. ==> 0XF80007B0[4:3] = 0x00000000U */
7606 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
7607 /* .. L3_SEL = 4 */
7608 /* .. ==> 0XF80007B0[7:5] = 0x00000004U */
7609 /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
7610 /* .. Speed = 1 */
7611 /* .. ==> 0XF80007B0[8:8] = 0x00000001U */
7612 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
7613 /* .. IO_Type = 1 */
7614 /* .. ==> 0XF80007B0[11:9] = 0x00000001U */
7615 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
7616 /* .. PULLUP = 0 */
7617 /* .. ==> 0XF80007B0[12:12] = 0x00000000U */
7618 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
7619 /* .. DisableRcvr = 0 */
7620 /* .. ==> 0XF80007B0[13:13] = 0x00000000U */
7621 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
7622 /* .. */
7623 EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00000380U),
7624 /* .. TRI_ENABLE = 0 */
7625 /* .. ==> 0XF80007B4[0:0] = 0x00000000U */
7626 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
7627 /* .. L0_SEL = 0 */
7628 /* .. ==> 0XF80007B4[1:1] = 0x00000000U */
7629 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
7630 /* .. L1_SEL = 0 */
7631 /* .. ==> 0XF80007B4[2:2] = 0x00000000U */
7632 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
7633 /* .. L2_SEL = 0 */
7634 /* .. ==> 0XF80007B4[4:3] = 0x00000000U */
7635 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
7636 /* .. L3_SEL = 4 */
7637 /* .. ==> 0XF80007B4[7:5] = 0x00000004U */
7638 /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
7639 /* .. Speed = 1 */
7640 /* .. ==> 0XF80007B4[8:8] = 0x00000001U */
7641 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
7642 /* .. IO_Type = 1 */
7643 /* .. ==> 0XF80007B4[11:9] = 0x00000001U */
7644 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
7645 /* .. PULLUP = 0 */
7646 /* .. ==> 0XF80007B4[12:12] = 0x00000000U */
7647 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
7648 /* .. DisableRcvr = 0 */
7649 /* .. ==> 0XF80007B4[13:13] = 0x00000000U */
7650 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
7651 /* .. */
7652 EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00000380U),
Michal Simek264065f2016-03-03 13:25:03 +0100[diff] [blame]7653 /* .. TRI_ENABLE = 0 */
7654 /* .. ==> 0XF80007B8[0:0] = 0x00000000U */
7655 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
7656 /* .. L0_SEL = 0 */
7657 /* .. ==> 0XF80007B8[1:1] = 0x00000000U */
7658 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
7659 /* .. L1_SEL = 0 */
7660 /* .. ==> 0XF80007B8[2:2] = 0x00000000U */
7661 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
7662 /* .. L2_SEL = 0 */
7663 /* .. ==> 0XF80007B8[4:3] = 0x00000000U */
7664 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
7665 /* .. L3_SEL = 0 */
7666 /* .. ==> 0XF80007B8[7:5] = 0x00000000U */
7667 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
7668 /* .. Speed = 0 */
7669 /* .. ==> 0XF80007B8[8:8] = 0x00000000U */
7670 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
7671 /* .. IO_Type = 1 */
7672 /* .. ==> 0XF80007B8[11:9] = 0x00000001U */
7673 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
7674 /* .. PULLUP = 1 */
7675 /* .. ==> 0XF80007B8[12:12] = 0x00000001U */
7676 /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
7677 /* .. DisableRcvr = 0 */
7678 /* .. ==> 0XF80007B8[13:13] = 0x00000000U */
7679 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
7680 /* .. */
7681 EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00001200U),
Nathan Rossi4eeed0e2015-11-24 19:34:09 +1000[diff] [blame]7682 /* .. TRI_ENABLE = 1 */
7683 /* .. ==> 0XF80007BC[0:0] = 0x00000001U */
7684 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
7685 /* .. Speed = 0 */
7686 /* .. ==> 0XF80007BC[8:8] = 0x00000000U */
7687 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
7688 /* .. IO_Type = 1 */
7689 /* .. ==> 0XF80007BC[11:9] = 0x00000001U */
7690 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
7691 /* .. PULLUP = 0 */
7692 /* .. ==> 0XF80007BC[12:12] = 0x00000000U */
7693 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
7694 /* .. DisableRcvr = 0 */
7695 /* .. ==> 0XF80007BC[13:13] = 0x00000000U */
7696 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
7697 /* .. */
7698 EMIT_MASKWRITE(0XF80007BC, 0x00003F01U, 0x00000201U),
7699 /* .. TRI_ENABLE = 0 */
7700 /* .. ==> 0XF80007C0[0:0] = 0x00000000U */
7701 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
7702 /* .. L0_SEL = 0 */
7703 /* .. ==> 0XF80007C0[1:1] = 0x00000000U */
7704 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
7705 /* .. L1_SEL = 0 */
7706 /* .. ==> 0XF80007C0[2:2] = 0x00000000U */
7707 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
7708 /* .. L2_SEL = 0 */
7709 /* .. ==> 0XF80007C0[4:3] = 0x00000000U */
7710 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
7711 /* .. L3_SEL = 7 */
7712 /* .. ==> 0XF80007C0[7:5] = 0x00000007U */
7713 /* .. ==> MASK : 0x000000E0U VAL : 0x000000E0U */
7714 /* .. Speed = 0 */
7715 /* .. ==> 0XF80007C0[8:8] = 0x00000000U */
7716 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
7717 /* .. IO_Type = 1 */
7718 /* .. ==> 0XF80007C0[11:9] = 0x00000001U */
7719 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
7720 /* .. PULLUP = 0 */
7721 /* .. ==> 0XF80007C0[12:12] = 0x00000000U */
7722 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
7723 /* .. DisableRcvr = 0 */
7724 /* .. ==> 0XF80007C0[13:13] = 0x00000000U */
7725 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
7726 /* .. */
7727 EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x000002E0U),
7728 /* .. TRI_ENABLE = 1 */
7729 /* .. ==> 0XF80007C4[0:0] = 0x00000001U */
7730 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
7731 /* .. L0_SEL = 0 */
7732 /* .. ==> 0XF80007C4[1:1] = 0x00000000U */
7733 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
7734 /* .. L1_SEL = 0 */
7735 /* .. ==> 0XF80007C4[2:2] = 0x00000000U */
7736 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
7737 /* .. L2_SEL = 0 */
7738 /* .. ==> 0XF80007C4[4:3] = 0x00000000U */
7739 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
7740 /* .. L3_SEL = 7 */
7741 /* .. ==> 0XF80007C4[7:5] = 0x00000007U */
7742 /* .. ==> MASK : 0x000000E0U VAL : 0x000000E0U */
7743 /* .. Speed = 0 */
7744 /* .. ==> 0XF80007C4[8:8] = 0x00000000U */
7745 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
7746 /* .. IO_Type = 1 */
7747 /* .. ==> 0XF80007C4[11:9] = 0x00000001U */
7748 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
7749 /* .. PULLUP = 0 */
7750 /* .. ==> 0XF80007C4[12:12] = 0x00000000U */
7751 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
7752 /* .. DisableRcvr = 0 */
7753 /* .. ==> 0XF80007C4[13:13] = 0x00000000U */
7754 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
7755 /* .. */
7756 EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x000002E1U),
7757 /* .. TRI_ENABLE = 0 */
Michal Simek264065f2016-03-03 13:25:03 +0100[diff] [blame]7758 /* .. ==> 0XF80007C8[0:0] = 0x00000000U */
7759 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
7760 /* .. L0_SEL = 0 */
7761 /* .. ==> 0XF80007C8[1:1] = 0x00000000U */
7762 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
7763 /* .. L1_SEL = 0 */
7764 /* .. ==> 0XF80007C8[2:2] = 0x00000000U */
7765 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
7766 /* .. L2_SEL = 0 */
7767 /* .. ==> 0XF80007C8[4:3] = 0x00000000U */
7768 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
7769 /* .. L3_SEL = 0 */
7770 /* .. ==> 0XF80007C8[7:5] = 0x00000000U */
7771 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
7772 /* .. Speed = 0 */
7773 /* .. ==> 0XF80007C8[8:8] = 0x00000000U */
7774 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
7775 /* .. IO_Type = 1 */
7776 /* .. ==> 0XF80007C8[11:9] = 0x00000001U */
7777 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
7778 /* .. PULLUP = 0 */
7779 /* .. ==> 0XF80007C8[12:12] = 0x00000000U */
7780 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
7781 /* .. DisableRcvr = 0 */
7782 /* .. ==> 0XF80007C8[13:13] = 0x00000000U */
7783 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
7784 /* .. */
7785 EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x00000200U),
7786 /* .. TRI_ENABLE = 0 */
7787 /* .. ==> 0XF80007CC[0:0] = 0x00000000U */
7788 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
7789 /* .. L0_SEL = 0 */
7790 /* .. ==> 0XF80007CC[1:1] = 0x00000000U */
7791 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
7792 /* .. L1_SEL = 0 */
7793 /* .. ==> 0XF80007CC[2:2] = 0x00000000U */
7794 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
7795 /* .. L2_SEL = 0 */
7796 /* .. ==> 0XF80007CC[4:3] = 0x00000000U */
7797 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
7798 /* .. L3_SEL = 0 */
7799 /* .. ==> 0XF80007CC[7:5] = 0x00000000U */
7800 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
7801 /* .. Speed = 0 */
7802 /* .. ==> 0XF80007CC[8:8] = 0x00000000U */
7803 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
7804 /* .. IO_Type = 1 */
7805 /* .. ==> 0XF80007CC[11:9] = 0x00000001U */
7806 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
7807 /* .. PULLUP = 0 */
7808 /* .. ==> 0XF80007CC[12:12] = 0x00000000U */
7809 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
7810 /* .. DisableRcvr = 0 */
7811 /* .. ==> 0XF80007CC[13:13] = 0x00000000U */
7812 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
7813 /* .. */
7814 EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x00000200U),
7815 /* .. TRI_ENABLE = 0 */
Nathan Rossi4eeed0e2015-11-24 19:34:09 +1000[diff] [blame]7816 /* .. ==> 0XF80007D0[0:0] = 0x00000000U */
7817 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
7818 /* .. L0_SEL = 0 */
7819 /* .. ==> 0XF80007D0[1:1] = 0x00000000U */
7820 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
7821 /* .. L1_SEL = 0 */
7822 /* .. ==> 0XF80007D0[2:2] = 0x00000000U */
7823 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
7824 /* .. L2_SEL = 0 */
7825 /* .. ==> 0XF80007D0[4:3] = 0x00000000U */
7826 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
7827 /* .. L3_SEL = 4 */
7828 /* .. ==> 0XF80007D0[7:5] = 0x00000004U */
7829 /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
7830 /* .. Speed = 0 */
7831 /* .. ==> 0XF80007D0[8:8] = 0x00000000U */
7832 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
7833 /* .. IO_Type = 1 */
7834 /* .. ==> 0XF80007D0[11:9] = 0x00000001U */
7835 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
7836 /* .. PULLUP = 0 */
7837 /* .. ==> 0XF80007D0[12:12] = 0x00000000U */
7838 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
7839 /* .. DisableRcvr = 0 */
7840 /* .. ==> 0XF80007D0[13:13] = 0x00000000U */
7841 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
7842 /* .. */
7843 EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00000280U),
7844 /* .. TRI_ENABLE = 0 */
7845 /* .. ==> 0XF80007D4[0:0] = 0x00000000U */
7846 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
7847 /* .. L0_SEL = 0 */
7848 /* .. ==> 0XF80007D4[1:1] = 0x00000000U */
7849 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
7850 /* .. L1_SEL = 0 */
7851 /* .. ==> 0XF80007D4[2:2] = 0x00000000U */
7852 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
7853 /* .. L2_SEL = 0 */
7854 /* .. ==> 0XF80007D4[4:3] = 0x00000000U */
7855 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
7856 /* .. L3_SEL = 4 */
7857 /* .. ==> 0XF80007D4[7:5] = 0x00000004U */
7858 /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
7859 /* .. Speed = 0 */
7860 /* .. ==> 0XF80007D4[8:8] = 0x00000000U */
7861 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
7862 /* .. IO_Type = 1 */
7863 /* .. ==> 0XF80007D4[11:9] = 0x00000001U */
7864 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
7865 /* .. PULLUP = 0 */
7866 /* .. ==> 0XF80007D4[12:12] = 0x00000000U */
7867 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
7868 /* .. DisableRcvr = 0 */
7869 /* .. ==> 0XF80007D4[13:13] = 0x00000000U */
7870 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
7871 /* .. */
7872 EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00000280U),
7873 /* .. SDIO0_WP_SEL = 55 */
7874 /* .. ==> 0XF8000830[5:0] = 0x00000037U */
7875 /* .. ==> MASK : 0x0000003FU VAL : 0x00000037U */
7876 /* .. SDIO0_CD_SEL = 47 */
7877 /* .. ==> 0XF8000830[21:16] = 0x0000002FU */
7878 /* .. ==> MASK : 0x003F0000U VAL : 0x002F0000U */
7879 /* .. */
7880 EMIT_MASKWRITE(0XF8000830, 0x003F003FU, 0x002F0037U),
7881 /* .. FINISH: MIO PROGRAMMING */
7882 /* .. START: LOCK IT BACK */
7883 /* .. LOCK_KEY = 0X767B */
7884 /* .. ==> 0XF8000004[15:0] = 0x0000767BU */
7885 /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */
7886 /* .. */
7887 EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
7888 /* .. FINISH: LOCK IT BACK */
7889 /* FINISH: top */
7890 /* */
7891 EMIT_EXIT(),
7892
7893 /* */
7894};
7895
7896unsigned long ps7_peripherals_init_data_2_0[] = {
7897 /* START: top */
7898 /* .. START: SLCR SETTINGS */
7899 /* .. UNLOCK_KEY = 0XDF0D */
7900 /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
7901 /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */
7902 /* .. */
7903 EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
7904 /* .. FINISH: SLCR SETTINGS */
7905 /* .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS */
7906 /* .. IBUF_DISABLE_MODE = 0x1 */
7907 /* .. ==> 0XF8000B48[7:7] = 0x00000001U */
7908 /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */
7909 /* .. TERM_DISABLE_MODE = 0x1 */
7910 /* .. ==> 0XF8000B48[8:8] = 0x00000001U */
7911 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
7912 /* .. */
7913 EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U),
7914 /* .. IBUF_DISABLE_MODE = 0x1 */
7915 /* .. ==> 0XF8000B4C[7:7] = 0x00000001U */
7916 /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */
7917 /* .. TERM_DISABLE_MODE = 0x1 */
7918 /* .. ==> 0XF8000B4C[8:8] = 0x00000001U */
7919 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
7920 /* .. */
7921 EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U),
7922 /* .. IBUF_DISABLE_MODE = 0x1 */
7923 /* .. ==> 0XF8000B50[7:7] = 0x00000001U */
7924 /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */
7925 /* .. TERM_DISABLE_MODE = 0x1 */
7926 /* .. ==> 0XF8000B50[8:8] = 0x00000001U */
7927 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
7928 /* .. */
7929 EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
7930 /* .. IBUF_DISABLE_MODE = 0x1 */
7931 /* .. ==> 0XF8000B54[7:7] = 0x00000001U */
7932 /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */
7933 /* .. TERM_DISABLE_MODE = 0x1 */
7934 /* .. ==> 0XF8000B54[8:8] = 0x00000001U */
7935 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
7936 /* .. */
7937 EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
7938 /* .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS */
7939 /* .. START: LOCK IT BACK */
7940 /* .. LOCK_KEY = 0X767B */
7941 /* .. ==> 0XF8000004[15:0] = 0x0000767BU */
7942 /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */
7943 /* .. */
7944 EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
7945 /* .. FINISH: LOCK IT BACK */
7946 /* .. START: SRAM/NOR SET OPMODE */
7947 /* .. FINISH: SRAM/NOR SET OPMODE */
7948 /* .. START: UART REGISTERS */
7949 /* .. BDIV = 0x6 */
7950 /* .. ==> 0XE0001034[7:0] = 0x00000006U */
7951 /* .. ==> MASK : 0x000000FFU VAL : 0x00000006U */
7952 /* .. */
7953 EMIT_MASKWRITE(0XE0001034, 0x000000FFU, 0x00000006U),
Michal Simek264065f2016-03-03 13:25:03 +0100[diff] [blame]7954 /* .. CD = 0x7c */
7955 /* .. ==> 0XE0001018[15:0] = 0x0000007CU */
7956 /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU */
Nathan Rossi4eeed0e2015-11-24 19:34:09 +1000[diff] [blame]7957 /* .. */
Michal Simek264065f2016-03-03 13:25:03 +0100[diff] [blame]7958 EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000007CU),
Nathan Rossi4eeed0e2015-11-24 19:34:09 +1000[diff] [blame]7959 /* .. STPBRK = 0x0 */
7960 /* .. ==> 0XE0001000[8:8] = 0x00000000U */
7961 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
7962 /* .. STTBRK = 0x0 */
7963 /* .. ==> 0XE0001000[7:7] = 0x00000000U */
7964 /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
7965 /* .. RSTTO = 0x0 */
7966 /* .. ==> 0XE0001000[6:6] = 0x00000000U */
7967 /* .. ==> MASK : 0x00000040U VAL : 0x00000000U */
7968 /* .. TXDIS = 0x0 */
7969 /* .. ==> 0XE0001000[5:5] = 0x00000000U */
7970 /* .. ==> MASK : 0x00000020U VAL : 0x00000000U */
7971 /* .. TXEN = 0x1 */
7972 /* .. ==> 0XE0001000[4:4] = 0x00000001U */
7973 /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */
7974 /* .. RXDIS = 0x0 */
7975 /* .. ==> 0XE0001000[3:3] = 0x00000000U */
7976 /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
7977 /* .. RXEN = 0x1 */
7978 /* .. ==> 0XE0001000[2:2] = 0x00000001U */
7979 /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
7980 /* .. TXRES = 0x1 */
7981 /* .. ==> 0XE0001000[1:1] = 0x00000001U */
7982 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
7983 /* .. RXRES = 0x1 */
7984 /* .. ==> 0XE0001000[0:0] = 0x00000001U */
7985 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
7986 /* .. */
7987 EMIT_MASKWRITE(0XE0001000, 0x000001FFU, 0x00000017U),
7988 /* .. IRMODE = 0x0 */
7989 /* .. ==> 0XE0001004[11:11] = 0x00000000U */
7990 /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
7991 /* .. UCLKEN = 0x0 */
7992 /* .. ==> 0XE0001004[10:10] = 0x00000000U */
7993 /* .. ==> MASK : 0x00000400U VAL : 0x00000000U */
7994 /* .. CHMODE = 0x0 */
7995 /* .. ==> 0XE0001004[9:8] = 0x00000000U */
7996 /* .. ==> MASK : 0x00000300U VAL : 0x00000000U */
7997 /* .. NBSTOP = 0x0 */
7998 /* .. ==> 0XE0001004[7:6] = 0x00000000U */
7999 /* .. ==> MASK : 0x000000C0U VAL : 0x00000000U */
8000 /* .. PAR = 0x4 */
8001 /* .. ==> 0XE0001004[5:3] = 0x00000004U */
8002 /* .. ==> MASK : 0x00000038U VAL : 0x00000020U */
8003 /* .. CHRL = 0x0 */
8004 /* .. ==> 0XE0001004[2:1] = 0x00000000U */
8005 /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */
8006 /* .. CLKS = 0x0 */
8007 /* .. ==> 0XE0001004[0:0] = 0x00000000U */
8008 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
8009 /* .. */
8010 EMIT_MASKWRITE(0XE0001004, 0x00000FFFU, 0x00000020U),
8011 /* .. FINISH: UART REGISTERS */
Nathan Rossi4eeed0e2015-11-24 19:34:09 +1000[diff] [blame]8012 /* .. START: QSPI REGISTERS */
8013 /* .. Holdb_dr = 1 */
8014 /* .. ==> 0XE000D000[19:19] = 0x00000001U */
8015 /* .. ==> MASK : 0x00080000U VAL : 0x00080000U */
8016 /* .. */
8017 EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U),
8018 /* .. FINISH: QSPI REGISTERS */
8019 /* .. START: PL POWER ON RESET REGISTERS */
8020 /* .. PCFG_POR_CNT_4K = 0 */
8021 /* .. ==> 0XF8007000[29:29] = 0x00000000U */
8022 /* .. ==> MASK : 0x20000000U VAL : 0x00000000U */
8023 /* .. */
8024 EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
8025 /* .. FINISH: PL POWER ON RESET REGISTERS */
8026 /* .. START: SMC TIMING CALCULATION REGISTER UPDATE */
8027 /* .. .. START: NAND SET CYCLE */
8028 /* .. .. FINISH: NAND SET CYCLE */
8029 /* .. .. START: OPMODE */
8030 /* .. .. FINISH: OPMODE */
8031 /* .. .. START: DIRECT COMMAND */
8032 /* .. .. FINISH: DIRECT COMMAND */
8033 /* .. .. START: SRAM/NOR CS0 SET CYCLE */
8034 /* .. .. FINISH: SRAM/NOR CS0 SET CYCLE */
8035 /* .. .. START: DIRECT COMMAND */
8036 /* .. .. FINISH: DIRECT COMMAND */
8037 /* .. .. START: NOR CS0 BASE ADDRESS */
8038 /* .. .. FINISH: NOR CS0 BASE ADDRESS */
8039 /* .. .. START: SRAM/NOR CS1 SET CYCLE */
8040 /* .. .. FINISH: SRAM/NOR CS1 SET CYCLE */
8041 /* .. .. START: DIRECT COMMAND */
8042 /* .. .. FINISH: DIRECT COMMAND */
8043 /* .. .. START: NOR CS1 BASE ADDRESS */
8044 /* .. .. FINISH: NOR CS1 BASE ADDRESS */
8045 /* .. .. START: USB RESET */
8046 /* .. .. .. START: USB0 RESET */
8047 /* .. .. .. .. START: DIR MODE BANK 0 */
8048 /* .. .. .. .. FINISH: DIR MODE BANK 0 */
8049 /* .. .. .. .. START: DIR MODE BANK 1 */
Michal Simek264065f2016-03-03 13:25:03 +0100[diff] [blame]8050 /* .. .. .. .. DIRECTION_1 = 0x4000 */
8051 /* .. .. .. .. ==> 0XE000A244[21:0] = 0x00004000U */
8052 /* .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U */
8053 /* .. .. .. .. */
8054 EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU, 0x00004000U),
Nathan Rossi4eeed0e2015-11-24 19:34:09 +1000[diff] [blame]8055 /* .. .. .. .. FINISH: DIR MODE BANK 1 */
8056 /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
8057 /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
8058 /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
8059 /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
8060 /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
Michal Simek264065f2016-03-03 13:25:03 +0100[diff] [blame]8061 /* .. .. .. .. MASK_1_LSW = 0xbfff */
8062 /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
8063 /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */
8064 /* .. .. .. .. DATA_1_LSW = 0x4000 */
8065 /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U */
8066 /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U */
8067 /* .. .. .. .. */
8068 EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U),
Nathan Rossi4eeed0e2015-11-24 19:34:09 +1000[diff] [blame]8069 /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
8070 /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
8071 /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
8072 /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
8073 /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
8074 /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
Michal Simek264065f2016-03-03 13:25:03 +0100[diff] [blame]8075 /* .. .. .. .. OP_ENABLE_1 = 0x4000 */
8076 /* .. .. .. .. ==> 0XE000A248[21:0] = 0x00004000U */
8077 /* .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U */
8078 /* .. .. .. .. */
8079 EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU, 0x00004000U),
Nathan Rossi4eeed0e2015-11-24 19:34:09 +1000[diff] [blame]8080 /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
8081 /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
8082 /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
8083 /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
8084 /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
8085 /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
Michal Simek264065f2016-03-03 13:25:03 +0100[diff] [blame]8086 /* .. .. .. .. MASK_1_LSW = 0xbfff */
8087 /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
8088 /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */
8089 /* .. .. .. .. DATA_1_LSW = 0x0 */
8090 /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U */
8091 /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U */
8092 /* .. .. .. .. */
8093 EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF0000U),
Nathan Rossi4eeed0e2015-11-24 19:34:09 +1000[diff] [blame]8094 /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
8095 /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
8096 /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
8097 /* .. .. .. .. START: ADD 1 MS DELAY */
8098 /* .. .. .. .. */
8099 EMIT_MASKDELAY(0XF8F00200, 1),
8100 /* .. .. .. .. FINISH: ADD 1 MS DELAY */
8101 /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
8102 /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
8103 /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
8104 /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
8105 /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
Michal Simek264065f2016-03-03 13:25:03 +0100[diff] [blame]8106 /* .. .. .. .. MASK_1_LSW = 0xbfff */
8107 /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
8108 /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */
8109 /* .. .. .. .. DATA_1_LSW = 0x4000 */
8110 /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U */
8111 /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U */
8112 /* .. .. .. .. */
8113 EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U),
Nathan Rossi4eeed0e2015-11-24 19:34:09 +1000[diff] [blame]8114 /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
8115 /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
8116 /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
8117 /* .. .. .. FINISH: USB0 RESET */
8118 /* .. .. .. START: USB1 RESET */
8119 /* .. .. .. .. START: DIR MODE BANK 0 */
8120 /* .. .. .. .. FINISH: DIR MODE BANK 0 */
8121 /* .. .. .. .. START: DIR MODE BANK 1 */
8122 /* .. .. .. .. FINISH: DIR MODE BANK 1 */
8123 /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
8124 /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
8125 /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
8126 /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
8127 /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
8128 /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
8129 /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
8130 /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
8131 /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
8132 /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
8133 /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
8134 /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
8135 /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
8136 /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
8137 /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
8138 /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
8139 /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
8140 /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
8141 /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
8142 /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
8143 /* .. .. .. .. START: ADD 1 MS DELAY */
8144 /* .. .. .. .. */
8145 EMIT_MASKDELAY(0XF8F00200, 1),
8146 /* .. .. .. .. FINISH: ADD 1 MS DELAY */
8147 /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
8148 /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
8149 /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
8150 /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
8151 /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
8152 /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
8153 /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
8154 /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
8155 /* .. .. .. FINISH: USB1 RESET */
8156 /* .. .. FINISH: USB RESET */
8157 /* .. .. START: ENET RESET */
8158 /* .. .. .. START: ENET0 RESET */
8159 /* .. .. .. .. START: DIR MODE BANK 0 */
8160 /* .. .. .. .. FINISH: DIR MODE BANK 0 */
8161 /* .. .. .. .. START: DIR MODE BANK 1 */
8162 /* .. .. .. .. FINISH: DIR MODE BANK 1 */
8163 /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
8164 /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
8165 /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
8166 /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
8167 /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
8168 /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
8169 /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
8170 /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
8171 /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
8172 /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
8173 /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
8174 /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
8175 /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
8176 /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
8177 /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
8178 /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
8179 /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
8180 /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
8181 /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
8182 /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
8183 /* .. .. .. .. START: ADD 1 MS DELAY */
8184 /* .. .. .. .. */
8185 EMIT_MASKDELAY(0XF8F00200, 1),
8186 /* .. .. .. .. FINISH: ADD 1 MS DELAY */
8187 /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
8188 /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
8189 /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
8190 /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
8191 /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
8192 /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
8193 /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
8194 /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
8195 /* .. .. .. FINISH: ENET0 RESET */
8196 /* .. .. .. START: ENET1 RESET */
8197 /* .. .. .. .. START: DIR MODE BANK 0 */
8198 /* .. .. .. .. FINISH: DIR MODE BANK 0 */
8199 /* .. .. .. .. START: DIR MODE BANK 1 */
8200 /* .. .. .. .. FINISH: DIR MODE BANK 1 */
8201 /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
8202 /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
8203 /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
8204 /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
8205 /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
8206 /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
8207 /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
8208 /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
8209 /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
8210 /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
8211 /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
8212 /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
8213 /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
8214 /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
8215 /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
8216 /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
8217 /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
8218 /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
8219 /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
8220 /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
8221 /* .. .. .. .. START: ADD 1 MS DELAY */
8222 /* .. .. .. .. */
8223 EMIT_MASKDELAY(0XF8F00200, 1),
8224 /* .. .. .. .. FINISH: ADD 1 MS DELAY */
8225 /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
8226 /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
8227 /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
8228 /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
8229 /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
8230 /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
8231 /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
8232 /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
8233 /* .. .. .. FINISH: ENET1 RESET */
8234 /* .. .. FINISH: ENET RESET */
8235 /* .. .. START: I2C RESET */
8236 /* .. .. .. START: I2C0 RESET */
8237 /* .. .. .. .. START: DIR MODE GPIO BANK0 */
8238 /* .. .. .. .. FINISH: DIR MODE GPIO BANK0 */
8239 /* .. .. .. .. START: DIR MODE GPIO BANK1 */
8240 /* .. .. .. .. FINISH: DIR MODE GPIO BANK1 */
8241 /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
8242 /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
8243 /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
8244 /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
8245 /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
8246 /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
8247 /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
8248 /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
8249 /* .. .. .. .. START: OUTPUT ENABLE */
8250 /* .. .. .. .. FINISH: OUTPUT ENABLE */
8251 /* .. .. .. .. START: OUTPUT ENABLE */
8252 /* .. .. .. .. FINISH: OUTPUT ENABLE */
8253 /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
8254 /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
8255 /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
8256 /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
8257 /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
8258 /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
8259 /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
8260 /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
8261 /* .. .. .. .. START: ADD 1 MS DELAY */
8262 /* .. .. .. .. */
8263 EMIT_MASKDELAY(0XF8F00200, 1),
8264 /* .. .. .. .. FINISH: ADD 1 MS DELAY */
8265 /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
8266 /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
8267 /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
8268 /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
8269 /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
8270 /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
8271 /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
8272 /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
8273 /* .. .. .. FINISH: I2C0 RESET */
8274 /* .. .. .. START: I2C1 RESET */
8275 /* .. .. .. .. START: DIR MODE GPIO BANK0 */
8276 /* .. .. .. .. FINISH: DIR MODE GPIO BANK0 */
8277 /* .. .. .. .. START: DIR MODE GPIO BANK1 */
8278 /* .. .. .. .. FINISH: DIR MODE GPIO BANK1 */
8279 /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
8280 /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
8281 /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
8282 /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
8283 /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
8284 /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
8285 /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
8286 /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
8287 /* .. .. .. .. START: OUTPUT ENABLE */
8288 /* .. .. .. .. FINISH: OUTPUT ENABLE */
8289 /* .. .. .. .. START: OUTPUT ENABLE */
8290 /* .. .. .. .. FINISH: OUTPUT ENABLE */
8291 /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
8292 /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
8293 /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
8294 /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
8295 /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
8296 /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
8297 /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
8298 /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
8299 /* .. .. .. .. START: ADD 1 MS DELAY */
8300 /* .. .. .. .. */
8301 EMIT_MASKDELAY(0XF8F00200, 1),
8302 /* .. .. .. .. FINISH: ADD 1 MS DELAY */
8303 /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
8304 /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
8305 /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
8306 /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
8307 /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
8308 /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
8309 /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
8310 /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
8311 /* .. .. .. FINISH: I2C1 RESET */
8312 /* .. .. FINISH: I2C RESET */
8313 /* .. .. START: NOR CHIP SELECT */
8314 /* .. .. .. START: DIR MODE BANK 0 */
8315 /* .. .. .. FINISH: DIR MODE BANK 0 */
8316 /* .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
8317 /* .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
8318 /* .. .. .. START: OUTPUT ENABLE BANK 0 */
8319 /* .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
8320 /* .. .. FINISH: NOR CHIP SELECT */
8321 /* .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE */
8322 /* FINISH: top */
8323 /* */
8324 EMIT_EXIT(),
8325
8326 /* */
8327};
8328
8329unsigned long ps7_post_config_2_0[] = {
8330 /* START: top */
8331 /* .. START: SLCR SETTINGS */
8332 /* .. UNLOCK_KEY = 0XDF0D */
8333 /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
8334 /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */
8335 /* .. */
8336 EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
8337 /* .. FINISH: SLCR SETTINGS */
8338 /* .. START: ENABLING LEVEL SHIFTER */
8339 /* .. USER_INP_ICT_EN_0 = 3 */
8340 /* .. ==> 0XF8000900[1:0] = 0x00000003U */
8341 /* .. ==> MASK : 0x00000003U VAL : 0x00000003U */
8342 /* .. USER_INP_ICT_EN_1 = 3 */
8343 /* .. ==> 0XF8000900[3:2] = 0x00000003U */
8344 /* .. ==> MASK : 0x0000000CU VAL : 0x0000000CU */
8345 /* .. */
8346 EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU),
Michal Simek264065f2016-03-03 13:25:03 +0100[diff] [blame]8347 /* .. FINISH: ENABLING LEVEL SHIFTER */
Nathan Rossi4eeed0e2015-11-24 19:34:09 +1000[diff] [blame]8348 /* .. START: FPGA RESETS TO 0 */
8349 /* .. reserved_3 = 0 */
8350 /* .. ==> 0XF8000240[31:25] = 0x00000000U */
8351 /* .. ==> MASK : 0xFE000000U VAL : 0x00000000U */
8352 /* .. FPGA_ACP_RST = 0 */
8353 /* .. ==> 0XF8000240[24:24] = 0x00000000U */
8354 /* .. ==> MASK : 0x01000000U VAL : 0x00000000U */
8355 /* .. FPGA_AXDS3_RST = 0 */
8356 /* .. ==> 0XF8000240[23:23] = 0x00000000U */
8357 /* .. ==> MASK : 0x00800000U VAL : 0x00000000U */
8358 /* .. FPGA_AXDS2_RST = 0 */
8359 /* .. ==> 0XF8000240[22:22] = 0x00000000U */
8360 /* .. ==> MASK : 0x00400000U VAL : 0x00000000U */
8361 /* .. FPGA_AXDS1_RST = 0 */
8362 /* .. ==> 0XF8000240[21:21] = 0x00000000U */
8363 /* .. ==> MASK : 0x00200000U VAL : 0x00000000U */
8364 /* .. FPGA_AXDS0_RST = 0 */
8365 /* .. ==> 0XF8000240[20:20] = 0x00000000U */
8366 /* .. ==> MASK : 0x00100000U VAL : 0x00000000U */
8367 /* .. reserved_2 = 0 */
8368 /* .. ==> 0XF8000240[19:18] = 0x00000000U */
8369 /* .. ==> MASK : 0x000C0000U VAL : 0x00000000U */
8370 /* .. FSSW1_FPGA_RST = 0 */
8371 /* .. ==> 0XF8000240[17:17] = 0x00000000U */
8372 /* .. ==> MASK : 0x00020000U VAL : 0x00000000U */
8373 /* .. FSSW0_FPGA_RST = 0 */
8374 /* .. ==> 0XF8000240[16:16] = 0x00000000U */
8375 /* .. ==> MASK : 0x00010000U VAL : 0x00000000U */
8376 /* .. reserved_1 = 0 */
8377 /* .. ==> 0XF8000240[15:14] = 0x00000000U */
8378 /* .. ==> MASK : 0x0000C000U VAL : 0x00000000U */
8379 /* .. FPGA_FMSW1_RST = 0 */
8380 /* .. ==> 0XF8000240[13:13] = 0x00000000U */
8381 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
8382 /* .. FPGA_FMSW0_RST = 0 */
8383 /* .. ==> 0XF8000240[12:12] = 0x00000000U */
8384 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
8385 /* .. FPGA_DMA3_RST = 0 */
8386 /* .. ==> 0XF8000240[11:11] = 0x00000000U */
8387 /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
8388 /* .. FPGA_DMA2_RST = 0 */
8389 /* .. ==> 0XF8000240[10:10] = 0x00000000U */
8390 /* .. ==> MASK : 0x00000400U VAL : 0x00000000U */
8391 /* .. FPGA_DMA1_RST = 0 */
8392 /* .. ==> 0XF8000240[9:9] = 0x00000000U */
8393 /* .. ==> MASK : 0x00000200U VAL : 0x00000000U */
8394 /* .. FPGA_DMA0_RST = 0 */
8395 /* .. ==> 0XF8000240[8:8] = 0x00000000U */
8396 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
8397 /* .. reserved = 0 */
8398 /* .. ==> 0XF8000240[7:4] = 0x00000000U */
8399 /* .. ==> MASK : 0x000000F0U VAL : 0x00000000U */
8400 /* .. FPGA3_OUT_RST = 0 */
8401 /* .. ==> 0XF8000240[3:3] = 0x00000000U */
8402 /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
8403 /* .. FPGA2_OUT_RST = 0 */
8404 /* .. ==> 0XF8000240[2:2] = 0x00000000U */
8405 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
8406 /* .. FPGA1_OUT_RST = 0 */
8407 /* .. ==> 0XF8000240[1:1] = 0x00000000U */
8408 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
8409 /* .. FPGA0_OUT_RST = 0 */
8410 /* .. ==> 0XF8000240[0:0] = 0x00000000U */
8411 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
8412 /* .. */
8413 EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U),
8414 /* .. FINISH: FPGA RESETS TO 0 */
8415 /* .. START: AFI REGISTERS */
8416 /* .. .. START: AFI0 REGISTERS */
8417 /* .. .. FINISH: AFI0 REGISTERS */
8418 /* .. .. START: AFI1 REGISTERS */
8419 /* .. .. FINISH: AFI1 REGISTERS */
8420 /* .. .. START: AFI2 REGISTERS */
8421 /* .. .. FINISH: AFI2 REGISTERS */
8422 /* .. .. START: AFI3 REGISTERS */
8423 /* .. .. FINISH: AFI3 REGISTERS */
8424 /* .. FINISH: AFI REGISTERS */
8425 /* .. START: LOCK IT BACK */
8426 /* .. LOCK_KEY = 0X767B */
8427 /* .. ==> 0XF8000004[15:0] = 0x0000767BU */
8428 /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */
8429 /* .. */
8430 EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
8431 /* .. FINISH: LOCK IT BACK */
8432 /* FINISH: top */
8433 /* */
8434 EMIT_EXIT(),
8435
8436 /* */
8437};
8438
Nathan Rossi4eeed0e2015-11-24 19:34:09 +1000[diff] [blame]8439
8440unsigned long ps7_pll_init_data_1_0[] = {
8441 /* START: top */
8442 /* .. START: SLCR SETTINGS */
8443 /* .. UNLOCK_KEY = 0XDF0D */
8444 /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
8445 /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */
8446 /* .. */
8447 EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
8448 /* .. FINISH: SLCR SETTINGS */
8449 /* .. START: PLL SLCR REGISTERS */
8450 /* .. .. START: ARM PLL INIT */
8451 /* .. .. PLL_RES = 0xc */
8452 /* .. .. ==> 0XF8000110[7:4] = 0x0000000CU */
8453 /* .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U */
8454 /* .. .. PLL_CP = 0x2 */
8455 /* .. .. ==> 0XF8000110[11:8] = 0x00000002U */
8456 /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */
8457 /* .. .. LOCK_CNT = 0x177 */
8458 /* .. .. ==> 0XF8000110[21:12] = 0x00000177U */
8459 /* .. .. ==> MASK : 0x003FF000U VAL : 0x00177000U */
8460 /* .. .. */
8461 EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x001772C0U),
8462 /* .. .. .. START: UPDATE FB_DIV */
8463 /* .. .. .. PLL_FDIV = 0x1a */
8464 /* .. .. .. ==> 0XF8000100[18:12] = 0x0000001AU */
8465 /* .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001A000U */
8466 /* .. .. .. */
8467 EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x0001A000U),
8468 /* .. .. .. FINISH: UPDATE FB_DIV */
8469 /* .. .. .. START: BY PASS PLL */
8470 /* .. .. .. PLL_BYPASS_FORCE = 1 */
8471 /* .. .. .. ==> 0XF8000100[4:4] = 0x00000001U */
8472 /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U */
8473 /* .. .. .. */
8474 EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U),
8475 /* .. .. .. FINISH: BY PASS PLL */
8476 /* .. .. .. START: ASSERT RESET */
8477 /* .. .. .. PLL_RESET = 1 */
8478 /* .. .. .. ==> 0XF8000100[0:0] = 0x00000001U */
8479 /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
8480 /* .. .. .. */
8481 EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U),
8482 /* .. .. .. FINISH: ASSERT RESET */
8483 /* .. .. .. START: DEASSERT RESET */
8484 /* .. .. .. PLL_RESET = 0 */
8485 /* .. .. .. ==> 0XF8000100[0:0] = 0x00000000U */
8486 /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
8487 /* .. .. .. */
8488 EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U),
8489 /* .. .. .. FINISH: DEASSERT RESET */
8490 /* .. .. .. START: CHECK PLL STATUS */
8491 /* .. .. .. ARM_PLL_LOCK = 1 */
8492 /* .. .. .. ==> 0XF800010C[0:0] = 0x00000001U */
8493 /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
8494 /* .. .. .. */
8495 EMIT_MASKPOLL(0XF800010C, 0x00000001U),
8496 /* .. .. .. FINISH: CHECK PLL STATUS */
8497 /* .. .. .. START: REMOVE PLL BY PASS */
8498 /* .. .. .. PLL_BYPASS_FORCE = 0 */
8499 /* .. .. .. ==> 0XF8000100[4:4] = 0x00000000U */
8500 /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
8501 /* .. .. .. */
8502 EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U),
8503 /* .. .. .. FINISH: REMOVE PLL BY PASS */
8504 /* .. .. .. SRCSEL = 0x0 */
8505 /* .. .. .. ==> 0XF8000120[5:4] = 0x00000000U */
8506 /* .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
8507 /* .. .. .. DIVISOR = 0x2 */
8508 /* .. .. .. ==> 0XF8000120[13:8] = 0x00000002U */
8509 /* .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U */
8510 /* .. .. .. CPU_6OR4XCLKACT = 0x1 */
8511 /* .. .. .. ==> 0XF8000120[24:24] = 0x00000001U */
8512 /* .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U */
8513 /* .. .. .. CPU_3OR2XCLKACT = 0x1 */
8514 /* .. .. .. ==> 0XF8000120[25:25] = 0x00000001U */
8515 /* .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U */
8516 /* .. .. .. CPU_2XCLKACT = 0x1 */
8517 /* .. .. .. ==> 0XF8000120[26:26] = 0x00000001U */
8518 /* .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U */
8519 /* .. .. .. CPU_1XCLKACT = 0x1 */
8520 /* .. .. .. ==> 0XF8000120[27:27] = 0x00000001U */
8521 /* .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U */
8522 /* .. .. .. CPU_PERI_CLKACT = 0x1 */
8523 /* .. .. .. ==> 0XF8000120[28:28] = 0x00000001U */
8524 /* .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U */
8525 /* .. .. .. */
8526 EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U),
8527 /* .. .. FINISH: ARM PLL INIT */
8528 /* .. .. START: DDR PLL INIT */
8529 /* .. .. PLL_RES = 0xc */
8530 /* .. .. ==> 0XF8000114[7:4] = 0x0000000CU */
8531 /* .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U */
8532 /* .. .. PLL_CP = 0x2 */
8533 /* .. .. ==> 0XF8000114[11:8] = 0x00000002U */
8534 /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */
8535 /* .. .. LOCK_CNT = 0x1db */
8536 /* .. .. ==> 0XF8000114[21:12] = 0x000001DBU */
8537 /* .. .. ==> MASK : 0x003FF000U VAL : 0x001DB000U */
8538 /* .. .. */
8539 EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x001DB2C0U),
8540 /* .. .. .. START: UPDATE FB_DIV */
8541 /* .. .. .. PLL_FDIV = 0x15 */
8542 /* .. .. .. ==> 0XF8000104[18:12] = 0x00000015U */
8543 /* .. .. .. ==> MASK : 0x0007F000U VAL : 0x00015000U */
8544 /* .. .. .. */
8545 EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00015000U),
8546 /* .. .. .. FINISH: UPDATE FB_DIV */
8547 /* .. .. .. START: BY PASS PLL */
8548 /* .. .. .. PLL_BYPASS_FORCE = 1 */
8549 /* .. .. .. ==> 0XF8000104[4:4] = 0x00000001U */
8550 /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U */
8551 /* .. .. .. */
8552 EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U),
8553 /* .. .. .. FINISH: BY PASS PLL */
8554 /* .. .. .. START: ASSERT RESET */
8555 /* .. .. .. PLL_RESET = 1 */
8556 /* .. .. .. ==> 0XF8000104[0:0] = 0x00000001U */
8557 /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
8558 /* .. .. .. */
8559 EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U),
8560 /* .. .. .. FINISH: ASSERT RESET */
8561 /* .. .. .. START: DEASSERT RESET */
8562 /* .. .. .. PLL_RESET = 0 */
8563 /* .. .. .. ==> 0XF8000104[0:0] = 0x00000000U */
8564 /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
8565 /* .. .. .. */
8566 EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U),
8567 /* .. .. .. FINISH: DEASSERT RESET */
8568 /* .. .. .. START: CHECK PLL STATUS */
8569 /* .. .. .. DDR_PLL_LOCK = 1 */
8570 /* .. .. .. ==> 0XF800010C[1:1] = 0x00000001U */
8571 /* .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */
8572 /* .. .. .. */
8573 EMIT_MASKPOLL(0XF800010C, 0x00000002U),
8574 /* .. .. .. FINISH: CHECK PLL STATUS */
8575 /* .. .. .. START: REMOVE PLL BY PASS */
8576 /* .. .. .. PLL_BYPASS_FORCE = 0 */
8577 /* .. .. .. ==> 0XF8000104[4:4] = 0x00000000U */
8578 /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
8579 /* .. .. .. */
8580 EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U),
8581 /* .. .. .. FINISH: REMOVE PLL BY PASS */
8582 /* .. .. .. DDR_3XCLKACT = 0x1 */
8583 /* .. .. .. ==> 0XF8000124[0:0] = 0x00000001U */
8584 /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
8585 /* .. .. .. DDR_2XCLKACT = 0x1 */
8586 /* .. .. .. ==> 0XF8000124[1:1] = 0x00000001U */
8587 /* .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */
8588 /* .. .. .. DDR_3XCLK_DIVISOR = 0x2 */
8589 /* .. .. .. ==> 0XF8000124[25:20] = 0x00000002U */
8590 /* .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U */
8591 /* .. .. .. DDR_2XCLK_DIVISOR = 0x3 */
8592 /* .. .. .. ==> 0XF8000124[31:26] = 0x00000003U */
8593 /* .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U */
8594 /* .. .. .. */
8595 EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U),
8596 /* .. .. FINISH: DDR PLL INIT */
8597 /* .. .. START: IO PLL INIT */
8598 /* .. .. PLL_RES = 0xc */
8599 /* .. .. ==> 0XF8000118[7:4] = 0x0000000CU */
8600 /* .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U */
8601 /* .. .. PLL_CP = 0x2 */
8602 /* .. .. ==> 0XF8000118[11:8] = 0x00000002U */
8603 /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */
8604 /* .. .. LOCK_CNT = 0x1f4 */
8605 /* .. .. ==> 0XF8000118[21:12] = 0x000001F4U */
8606 /* .. .. ==> MASK : 0x003FF000U VAL : 0x001F4000U */
8607 /* .. .. */
8608 EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x001F42C0U),
8609 /* .. .. .. START: UPDATE FB_DIV */
8610 /* .. .. .. PLL_FDIV = 0x14 */
8611 /* .. .. .. ==> 0XF8000108[18:12] = 0x00000014U */
8612 /* .. .. .. ==> MASK : 0x0007F000U VAL : 0x00014000U */
8613 /* .. .. .. */
8614 EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x00014000U),
8615 /* .. .. .. FINISH: UPDATE FB_DIV */
8616 /* .. .. .. START: BY PASS PLL */
8617 /* .. .. .. PLL_BYPASS_FORCE = 1 */
8618 /* .. .. .. ==> 0XF8000108[4:4] = 0x00000001U */
8619 /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U */
8620 /* .. .. .. */
8621 EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U),
8622 /* .. .. .. FINISH: BY PASS PLL */
8623 /* .. .. .. START: ASSERT RESET */
8624 /* .. .. .. PLL_RESET = 1 */
8625 /* .. .. .. ==> 0XF8000108[0:0] = 0x00000001U */
8626 /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
8627 /* .. .. .. */
8628 EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U),
8629 /* .. .. .. FINISH: ASSERT RESET */
8630 /* .. .. .. START: DEASSERT RESET */
8631 /* .. .. .. PLL_RESET = 0 */
8632 /* .. .. .. ==> 0XF8000108[0:0] = 0x00000000U */
8633 /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
8634 /* .. .. .. */
8635 EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U),
8636 /* .. .. .. FINISH: DEASSERT RESET */
8637 /* .. .. .. START: CHECK PLL STATUS */
8638 /* .. .. .. IO_PLL_LOCK = 1 */
8639 /* .. .. .. ==> 0XF800010C[2:2] = 0x00000001U */
8640 /* .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U */
8641 /* .. .. .. */
8642 EMIT_MASKPOLL(0XF800010C, 0x00000004U),
8643 /* .. .. .. FINISH: CHECK PLL STATUS */
8644 /* .. .. .. START: REMOVE PLL BY PASS */
8645 /* .. .. .. PLL_BYPASS_FORCE = 0 */
8646 /* .. .. .. ==> 0XF8000108[4:4] = 0x00000000U */
8647 /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
8648 /* .. .. .. */
8649 EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U),
8650 /* .. .. .. FINISH: REMOVE PLL BY PASS */
8651 /* .. .. FINISH: IO PLL INIT */
8652 /* .. FINISH: PLL SLCR REGISTERS */
8653 /* .. START: LOCK IT BACK */
8654 /* .. LOCK_KEY = 0X767B */
8655 /* .. ==> 0XF8000004[15:0] = 0x0000767BU */
8656 /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */
8657 /* .. */
8658 EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
8659 /* .. FINISH: LOCK IT BACK */
8660 /* FINISH: top */
8661 /* */
8662 EMIT_EXIT(),
8663
8664 /* */
8665};
8666
8667unsigned long ps7_clock_init_data_1_0[] = {
8668 /* START: top */
8669 /* .. START: SLCR SETTINGS */
8670 /* .. UNLOCK_KEY = 0XDF0D */
8671 /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
8672 /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */
8673 /* .. */
8674 EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
8675 /* .. FINISH: SLCR SETTINGS */
8676 /* .. START: CLOCK CONTROL SLCR REGISTERS */
8677 /* .. CLKACT = 0x1 */
8678 /* .. ==> 0XF8000128[0:0] = 0x00000001U */
8679 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
8680 /* .. DIVISOR0 = 0x34 */
8681 /* .. ==> 0XF8000128[13:8] = 0x00000034U */
8682 /* .. ==> MASK : 0x00003F00U VAL : 0x00003400U */
8683 /* .. DIVISOR1 = 0x2 */
8684 /* .. ==> 0XF8000128[25:20] = 0x00000002U */
8685 /* .. ==> MASK : 0x03F00000U VAL : 0x00200000U */
8686 /* .. */
8687 EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00203401U),
8688 /* .. CLKACT = 0x1 */
8689 /* .. ==> 0XF8000138[0:0] = 0x00000001U */
8690 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
8691 /* .. SRCSEL = 0x0 */
8692 /* .. ==> 0XF8000138[4:4] = 0x00000000U */
8693 /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */
8694 /* .. */
8695 EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000001U),
8696 /* .. CLKACT = 0x1 */
8697 /* .. ==> 0XF8000140[0:0] = 0x00000001U */
8698 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
8699 /* .. SRCSEL = 0x0 */
8700 /* .. ==> 0XF8000140[6:4] = 0x00000000U */
8701 /* .. ==> MASK : 0x00000070U VAL : 0x00000000U */
8702 /* .. DIVISOR = 0x8 */
8703 /* .. ==> 0XF8000140[13:8] = 0x00000008U */
8704 /* .. ==> MASK : 0x00003F00U VAL : 0x00000800U */
8705 /* .. DIVISOR1 = 0x1 */
8706 /* .. ==> 0XF8000140[25:20] = 0x00000001U */
8707 /* .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
8708 /* .. */
8709 EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00100801U),
8710 /* .. CLKACT = 0x1 */
8711 /* .. ==> 0XF800014C[0:0] = 0x00000001U */
8712 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
8713 /* .. SRCSEL = 0x0 */
8714 /* .. ==> 0XF800014C[5:4] = 0x00000000U */
8715 /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */
8716 /* .. DIVISOR = 0x5 */
8717 /* .. ==> 0XF800014C[13:8] = 0x00000005U */
8718 /* .. ==> MASK : 0x00003F00U VAL : 0x00000500U */
8719 /* .. */
8720 EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000501U),
8721 /* .. CLKACT0 = 0x1 */
8722 /* .. ==> 0XF8000150[0:0] = 0x00000001U */
8723 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
8724 /* .. CLKACT1 = 0x0 */
8725 /* .. ==> 0XF8000150[1:1] = 0x00000000U */
8726 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
8727 /* .. SRCSEL = 0x0 */
8728 /* .. ==> 0XF8000150[5:4] = 0x00000000U */
8729 /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */
8730 /* .. DIVISOR = 0x14 */
8731 /* .. ==> 0XF8000150[13:8] = 0x00000014U */
8732 /* .. ==> MASK : 0x00003F00U VAL : 0x00001400U */
8733 /* .. */
8734 EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00001401U),
8735 /* .. CLKACT0 = 0x0 */
8736 /* .. ==> 0XF8000154[0:0] = 0x00000000U */
8737 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
8738 /* .. CLKACT1 = 0x1 */
8739 /* .. ==> 0XF8000154[1:1] = 0x00000001U */
8740 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
8741 /* .. SRCSEL = 0x0 */
8742 /* .. ==> 0XF8000154[5:4] = 0x00000000U */
8743 /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */
Michal Simek264065f2016-03-03 13:25:03 +0100[diff] [blame]8744 /* .. DIVISOR = 0xa */
8745 /* .. ==> 0XF8000154[13:8] = 0x0000000AU */
8746 /* .. ==> MASK : 0x00003F00U VAL : 0x00000A00U */
Nathan Rossi4eeed0e2015-11-24 19:34:09 +1000[diff] [blame]8747 /* .. */
Michal Simek264065f2016-03-03 13:25:03 +0100[diff] [blame]8748 EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A02U),
Nathan Rossi4eeed0e2015-11-24 19:34:09 +1000[diff] [blame]8749 /* .. .. START: TRACE CLOCK */
8750 /* .. .. FINISH: TRACE CLOCK */
8751 /* .. .. CLKACT = 0x1 */
8752 /* .. .. ==> 0XF8000168[0:0] = 0x00000001U */
8753 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
8754 /* .. .. SRCSEL = 0x0 */
8755 /* .. .. ==> 0XF8000168[5:4] = 0x00000000U */
8756 /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
8757 /* .. .. DIVISOR = 0x5 */
8758 /* .. .. ==> 0XF8000168[13:8] = 0x00000005U */
8759 /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U */
8760 /* .. .. */
8761 EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000501U),
8762 /* .. .. SRCSEL = 0x0 */
8763 /* .. .. ==> 0XF8000170[5:4] = 0x00000000U */
8764 /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
8765 /* .. .. DIVISOR0 = 0xa */
8766 /* .. .. ==> 0XF8000170[13:8] = 0x0000000AU */
8767 /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U */
8768 /* .. .. DIVISOR1 = 0x1 */
8769 /* .. .. ==> 0XF8000170[25:20] = 0x00000001U */
8770 /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
8771 /* .. .. */
8772 EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00100A00U),
Michal Simek264065f2016-03-03 13:25:03 +0100[diff] [blame]8773 /* .. .. SRCSEL = 0x0 */
8774 /* .. .. ==> 0XF8000180[5:4] = 0x00000000U */
8775 /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
8776 /* .. .. DIVISOR0 = 0x7 */
8777 /* .. .. ==> 0XF8000180[13:8] = 0x00000007U */
8778 /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000700U */
Nathan Rossi4eeed0e2015-11-24 19:34:09 +1000[diff] [blame]8779 /* .. .. DIVISOR1 = 0x1 */
8780 /* .. .. ==> 0XF8000180[25:20] = 0x00000001U */
8781 /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
8782 /* .. .. */
Michal Simek264065f2016-03-03 13:25:03 +0100[diff] [blame]8783 EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100700U),
8784 /* .. .. SRCSEL = 0x0 */
8785 /* .. .. ==> 0XF8000190[5:4] = 0x00000000U */
8786 /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
8787 /* .. .. DIVISOR0 = 0x5 */
8788 /* .. .. ==> 0XF8000190[13:8] = 0x00000005U */
8789 /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U */
8790 /* .. .. DIVISOR1 = 0x1 */
8791 /* .. .. ==> 0XF8000190[25:20] = 0x00000001U */
8792 /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
Nathan Rossi4eeed0e2015-11-24 19:34:09 +1000[diff] [blame]8793 /* .. .. */
Michal Simek264065f2016-03-03 13:25:03 +0100[diff] [blame]8794 EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00100500U),
Nathan Rossi4eeed0e2015-11-24 19:34:09 +1000[diff] [blame]8795 /* .. .. SRCSEL = 0x0 */
8796 /* .. .. ==> 0XF80001A0[5:4] = 0x00000000U */
8797 /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
Michal Simek264065f2016-03-03 13:25:03 +0100[diff] [blame]8798 /* .. .. DIVISOR0 = 0x14 */
8799 /* .. .. ==> 0XF80001A0[13:8] = 0x00000014U */
8800 /* .. .. ==> MASK : 0x00003F00U VAL : 0x00001400U */
Nathan Rossi4eeed0e2015-11-24 19:34:09 +1000[diff] [blame]8801 /* .. .. DIVISOR1 = 0x1 */
8802 /* .. .. ==> 0XF80001A0[25:20] = 0x00000001U */
8803 /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
8804 /* .. .. */
Michal Simek264065f2016-03-03 13:25:03 +0100[diff] [blame]8805 EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00101400U),
Nathan Rossi4eeed0e2015-11-24 19:34:09 +1000[diff] [blame]8806 /* .. .. CLK_621_TRUE = 0x1 */
8807 /* .. .. ==> 0XF80001C4[0:0] = 0x00000001U */
8808 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
8809 /* .. .. */
8810 EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U),
8811 /* .. .. DMA_CPU_2XCLKACT = 0x1 */
8812 /* .. .. ==> 0XF800012C[0:0] = 0x00000001U */
8813 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
8814 /* .. .. USB0_CPU_1XCLKACT = 0x1 */
8815 /* .. .. ==> 0XF800012C[2:2] = 0x00000001U */
8816 /* .. .. ==> MASK : 0x00000004U VAL : 0x00000004U */
8817 /* .. .. USB1_CPU_1XCLKACT = 0x1 */
8818 /* .. .. ==> 0XF800012C[3:3] = 0x00000001U */
8819 /* .. .. ==> MASK : 0x00000008U VAL : 0x00000008U */
8820 /* .. .. GEM0_CPU_1XCLKACT = 0x1 */
8821 /* .. .. ==> 0XF800012C[6:6] = 0x00000001U */
8822 /* .. .. ==> MASK : 0x00000040U VAL : 0x00000040U */
8823 /* .. .. GEM1_CPU_1XCLKACT = 0x0 */
8824 /* .. .. ==> 0XF800012C[7:7] = 0x00000000U */
8825 /* .. .. ==> MASK : 0x00000080U VAL : 0x00000000U */
8826 /* .. .. SDI0_CPU_1XCLKACT = 0x1 */
8827 /* .. .. ==> 0XF800012C[10:10] = 0x00000001U */
8828 /* .. .. ==> MASK : 0x00000400U VAL : 0x00000400U */
8829 /* .. .. SDI1_CPU_1XCLKACT = 0x0 */
8830 /* .. .. ==> 0XF800012C[11:11] = 0x00000000U */
8831 /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */
8832 /* .. .. SPI0_CPU_1XCLKACT = 0x0 */
8833 /* .. .. ==> 0XF800012C[14:14] = 0x00000000U */
8834 /* .. .. ==> MASK : 0x00004000U VAL : 0x00000000U */
8835 /* .. .. SPI1_CPU_1XCLKACT = 0x0 */
8836 /* .. .. ==> 0XF800012C[15:15] = 0x00000000U */
8837 /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */
8838 /* .. .. CAN0_CPU_1XCLKACT = 0x0 */
8839 /* .. .. ==> 0XF800012C[16:16] = 0x00000000U */
8840 /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
8841 /* .. .. CAN1_CPU_1XCLKACT = 0x0 */
8842 /* .. .. ==> 0XF800012C[17:17] = 0x00000000U */
8843 /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
8844 /* .. .. I2C0_CPU_1XCLKACT = 0x1 */
8845 /* .. .. ==> 0XF800012C[18:18] = 0x00000001U */
8846 /* .. .. ==> MASK : 0x00040000U VAL : 0x00040000U */
8847 /* .. .. I2C1_CPU_1XCLKACT = 0x1 */
8848 /* .. .. ==> 0XF800012C[19:19] = 0x00000001U */
8849 /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */
8850 /* .. .. UART0_CPU_1XCLKACT = 0x0 */
8851 /* .. .. ==> 0XF800012C[20:20] = 0x00000000U */
8852 /* .. .. ==> MASK : 0x00100000U VAL : 0x00000000U */
8853 /* .. .. UART1_CPU_1XCLKACT = 0x1 */
8854 /* .. .. ==> 0XF800012C[21:21] = 0x00000001U */
8855 /* .. .. ==> MASK : 0x00200000U VAL : 0x00200000U */
8856 /* .. .. GPIO_CPU_1XCLKACT = 0x1 */
8857 /* .. .. ==> 0XF800012C[22:22] = 0x00000001U */
8858 /* .. .. ==> MASK : 0x00400000U VAL : 0x00400000U */
8859 /* .. .. LQSPI_CPU_1XCLKACT = 0x1 */
8860 /* .. .. ==> 0XF800012C[23:23] = 0x00000001U */
8861 /* .. .. ==> MASK : 0x00800000U VAL : 0x00800000U */
8862 /* .. .. SMC_CPU_1XCLKACT = 0x1 */
8863 /* .. .. ==> 0XF800012C[24:24] = 0x00000001U */
8864 /* .. .. ==> MASK : 0x01000000U VAL : 0x01000000U */
8865 /* .. .. */
8866 EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01EC044DU),
8867 /* .. FINISH: CLOCK CONTROL SLCR REGISTERS */
8868 /* .. START: THIS SHOULD BE BLANK */
8869 /* .. FINISH: THIS SHOULD BE BLANK */
8870 /* .. START: LOCK IT BACK */
8871 /* .. LOCK_KEY = 0X767B */
8872 /* .. ==> 0XF8000004[15:0] = 0x0000767BU */
8873 /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */
8874 /* .. */
8875 EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
8876 /* .. FINISH: LOCK IT BACK */
8877 /* FINISH: top */
8878 /* */
8879 EMIT_EXIT(),
8880
8881 /* */
8882};
8883
8884unsigned long ps7_ddr_init_data_1_0[] = {
8885 /* START: top */
8886 /* .. START: DDR INITIALIZATION */
8887 /* .. .. START: LOCK DDR */
8888 /* .. .. reg_ddrc_soft_rstb = 0 */
8889 /* .. .. ==> 0XF8006000[0:0] = 0x00000000U */
8890 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
8891 /* .. .. reg_ddrc_powerdown_en = 0x0 */
8892 /* .. .. ==> 0XF8006000[1:1] = 0x00000000U */
8893 /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
8894 /* .. .. reg_ddrc_data_bus_width = 0x0 */
8895 /* .. .. ==> 0XF8006000[3:2] = 0x00000000U */
8896 /* .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U */
8897 /* .. .. reg_ddrc_burst8_refresh = 0x0 */
8898 /* .. .. ==> 0XF8006000[6:4] = 0x00000000U */
8899 /* .. .. ==> MASK : 0x00000070U VAL : 0x00000000U */
8900 /* .. .. reg_ddrc_rdwr_idle_gap = 0x1 */
8901 /* .. .. ==> 0XF8006000[13:7] = 0x00000001U */
8902 /* .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U */
8903 /* .. .. reg_ddrc_dis_rd_bypass = 0x0 */
8904 /* .. .. ==> 0XF8006000[14:14] = 0x00000000U */
8905 /* .. .. ==> MASK : 0x00004000U VAL : 0x00000000U */
8906 /* .. .. reg_ddrc_dis_act_bypass = 0x0 */
8907 /* .. .. ==> 0XF8006000[15:15] = 0x00000000U */
8908 /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */
8909 /* .. .. reg_ddrc_dis_auto_refresh = 0x0 */
8910 /* .. .. ==> 0XF8006000[16:16] = 0x00000000U */
8911 /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
8912 /* .. .. */
8913 EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U),
8914 /* .. .. FINISH: LOCK DDR */
8915 /* .. .. reg_ddrc_t_rfc_nom_x32 = 0x7f */
8916 /* .. .. ==> 0XF8006004[11:0] = 0x0000007FU */
8917 /* .. .. ==> MASK : 0x00000FFFU VAL : 0x0000007FU */
8918 /* .. .. reg_ddrc_active_ranks = 0x1 */
8919 /* .. .. ==> 0XF8006004[13:12] = 0x00000001U */
8920 /* .. .. ==> MASK : 0x00003000U VAL : 0x00001000U */
8921 /* .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 */
8922 /* .. .. ==> 0XF8006004[18:14] = 0x00000000U */
8923 /* .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U */
8924 /* .. .. reg_ddrc_wr_odt_block = 0x1 */
8925 /* .. .. ==> 0XF8006004[20:19] = 0x00000001U */
8926 /* .. .. ==> MASK : 0x00180000U VAL : 0x00080000U */
8927 /* .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0 */
8928 /* .. .. ==> 0XF8006004[21:21] = 0x00000000U */
8929 /* .. .. ==> MASK : 0x00200000U VAL : 0x00000000U */
8930 /* .. .. reg_ddrc_addrmap_cs_bit1 = 0x0 */
8931 /* .. .. ==> 0XF8006004[26:22] = 0x00000000U */
8932 /* .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U */
8933 /* .. .. reg_ddrc_addrmap_open_bank = 0x0 */
8934 /* .. .. ==> 0XF8006004[27:27] = 0x00000000U */
8935 /* .. .. ==> MASK : 0x08000000U VAL : 0x00000000U */
8936 /* .. .. reg_ddrc_addrmap_4bank_ram = 0x0 */
8937 /* .. .. ==> 0XF8006004[28:28] = 0x00000000U */
8938 /* .. .. ==> MASK : 0x10000000U VAL : 0x00000000U */
8939 /* .. .. */
8940 EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU, 0x0008107FU),
8941 /* .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf */
8942 /* .. .. ==> 0XF8006008[10:0] = 0x0000000FU */
8943 /* .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU */
8944 /* .. .. reg_ddrc_hpr_max_starve_x32 = 0xf */
8945 /* .. .. ==> 0XF8006008[21:11] = 0x0000000FU */
8946 /* .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U */
8947 /* .. .. reg_ddrc_hpr_xact_run_length = 0xf */
8948 /* .. .. ==> 0XF8006008[25:22] = 0x0000000FU */
8949 /* .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U */
8950 /* .. .. */
8951 EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU),
8952 /* .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 */
8953 /* .. .. ==> 0XF800600C[10:0] = 0x00000001U */
8954 /* .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U */
8955 /* .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 */
8956 /* .. .. ==> 0XF800600C[21:11] = 0x00000002U */
8957 /* .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U */
8958 /* .. .. reg_ddrc_lpr_xact_run_length = 0x8 */
8959 /* .. .. ==> 0XF800600C[25:22] = 0x00000008U */
8960 /* .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U */
8961 /* .. .. */
8962 EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U),
8963 /* .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 */
8964 /* .. .. ==> 0XF8006010[10:0] = 0x00000001U */
8965 /* .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U */
8966 /* .. .. reg_ddrc_w_xact_run_length = 0x8 */
8967 /* .. .. ==> 0XF8006010[14:11] = 0x00000008U */
8968 /* .. .. ==> MASK : 0x00007800U VAL : 0x00004000U */
8969 /* .. .. reg_ddrc_w_max_starve_x32 = 0x2 */
8970 /* .. .. ==> 0XF8006010[25:15] = 0x00000002U */
8971 /* .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U */
8972 /* .. .. */
8973 EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U),
8974 /* .. .. reg_ddrc_t_rc = 0x1a */
8975 /* .. .. ==> 0XF8006014[5:0] = 0x0000001AU */
8976 /* .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU */
8977 /* .. .. reg_ddrc_t_rfc_min = 0x54 */
8978 /* .. .. ==> 0XF8006014[13:6] = 0x00000054U */
8979 /* .. .. ==> MASK : 0x00003FC0U VAL : 0x00001500U */
8980 /* .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 */
8981 /* .. .. ==> 0XF8006014[20:14] = 0x00000010U */
8982 /* .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U */
8983 /* .. .. */
8984 EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x0004151AU),
8985 /* .. .. reg_ddrc_wr2pre = 0x12 */
8986 /* .. .. ==> 0XF8006018[4:0] = 0x00000012U */
8987 /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U */
8988 /* .. .. reg_ddrc_powerdown_to_x32 = 0x6 */
8989 /* .. .. ==> 0XF8006018[9:5] = 0x00000006U */
8990 /* .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U */
8991 /* .. .. reg_ddrc_t_faw = 0x15 */
8992 /* .. .. ==> 0XF8006018[15:10] = 0x00000015U */
8993 /* .. .. ==> MASK : 0x0000FC00U VAL : 0x00005400U */
8994 /* .. .. reg_ddrc_t_ras_max = 0x23 */
8995 /* .. .. ==> 0XF8006018[21:16] = 0x00000023U */
8996 /* .. .. ==> MASK : 0x003F0000U VAL : 0x00230000U */
8997 /* .. .. reg_ddrc_t_ras_min = 0x13 */
8998 /* .. .. ==> 0XF8006018[26:22] = 0x00000013U */
8999 /* .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U */
9000 /* .. .. reg_ddrc_t_cke = 0x4 */
9001 /* .. .. ==> 0XF8006018[31:28] = 0x00000004U */
9002 /* .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U */
9003 /* .. .. */
9004 EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x44E354D2U),
9005 /* .. .. reg_ddrc_write_latency = 0x5 */
9006 /* .. .. ==> 0XF800601C[4:0] = 0x00000005U */
9007 /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U */
9008 /* .. .. reg_ddrc_rd2wr = 0x7 */
9009 /* .. .. ==> 0XF800601C[9:5] = 0x00000007U */
9010 /* .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U */
9011 /* .. .. reg_ddrc_wr2rd = 0xe */
9012 /* .. .. ==> 0XF800601C[14:10] = 0x0000000EU */
9013 /* .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U */
9014 /* .. .. reg_ddrc_t_xp = 0x4 */
9015 /* .. .. ==> 0XF800601C[19:15] = 0x00000004U */
9016 /* .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U */
9017 /* .. .. reg_ddrc_pad_pd = 0x0 */
9018 /* .. .. ==> 0XF800601C[22:20] = 0x00000000U */
9019 /* .. .. ==> MASK : 0x00700000U VAL : 0x00000000U */
9020 /* .. .. reg_ddrc_rd2pre = 0x4 */
9021 /* .. .. ==> 0XF800601C[27:23] = 0x00000004U */
9022 /* .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U */
9023 /* .. .. reg_ddrc_t_rcd = 0x7 */
9024 /* .. .. ==> 0XF800601C[31:28] = 0x00000007U */
9025 /* .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U */
9026 /* .. .. */
9027 EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0x720238E5U),
9028 /* .. .. reg_ddrc_t_ccd = 0x4 */
9029 /* .. .. ==> 0XF8006020[4:2] = 0x00000004U */
9030 /* .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U */
9031 /* .. .. reg_ddrc_t_rrd = 0x6 */
9032 /* .. .. ==> 0XF8006020[7:5] = 0x00000006U */
9033 /* .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U */
9034 /* .. .. reg_ddrc_refresh_margin = 0x2 */
9035 /* .. .. ==> 0XF8006020[11:8] = 0x00000002U */
9036 /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */
9037 /* .. .. reg_ddrc_t_rp = 0x7 */
9038 /* .. .. ==> 0XF8006020[15:12] = 0x00000007U */
9039 /* .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U */
9040 /* .. .. reg_ddrc_refresh_to_x32 = 0x8 */
9041 /* .. .. ==> 0XF8006020[20:16] = 0x00000008U */
9042 /* .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U */
9043 /* .. .. reg_ddrc_sdram = 0x1 */
9044 /* .. .. ==> 0XF8006020[21:21] = 0x00000001U */
9045 /* .. .. ==> MASK : 0x00200000U VAL : 0x00200000U */
9046 /* .. .. reg_ddrc_mobile = 0x0 */
9047 /* .. .. ==> 0XF8006020[22:22] = 0x00000000U */
9048 /* .. .. ==> MASK : 0x00400000U VAL : 0x00000000U */
9049 /* .. .. reg_ddrc_clock_stop_en = 0x0 */
9050 /* .. .. ==> 0XF8006020[23:23] = 0x00000000U */
9051 /* .. .. ==> MASK : 0x00800000U VAL : 0x00000000U */
9052 /* .. .. reg_ddrc_read_latency = 0x7 */
9053 /* .. .. ==> 0XF8006020[28:24] = 0x00000007U */
9054 /* .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U */
9055 /* .. .. reg_phy_mode_ddr1_ddr2 = 0x1 */
9056 /* .. .. ==> 0XF8006020[29:29] = 0x00000001U */
9057 /* .. .. ==> MASK : 0x20000000U VAL : 0x20000000U */
9058 /* .. .. reg_ddrc_dis_pad_pd = 0x0 */
9059 /* .. .. ==> 0XF8006020[30:30] = 0x00000000U */
9060 /* .. .. ==> MASK : 0x40000000U VAL : 0x00000000U */
9061 /* .. .. reg_ddrc_loopback = 0x0 */
9062 /* .. .. ==> 0XF8006020[31:31] = 0x00000000U */
9063 /* .. .. ==> MASK : 0x80000000U VAL : 0x00000000U */
9064 /* .. .. */
9065 EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU, 0x272872D0U),
9066 /* .. .. reg_ddrc_en_2t_timing_mode = 0x0 */
9067 /* .. .. ==> 0XF8006024[0:0] = 0x00000000U */
9068 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
9069 /* .. .. reg_ddrc_prefer_write = 0x0 */
9070 /* .. .. ==> 0XF8006024[1:1] = 0x00000000U */
9071 /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
9072 /* .. .. reg_ddrc_max_rank_rd = 0xf */
9073 /* .. .. ==> 0XF8006024[5:2] = 0x0000000FU */
9074 /* .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU */
9075 /* .. .. reg_ddrc_mr_wr = 0x0 */
9076 /* .. .. ==> 0XF8006024[6:6] = 0x00000000U */
9077 /* .. .. ==> MASK : 0x00000040U VAL : 0x00000000U */
9078 /* .. .. reg_ddrc_mr_addr = 0x0 */
9079 /* .. .. ==> 0XF8006024[8:7] = 0x00000000U */
9080 /* .. .. ==> MASK : 0x00000180U VAL : 0x00000000U */
9081 /* .. .. reg_ddrc_mr_data = 0x0 */
9082 /* .. .. ==> 0XF8006024[24:9] = 0x00000000U */
9083 /* .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U */
9084 /* .. .. ddrc_reg_mr_wr_busy = 0x0 */
9085 /* .. .. ==> 0XF8006024[25:25] = 0x00000000U */
9086 /* .. .. ==> MASK : 0x02000000U VAL : 0x00000000U */
9087 /* .. .. reg_ddrc_mr_type = 0x0 */
9088 /* .. .. ==> 0XF8006024[26:26] = 0x00000000U */
9089 /* .. .. ==> MASK : 0x04000000U VAL : 0x00000000U */
9090 /* .. .. reg_ddrc_mr_rdata_valid = 0x0 */
9091 /* .. .. ==> 0XF8006024[27:27] = 0x00000000U */
9092 /* .. .. ==> MASK : 0x08000000U VAL : 0x00000000U */
9093 /* .. .. */
9094 EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU, 0x0000003CU),
9095 /* .. .. reg_ddrc_final_wait_x32 = 0x7 */
9096 /* .. .. ==> 0XF8006028[6:0] = 0x00000007U */
9097 /* .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U */
9098 /* .. .. reg_ddrc_pre_ocd_x32 = 0x0 */
9099 /* .. .. ==> 0XF8006028[10:7] = 0x00000000U */
9100 /* .. .. ==> MASK : 0x00000780U VAL : 0x00000000U */
9101 /* .. .. reg_ddrc_t_mrd = 0x4 */
9102 /* .. .. ==> 0XF8006028[13:11] = 0x00000004U */
9103 /* .. .. ==> MASK : 0x00003800U VAL : 0x00002000U */
9104 /* .. .. */
9105 EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U),
9106 /* .. .. reg_ddrc_emr2 = 0x8 */
9107 /* .. .. ==> 0XF800602C[15:0] = 0x00000008U */
9108 /* .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U */
9109 /* .. .. reg_ddrc_emr3 = 0x0 */
9110 /* .. .. ==> 0XF800602C[31:16] = 0x00000000U */
9111 /* .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U */
9112 /* .. .. */
9113 EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000008U),
9114 /* .. .. reg_ddrc_mr = 0x930 */
9115 /* .. .. ==> 0XF8006030[15:0] = 0x00000930U */
9116 /* .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U */
9117 /* .. .. reg_ddrc_emr = 0x4 */
9118 /* .. .. ==> 0XF8006030[31:16] = 0x00000004U */
9119 /* .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U */
9120 /* .. .. */
9121 EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040930U),
9122 /* .. .. reg_ddrc_burst_rdwr = 0x4 */
9123 /* .. .. ==> 0XF8006034[3:0] = 0x00000004U */
9124 /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U */
Michal Simek264065f2016-03-03 13:25:03 +0100[diff] [blame]9125 /* .. .. reg_ddrc_pre_cke_x1024 = 0x167 */
9126 /* .. .. ==> 0XF8006034[13:4] = 0x00000167U */
9127 /* .. .. ==> MASK : 0x00003FF0U VAL : 0x00001670U */
Nathan Rossi4eeed0e2015-11-24 19:34:09 +1000[diff] [blame]9128 /* .. .. reg_ddrc_post_cke_x1024 = 0x1 */
9129 /* .. .. ==> 0XF8006034[25:16] = 0x00000001U */
9130 /* .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U */
9131 /* .. .. reg_ddrc_burstchop = 0x0 */
9132 /* .. .. ==> 0XF8006034[28:28] = 0x00000000U */
9133 /* .. .. ==> MASK : 0x10000000U VAL : 0x00000000U */
9134 /* .. .. */
Michal Simek264065f2016-03-03 13:25:03 +0100[diff] [blame]9135 EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x00011674U),
Nathan Rossi4eeed0e2015-11-24 19:34:09 +1000[diff] [blame]9136 /* .. .. reg_ddrc_force_low_pri_n = 0x0 */
9137 /* .. .. ==> 0XF8006038[0:0] = 0x00000000U */
9138 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
9139 /* .. .. reg_ddrc_dis_dq = 0x0 */
9140 /* .. .. ==> 0XF8006038[1:1] = 0x00000000U */
9141 /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
9142 /* .. .. reg_phy_debug_mode = 0x0 */
9143 /* .. .. ==> 0XF8006038[6:6] = 0x00000000U */
9144 /* .. .. ==> MASK : 0x00000040U VAL : 0x00000000U */
9145 /* .. .. reg_phy_wr_level_start = 0x0 */
9146 /* .. .. ==> 0XF8006038[7:7] = 0x00000000U */
9147 /* .. .. ==> MASK : 0x00000080U VAL : 0x00000000U */
9148 /* .. .. reg_phy_rd_level_start = 0x0 */
9149 /* .. .. ==> 0XF8006038[8:8] = 0x00000000U */
9150 /* .. .. ==> MASK : 0x00000100U VAL : 0x00000000U */
9151 /* .. .. reg_phy_dq0_wait_t = 0x0 */
9152 /* .. .. ==> 0XF8006038[12:9] = 0x00000000U */
9153 /* .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U */
9154 /* .. .. */
9155 EMIT_MASKWRITE(0XF8006038, 0x00001FC3U, 0x00000000U),
9156 /* .. .. reg_ddrc_addrmap_bank_b0 = 0x7 */
9157 /* .. .. ==> 0XF800603C[3:0] = 0x00000007U */
9158 /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U */
9159 /* .. .. reg_ddrc_addrmap_bank_b1 = 0x7 */
9160 /* .. .. ==> 0XF800603C[7:4] = 0x00000007U */
9161 /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U */
9162 /* .. .. reg_ddrc_addrmap_bank_b2 = 0x7 */
9163 /* .. .. ==> 0XF800603C[11:8] = 0x00000007U */
9164 /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U */
9165 /* .. .. reg_ddrc_addrmap_col_b5 = 0x0 */
9166 /* .. .. ==> 0XF800603C[15:12] = 0x00000000U */
9167 /* .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U */
9168 /* .. .. reg_ddrc_addrmap_col_b6 = 0x0 */
9169 /* .. .. ==> 0XF800603C[19:16] = 0x00000000U */
9170 /* .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U */
9171 /* .. .. */
9172 EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U),
9173 /* .. .. reg_ddrc_addrmap_col_b2 = 0x0 */
9174 /* .. .. ==> 0XF8006040[3:0] = 0x00000000U */
9175 /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U */
9176 /* .. .. reg_ddrc_addrmap_col_b3 = 0x0 */
9177 /* .. .. ==> 0XF8006040[7:4] = 0x00000000U */
9178 /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */
9179 /* .. .. reg_ddrc_addrmap_col_b4 = 0x0 */
9180 /* .. .. ==> 0XF8006040[11:8] = 0x00000000U */
9181 /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U */
9182 /* .. .. reg_ddrc_addrmap_col_b7 = 0x0 */
9183 /* .. .. ==> 0XF8006040[15:12] = 0x00000000U */
9184 /* .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U */
9185 /* .. .. reg_ddrc_addrmap_col_b8 = 0x0 */
9186 /* .. .. ==> 0XF8006040[19:16] = 0x00000000U */
9187 /* .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U */
9188 /* .. .. reg_ddrc_addrmap_col_b9 = 0xf */
9189 /* .. .. ==> 0XF8006040[23:20] = 0x0000000FU */
9190 /* .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U */
9191 /* .. .. reg_ddrc_addrmap_col_b10 = 0xf */
9192 /* .. .. ==> 0XF8006040[27:24] = 0x0000000FU */
9193 /* .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U */
9194 /* .. .. reg_ddrc_addrmap_col_b11 = 0xf */
9195 /* .. .. ==> 0XF8006040[31:28] = 0x0000000FU */
9196 /* .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U */
9197 /* .. .. */
9198 EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U),
9199 /* .. .. reg_ddrc_addrmap_row_b0 = 0x6 */
9200 /* .. .. ==> 0XF8006044[3:0] = 0x00000006U */
9201 /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U */
9202 /* .. .. reg_ddrc_addrmap_row_b1 = 0x6 */
9203 /* .. .. ==> 0XF8006044[7:4] = 0x00000006U */
9204 /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U */
9205 /* .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 */
9206 /* .. .. ==> 0XF8006044[11:8] = 0x00000006U */
9207 /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U */
9208 /* .. .. reg_ddrc_addrmap_row_b12 = 0x6 */
9209 /* .. .. ==> 0XF8006044[15:12] = 0x00000006U */
9210 /* .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U */
9211 /* .. .. reg_ddrc_addrmap_row_b13 = 0x6 */
9212 /* .. .. ==> 0XF8006044[19:16] = 0x00000006U */
9213 /* .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U */
9214 /* .. .. reg_ddrc_addrmap_row_b14 = 0xf */
9215 /* .. .. ==> 0XF8006044[23:20] = 0x0000000FU */
9216 /* .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U */
9217 /* .. .. reg_ddrc_addrmap_row_b15 = 0xf */
9218 /* .. .. ==> 0XF8006044[27:24] = 0x0000000FU */
9219 /* .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U */
9220 /* .. .. */
9221 EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0FF66666U),
9222 /* .. .. reg_ddrc_rank0_rd_odt = 0x0 */
9223 /* .. .. ==> 0XF8006048[2:0] = 0x00000000U */
9224 /* .. .. ==> MASK : 0x00000007U VAL : 0x00000000U */
9225 /* .. .. reg_ddrc_rank0_wr_odt = 0x1 */
9226 /* .. .. ==> 0XF8006048[5:3] = 0x00000001U */
9227 /* .. .. ==> MASK : 0x00000038U VAL : 0x00000008U */
9228 /* .. .. reg_ddrc_rank1_rd_odt = 0x1 */
9229 /* .. .. ==> 0XF8006048[8:6] = 0x00000001U */
9230 /* .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U */
9231 /* .. .. reg_ddrc_rank1_wr_odt = 0x1 */
9232 /* .. .. ==> 0XF8006048[11:9] = 0x00000001U */
9233 /* .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
9234 /* .. .. reg_phy_rd_local_odt = 0x0 */
9235 /* .. .. ==> 0XF8006048[13:12] = 0x00000000U */
9236 /* .. .. ==> MASK : 0x00003000U VAL : 0x00000000U */
9237 /* .. .. reg_phy_wr_local_odt = 0x3 */
9238 /* .. .. ==> 0XF8006048[15:14] = 0x00000003U */
9239 /* .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U */
9240 /* .. .. reg_phy_idle_local_odt = 0x3 */
9241 /* .. .. ==> 0XF8006048[17:16] = 0x00000003U */
9242 /* .. .. ==> MASK : 0x00030000U VAL : 0x00030000U */
9243 /* .. .. reg_ddrc_rank2_rd_odt = 0x0 */
9244 /* .. .. ==> 0XF8006048[20:18] = 0x00000000U */
9245 /* .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U */
9246 /* .. .. reg_ddrc_rank2_wr_odt = 0x0 */
9247 /* .. .. ==> 0XF8006048[23:21] = 0x00000000U */
9248 /* .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U */
9249 /* .. .. reg_ddrc_rank3_rd_odt = 0x0 */
9250 /* .. .. ==> 0XF8006048[26:24] = 0x00000000U */
9251 /* .. .. ==> MASK : 0x07000000U VAL : 0x00000000U */
9252 /* .. .. reg_ddrc_rank3_wr_odt = 0x0 */
9253 /* .. .. ==> 0XF8006048[29:27] = 0x00000000U */
9254 /* .. .. ==> MASK : 0x38000000U VAL : 0x00000000U */
9255 /* .. .. */
9256 EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU, 0x0003C248U),
9257 /* .. .. reg_phy_rd_cmd_to_data = 0x0 */
9258 /* .. .. ==> 0XF8006050[3:0] = 0x00000000U */
9259 /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U */
9260 /* .. .. reg_phy_wr_cmd_to_data = 0x0 */
9261 /* .. .. ==> 0XF8006050[7:4] = 0x00000000U */
9262 /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */
9263 /* .. .. reg_phy_rdc_we_to_re_delay = 0x8 */
9264 /* .. .. ==> 0XF8006050[11:8] = 0x00000008U */
9265 /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U */
9266 /* .. .. reg_phy_rdc_fifo_rst_disable = 0x0 */
9267 /* .. .. ==> 0XF8006050[15:15] = 0x00000000U */
9268 /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */
9269 /* .. .. reg_phy_use_fixed_re = 0x1 */
9270 /* .. .. ==> 0XF8006050[16:16] = 0x00000001U */
9271 /* .. .. ==> MASK : 0x00010000U VAL : 0x00010000U */
9272 /* .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 */
9273 /* .. .. ==> 0XF8006050[17:17] = 0x00000000U */
9274 /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
9275 /* .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 */
9276 /* .. .. ==> 0XF8006050[18:18] = 0x00000000U */
9277 /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
9278 /* .. .. reg_phy_clk_stall_level = 0x0 */
9279 /* .. .. ==> 0XF8006050[19:19] = 0x00000000U */
9280 /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */
9281 /* .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 */
9282 /* .. .. ==> 0XF8006050[27:24] = 0x00000007U */
9283 /* .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U */
9284 /* .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 */
9285 /* .. .. ==> 0XF8006050[31:28] = 0x00000007U */
9286 /* .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U */
9287 /* .. .. */
9288 EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U),
9289 /* .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1 */
9290 /* .. .. ==> 0XF8006058[7:0] = 0x00000001U */
9291 /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U */
9292 /* .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1 */
9293 /* .. .. ==> 0XF8006058[15:8] = 0x00000001U */
9294 /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U */
9295 /* .. .. reg_ddrc_dis_dll_calib = 0x0 */
9296 /* .. .. ==> 0XF8006058[16:16] = 0x00000000U */
9297 /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
9298 /* .. .. */
9299 EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU, 0x00000101U),
9300 /* .. .. reg_ddrc_rd_odt_delay = 0x3 */
9301 /* .. .. ==> 0XF800605C[3:0] = 0x00000003U */
9302 /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U */
9303 /* .. .. reg_ddrc_wr_odt_delay = 0x0 */
9304 /* .. .. ==> 0XF800605C[7:4] = 0x00000000U */
9305 /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */
9306 /* .. .. reg_ddrc_rd_odt_hold = 0x0 */
9307 /* .. .. ==> 0XF800605C[11:8] = 0x00000000U */
9308 /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U */
9309 /* .. .. reg_ddrc_wr_odt_hold = 0x5 */
9310 /* .. .. ==> 0XF800605C[15:12] = 0x00000005U */
9311 /* .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U */
9312 /* .. .. */
9313 EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U),
9314 /* .. .. reg_ddrc_pageclose = 0x0 */
9315 /* .. .. ==> 0XF8006060[0:0] = 0x00000000U */
9316 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
9317 /* .. .. reg_ddrc_lpr_num_entries = 0x1f */
9318 /* .. .. ==> 0XF8006060[6:1] = 0x0000001FU */
9319 /* .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU */
9320 /* .. .. reg_ddrc_auto_pre_en = 0x0 */
9321 /* .. .. ==> 0XF8006060[7:7] = 0x00000000U */
9322 /* .. .. ==> MASK : 0x00000080U VAL : 0x00000000U */
9323 /* .. .. reg_ddrc_refresh_update_level = 0x0 */
9324 /* .. .. ==> 0XF8006060[8:8] = 0x00000000U */
9325 /* .. .. ==> MASK : 0x00000100U VAL : 0x00000000U */
9326 /* .. .. reg_ddrc_dis_wc = 0x0 */
9327 /* .. .. ==> 0XF8006060[9:9] = 0x00000000U */
9328 /* .. .. ==> MASK : 0x00000200U VAL : 0x00000000U */
9329 /* .. .. reg_ddrc_dis_collision_page_opt = 0x0 */
9330 /* .. .. ==> 0XF8006060[10:10] = 0x00000000U */
9331 /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
9332 /* .. .. reg_ddrc_selfref_en = 0x0 */
9333 /* .. .. ==> 0XF8006060[12:12] = 0x00000000U */
9334 /* .. .. ==> MASK : 0x00001000U VAL : 0x00000000U */
9335 /* .. .. */
9336 EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU),
9337 /* .. .. reg_ddrc_go2critical_hysteresis = 0x0 */
9338 /* .. .. ==> 0XF8006064[12:5] = 0x00000000U */
9339 /* .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U */
9340 /* .. .. reg_arb_go2critical_en = 0x1 */
9341 /* .. .. ==> 0XF8006064[17:17] = 0x00000001U */
9342 /* .. .. ==> MASK : 0x00020000U VAL : 0x00020000U */
9343 /* .. .. */
9344 EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U),
9345 /* .. .. reg_ddrc_wrlvl_ww = 0x41 */
9346 /* .. .. ==> 0XF8006068[7:0] = 0x00000041U */
9347 /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U */
9348 /* .. .. reg_ddrc_rdlvl_rr = 0x41 */
9349 /* .. .. ==> 0XF8006068[15:8] = 0x00000041U */
9350 /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U */
9351 /* .. .. reg_ddrc_dfi_t_wlmrd = 0x28 */
9352 /* .. .. ==> 0XF8006068[25:16] = 0x00000028U */
9353 /* .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U */
9354 /* .. .. */
9355 EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284141U),
9356 /* .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 */
9357 /* .. .. ==> 0XF800606C[7:0] = 0x00000010U */
9358 /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U */
9359 /* .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 */
9360 /* .. .. ==> 0XF800606C[15:8] = 0x00000016U */
9361 /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U */
9362 /* .. .. */
9363 EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U),
9364 /* .. .. refresh_timer0_start_value_x32 = 0x0 */
9365 /* .. .. ==> 0XF80060A0[11:0] = 0x00000000U */
9366 /* .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U */
9367 /* .. .. refresh_timer1_start_value_x32 = 0x8 */
9368 /* .. .. ==> 0XF80060A0[23:12] = 0x00000008U */
9369 /* .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U */
9370 /* .. .. */
9371 EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU, 0x00008000U),
9372 /* .. .. reg_ddrc_dis_auto_zq = 0x0 */
9373 /* .. .. ==> 0XF80060A4[0:0] = 0x00000000U */
9374 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
9375 /* .. .. reg_ddrc_ddr3 = 0x1 */
9376 /* .. .. ==> 0XF80060A4[1:1] = 0x00000001U */
9377 /* .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */
9378 /* .. .. reg_ddrc_t_mod = 0x200 */
9379 /* .. .. ==> 0XF80060A4[11:2] = 0x00000200U */
9380 /* .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U */
9381 /* .. .. reg_ddrc_t_zq_long_nop = 0x200 */
9382 /* .. .. ==> 0XF80060A4[21:12] = 0x00000200U */
9383 /* .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U */
9384 /* .. .. reg_ddrc_t_zq_short_nop = 0x40 */
9385 /* .. .. ==> 0XF80060A4[31:22] = 0x00000040U */
9386 /* .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U */
9387 /* .. .. */
9388 EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U),
9389 /* .. .. t_zq_short_interval_x1024 = 0xc845 */
9390 /* .. .. ==> 0XF80060A8[19:0] = 0x0000C845U */
9391 /* .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000C845U */
9392 /* .. .. dram_rstn_x1024 = 0x67 */
9393 /* .. .. ==> 0XF80060A8[27:20] = 0x00000067U */
9394 /* .. .. ==> MASK : 0x0FF00000U VAL : 0x06700000U */
9395 /* .. .. */
9396 EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0670C845U),
9397 /* .. .. deeppowerdown_en = 0x0 */
9398 /* .. .. ==> 0XF80060AC[0:0] = 0x00000000U */
9399 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
9400 /* .. .. deeppowerdown_to_x1024 = 0xff */
9401 /* .. .. ==> 0XF80060AC[8:1] = 0x000000FFU */
9402 /* .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU */
9403 /* .. .. */
9404 EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU),
9405 /* .. .. dfi_wrlvl_max_x1024 = 0xfff */
9406 /* .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU */
9407 /* .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU */
9408 /* .. .. dfi_rdlvl_max_x1024 = 0xfff */
9409 /* .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU */
9410 /* .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U */
9411 /* .. .. ddrc_reg_twrlvl_max_error = 0x0 */
9412 /* .. .. ==> 0XF80060B0[24:24] = 0x00000000U */
9413 /* .. .. ==> MASK : 0x01000000U VAL : 0x00000000U */
9414 /* .. .. ddrc_reg_trdlvl_max_error = 0x0 */
9415 /* .. .. ==> 0XF80060B0[25:25] = 0x00000000U */
9416 /* .. .. ==> MASK : 0x02000000U VAL : 0x00000000U */
9417 /* .. .. reg_ddrc_dfi_wr_level_en = 0x1 */
9418 /* .. .. ==> 0XF80060B0[26:26] = 0x00000001U */
9419 /* .. .. ==> MASK : 0x04000000U VAL : 0x04000000U */
9420 /* .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 */
9421 /* .. .. ==> 0XF80060B0[27:27] = 0x00000001U */
9422 /* .. .. ==> MASK : 0x08000000U VAL : 0x08000000U */
9423 /* .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 */
9424 /* .. .. ==> 0XF80060B0[28:28] = 0x00000001U */
9425 /* .. .. ==> MASK : 0x10000000U VAL : 0x10000000U */
9426 /* .. .. */
9427 EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
9428 /* .. .. reg_ddrc_2t_delay = 0x0 */
9429 /* .. .. ==> 0XF80060B4[8:0] = 0x00000000U */
9430 /* .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U */
9431 /* .. .. reg_ddrc_skip_ocd = 0x1 */
9432 /* .. .. ==> 0XF80060B4[9:9] = 0x00000001U */
9433 /* .. .. ==> MASK : 0x00000200U VAL : 0x00000200U */
9434 /* .. .. reg_ddrc_dis_pre_bypass = 0x0 */
9435 /* .. .. ==> 0XF80060B4[10:10] = 0x00000000U */
9436 /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
9437 /* .. .. */
9438 EMIT_MASKWRITE(0XF80060B4, 0x000007FFU, 0x00000200U),
9439 /* .. .. reg_ddrc_dfi_t_rddata_en = 0x6 */
9440 /* .. .. ==> 0XF80060B8[4:0] = 0x00000006U */
9441 /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U */
9442 /* .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 */
9443 /* .. .. ==> 0XF80060B8[14:5] = 0x00000003U */
9444 /* .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U */
9445 /* .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 */
9446 /* .. .. ==> 0XF80060B8[24:15] = 0x00000040U */
9447 /* .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U */
9448 /* .. .. */
9449 EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x00200066U),
9450 /* .. .. START: RESET ECC ERROR */
9451 /* .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 */
9452 /* .. .. ==> 0XF80060C4[0:0] = 0x00000001U */
9453 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
9454 /* .. .. Clear_Correctable_DRAM_ECC_error = 1 */
9455 /* .. .. ==> 0XF80060C4[1:1] = 0x00000001U */
9456 /* .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */
9457 /* .. .. */
9458 EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000003U),
9459 /* .. .. FINISH: RESET ECC ERROR */
9460 /* .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 */
9461 /* .. .. ==> 0XF80060C4[0:0] = 0x00000000U */
9462 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
9463 /* .. .. Clear_Correctable_DRAM_ECC_error = 0x0 */
9464 /* .. .. ==> 0XF80060C4[1:1] = 0x00000000U */
9465 /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
9466 /* .. .. */
9467 EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U),
9468 /* .. .. CORR_ECC_LOG_VALID = 0x0 */
9469 /* .. .. ==> 0XF80060C8[0:0] = 0x00000000U */
9470 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
9471 /* .. .. ECC_CORRECTED_BIT_NUM = 0x0 */
9472 /* .. .. ==> 0XF80060C8[7:1] = 0x00000000U */
9473 /* .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U */
9474 /* .. .. */
9475 EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U),
9476 /* .. .. UNCORR_ECC_LOG_VALID = 0x0 */
9477 /* .. .. ==> 0XF80060DC[0:0] = 0x00000000U */
9478 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
9479 /* .. .. */
9480 EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U),
9481 /* .. .. STAT_NUM_CORR_ERR = 0x0 */
9482 /* .. .. ==> 0XF80060F0[15:8] = 0x00000000U */
9483 /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U */
9484 /* .. .. STAT_NUM_UNCORR_ERR = 0x0 */
9485 /* .. .. ==> 0XF80060F0[7:0] = 0x00000000U */
9486 /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U */
9487 /* .. .. */
9488 EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U),
9489 /* .. .. reg_ddrc_ecc_mode = 0x0 */
9490 /* .. .. ==> 0XF80060F4[2:0] = 0x00000000U */
9491 /* .. .. ==> MASK : 0x00000007U VAL : 0x00000000U */
9492 /* .. .. reg_ddrc_dis_scrub = 0x1 */
9493 /* .. .. ==> 0XF80060F4[3:3] = 0x00000001U */
9494 /* .. .. ==> MASK : 0x00000008U VAL : 0x00000008U */
9495 /* .. .. */
9496 EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U),
9497 /* .. .. reg_phy_dif_on = 0x0 */
9498 /* .. .. ==> 0XF8006114[3:0] = 0x00000000U */
9499 /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U */
9500 /* .. .. reg_phy_dif_off = 0x0 */
9501 /* .. .. ==> 0XF8006114[7:4] = 0x00000000U */
9502 /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */
9503 /* .. .. */
9504 EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U),
9505 /* .. .. reg_phy_data_slice_in_use = 0x1 */
9506 /* .. .. ==> 0XF8006118[0:0] = 0x00000001U */
9507 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
9508 /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
9509 /* .. .. ==> 0XF8006118[1:1] = 0x00000000U */
9510 /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
9511 /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
9512 /* .. .. ==> 0XF8006118[2:2] = 0x00000000U */
9513 /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
9514 /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
9515 /* .. .. ==> 0XF8006118[3:3] = 0x00000000U */
9516 /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
9517 /* .. .. reg_phy_board_lpbk_tx = 0x0 */
9518 /* .. .. ==> 0XF8006118[4:4] = 0x00000000U */
9519 /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
9520 /* .. .. reg_phy_board_lpbk_rx = 0x0 */
9521 /* .. .. ==> 0XF8006118[5:5] = 0x00000000U */
9522 /* .. .. ==> MASK : 0x00000020U VAL : 0x00000000U */
9523 /* .. .. reg_phy_bist_shift_dq = 0x0 */
9524 /* .. .. ==> 0XF8006118[14:6] = 0x00000000U */
9525 /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */
9526 /* .. .. reg_phy_bist_err_clr = 0x0 */
9527 /* .. .. ==> 0XF8006118[23:15] = 0x00000000U */
9528 /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */
9529 /* .. .. reg_phy_dq_offset = 0x40 */
9530 /* .. .. ==> 0XF8006118[30:24] = 0x00000040U */
9531 /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */
9532 /* .. .. */
9533 EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU, 0x40000001U),
9534 /* .. .. reg_phy_data_slice_in_use = 0x1 */
9535 /* .. .. ==> 0XF800611C[0:0] = 0x00000001U */
9536 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
9537 /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
9538 /* .. .. ==> 0XF800611C[1:1] = 0x00000000U */
9539 /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
9540 /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
9541 /* .. .. ==> 0XF800611C[2:2] = 0x00000000U */
9542 /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
9543 /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
9544 /* .. .. ==> 0XF800611C[3:3] = 0x00000000U */
9545 /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
9546 /* .. .. reg_phy_board_lpbk_tx = 0x0 */
9547 /* .. .. ==> 0XF800611C[4:4] = 0x00000000U */
9548 /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
9549 /* .. .. reg_phy_board_lpbk_rx = 0x0 */
9550 /* .. .. ==> 0XF800611C[5:5] = 0x00000000U */
9551 /* .. .. ==> MASK : 0x00000020U VAL : 0x00000000U */
9552 /* .. .. reg_phy_bist_shift_dq = 0x0 */
9553 /* .. .. ==> 0XF800611C[14:6] = 0x00000000U */
9554 /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */
9555 /* .. .. reg_phy_bist_err_clr = 0x0 */
9556 /* .. .. ==> 0XF800611C[23:15] = 0x00000000U */
9557 /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */
9558 /* .. .. reg_phy_dq_offset = 0x40 */
9559 /* .. .. ==> 0XF800611C[30:24] = 0x00000040U */
9560 /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */
9561 /* .. .. */
9562 EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU, 0x40000001U),
9563 /* .. .. reg_phy_data_slice_in_use = 0x1 */
9564 /* .. .. ==> 0XF8006120[0:0] = 0x00000001U */
9565 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
9566 /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
9567 /* .. .. ==> 0XF8006120[1:1] = 0x00000000U */
9568 /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
9569 /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
9570 /* .. .. ==> 0XF8006120[2:2] = 0x00000000U */
9571 /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
9572 /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
9573 /* .. .. ==> 0XF8006120[3:3] = 0x00000000U */
9574 /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
9575 /* .. .. reg_phy_board_lpbk_tx = 0x0 */
9576 /* .. .. ==> 0XF8006120[4:4] = 0x00000000U */
9577 /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
9578 /* .. .. reg_phy_board_lpbk_rx = 0x0 */
9579 /* .. .. ==> 0XF8006120[5:5] = 0x00000000U */
9580 /* .. .. ==> MASK : 0x00000020U VAL : 0x00000000U */
9581 /* .. .. reg_phy_bist_shift_dq = 0x0 */
9582 /* .. .. ==> 0XF8006120[14:6] = 0x00000000U */
9583 /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */
9584 /* .. .. reg_phy_bist_err_clr = 0x0 */
9585 /* .. .. ==> 0XF8006120[23:15] = 0x00000000U */
9586 /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */
9587 /* .. .. reg_phy_dq_offset = 0x40 */
9588 /* .. .. ==> 0XF8006120[30:24] = 0x00000040U */
9589 /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */
9590 /* .. .. */
9591 EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU, 0x40000001U),
9592 /* .. .. reg_phy_data_slice_in_use = 0x1 */
9593 /* .. .. ==> 0XF8006124[0:0] = 0x00000001U */
9594 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
9595 /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
9596 /* .. .. ==> 0XF8006124[1:1] = 0x00000000U */
9597 /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
9598 /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
9599 /* .. .. ==> 0XF8006124[2:2] = 0x00000000U */
9600 /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
9601 /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
9602 /* .. .. ==> 0XF8006124[3:3] = 0x00000000U */
9603 /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
9604 /* .. .. reg_phy_board_lpbk_tx = 0x0 */
9605 /* .. .. ==> 0XF8006124[4:4] = 0x00000000U */
9606 /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
9607 /* .. .. reg_phy_board_lpbk_rx = 0x0 */
9608 /* .. .. ==> 0XF8006124[5:5] = 0x00000000U */
9609 /* .. .. ==> MASK : 0x00000020U VAL : 0x00000000U */
9610 /* .. .. reg_phy_bist_shift_dq = 0x0 */
9611 /* .. .. ==> 0XF8006124[14:6] = 0x00000000U */
9612 /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */
9613 /* .. .. reg_phy_bist_err_clr = 0x0 */
9614 /* .. .. ==> 0XF8006124[23:15] = 0x00000000U */
9615 /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */
9616 /* .. .. reg_phy_dq_offset = 0x40 */
9617 /* .. .. ==> 0XF8006124[30:24] = 0x00000040U */
9618 /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */
9619 /* .. .. */
9620 EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU, 0x40000001U),
9621 /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
9622 /* .. .. ==> 0XF800612C[9:0] = 0x00000000U */
9623 /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */
9624 /* .. .. reg_phy_gatelvl_init_ratio = 0x8f */
9625 /* .. .. ==> 0XF800612C[19:10] = 0x0000008FU */
9626 /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00023C00U */
9627 /* .. .. */
9628 EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x00023C00U),
9629 /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
9630 /* .. .. ==> 0XF8006130[9:0] = 0x00000000U */
9631 /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */
9632 /* .. .. reg_phy_gatelvl_init_ratio = 0x8a */
9633 /* .. .. ==> 0XF8006130[19:10] = 0x0000008AU */
9634 /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00022800U */
9635 /* .. .. */
9636 EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x00022800U),
9637 /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
9638 /* .. .. ==> 0XF8006134[9:0] = 0x00000000U */
9639 /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */
9640 /* .. .. reg_phy_gatelvl_init_ratio = 0x8b */
9641 /* .. .. ==> 0XF8006134[19:10] = 0x0000008BU */
9642 /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00022C00U */
9643 /* .. .. */
9644 EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x00022C00U),
9645 /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
9646 /* .. .. ==> 0XF8006138[9:0] = 0x00000000U */
9647 /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */
9648 /* .. .. reg_phy_gatelvl_init_ratio = 0x92 */
9649 /* .. .. ==> 0XF8006138[19:10] = 0x00000092U */
9650 /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00024800U */
9651 /* .. .. */
9652 EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x00024800U),
9653 /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
9654 /* .. .. ==> 0XF8006140[9:0] = 0x00000035U */
9655 /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */
9656 /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
9657 /* .. .. ==> 0XF8006140[10:10] = 0x00000000U */
9658 /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
9659 /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
9660 /* .. .. ==> 0XF8006140[19:11] = 0x00000000U */
9661 /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
9662 /* .. .. */
9663 EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U),
9664 /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
9665 /* .. .. ==> 0XF8006144[9:0] = 0x00000035U */
9666 /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */
9667 /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
9668 /* .. .. ==> 0XF8006144[10:10] = 0x00000000U */
9669 /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
9670 /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
9671 /* .. .. ==> 0XF8006144[19:11] = 0x00000000U */
9672 /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
9673 /* .. .. */
9674 EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U),
9675 /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
9676 /* .. .. ==> 0XF8006148[9:0] = 0x00000035U */
9677 /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */
9678 /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
9679 /* .. .. ==> 0XF8006148[10:10] = 0x00000000U */
9680 /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
9681 /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
9682 /* .. .. ==> 0XF8006148[19:11] = 0x00000000U */
9683 /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
9684 /* .. .. */
9685 EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U),
9686 /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
9687 /* .. .. ==> 0XF800614C[9:0] = 0x00000035U */
9688 /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */
9689 /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
9690 /* .. .. ==> 0XF800614C[10:10] = 0x00000000U */
9691 /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
9692 /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
9693 /* .. .. ==> 0XF800614C[19:11] = 0x00000000U */
9694 /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
9695 /* .. .. */
9696 EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U),
9697 /* .. .. reg_phy_wr_dqs_slave_ratio = 0x77 */
9698 /* .. .. ==> 0XF8006154[9:0] = 0x00000077U */
9699 /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000077U */
9700 /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
9701 /* .. .. ==> 0XF8006154[10:10] = 0x00000000U */
9702 /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
9703 /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
9704 /* .. .. ==> 0XF8006154[19:11] = 0x00000000U */
9705 /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
9706 /* .. .. */
9707 EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x00000077U),
9708 /* .. .. reg_phy_wr_dqs_slave_ratio = 0x7c */
9709 /* .. .. ==> 0XF8006158[9:0] = 0x0000007CU */
9710 /* .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU */
9711 /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
9712 /* .. .. ==> 0XF8006158[10:10] = 0x00000000U */
9713 /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
9714 /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
9715 /* .. .. ==> 0XF8006158[19:11] = 0x00000000U */
9716 /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
9717 /* .. .. */
9718 EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x0000007CU),
9719 /* .. .. reg_phy_wr_dqs_slave_ratio = 0x7c */
9720 /* .. .. ==> 0XF800615C[9:0] = 0x0000007CU */
9721 /* .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU */
9722 /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
9723 /* .. .. ==> 0XF800615C[10:10] = 0x00000000U */
9724 /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
9725 /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
9726 /* .. .. ==> 0XF800615C[19:11] = 0x00000000U */
9727 /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
9728 /* .. .. */
9729 EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x0000007CU),
9730 /* .. .. reg_phy_wr_dqs_slave_ratio = 0x75 */
9731 /* .. .. ==> 0XF8006160[9:0] = 0x00000075U */
9732 /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000075U */
9733 /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
9734 /* .. .. ==> 0XF8006160[10:10] = 0x00000000U */
9735 /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
9736 /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
9737 /* .. .. ==> 0XF8006160[19:11] = 0x00000000U */
9738 /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
9739 /* .. .. */
9740 EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x00000075U),
9741 /* .. .. reg_phy_fifo_we_slave_ratio = 0xe4 */
9742 /* .. .. ==> 0XF8006168[10:0] = 0x000000E4U */
9743 /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000E4U */
9744 /* .. .. reg_phy_fifo_we_in_force = 0x0 */
9745 /* .. .. ==> 0XF8006168[11:11] = 0x00000000U */
9746 /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */
9747 /* .. .. reg_phy_fifo_we_in_delay = 0x0 */
9748 /* .. .. ==> 0XF8006168[20:12] = 0x00000000U */
9749 /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */
9750 /* .. .. */
9751 EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000E4U),
9752 /* .. .. reg_phy_fifo_we_slave_ratio = 0xdf */
9753 /* .. .. ==> 0XF800616C[10:0] = 0x000000DFU */
9754 /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000DFU */
9755 /* .. .. reg_phy_fifo_we_in_force = 0x0 */
9756 /* .. .. ==> 0XF800616C[11:11] = 0x00000000U */
9757 /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */
9758 /* .. .. reg_phy_fifo_we_in_delay = 0x0 */
9759 /* .. .. ==> 0XF800616C[20:12] = 0x00000000U */
9760 /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */
9761 /* .. .. */
9762 EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000DFU),
9763 /* .. .. reg_phy_fifo_we_slave_ratio = 0xe0 */
9764 /* .. .. ==> 0XF8006170[10:0] = 0x000000E0U */
9765 /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000E0U */
9766 /* .. .. reg_phy_fifo_we_in_force = 0x0 */
9767 /* .. .. ==> 0XF8006170[11:11] = 0x00000000U */
9768 /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */
9769 /* .. .. reg_phy_fifo_we_in_delay = 0x0 */
9770 /* .. .. ==> 0XF8006170[20:12] = 0x00000000U */
9771 /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */
9772 /* .. .. */
9773 EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000E0U),
9774 /* .. .. reg_phy_fifo_we_slave_ratio = 0xe7 */
9775 /* .. .. ==> 0XF8006174[10:0] = 0x000000E7U */
9776 /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000E7U */
9777 /* .. .. reg_phy_fifo_we_in_force = 0x0 */
9778 /* .. .. ==> 0XF8006174[11:11] = 0x00000000U */
9779 /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */
9780 /* .. .. reg_phy_fifo_we_in_delay = 0x0 */
9781 /* .. .. ==> 0XF8006174[20:12] = 0x00000000U */
9782 /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */
9783 /* .. .. */
9784 EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000E7U),
9785 /* .. .. reg_phy_wr_data_slave_ratio = 0xb7 */
9786 /* .. .. ==> 0XF800617C[9:0] = 0x000000B7U */
9787 /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000B7U */
9788 /* .. .. reg_phy_wr_data_slave_force = 0x0 */
9789 /* .. .. ==> 0XF800617C[10:10] = 0x00000000U */
9790 /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
9791 /* .. .. reg_phy_wr_data_slave_delay = 0x0 */
9792 /* .. .. ==> 0XF800617C[19:11] = 0x00000000U */
9793 /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
9794 /* .. .. */
9795 EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000B7U),
9796 /* .. .. reg_phy_wr_data_slave_ratio = 0xbc */
9797 /* .. .. ==> 0XF8006180[9:0] = 0x000000BCU */
9798 /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU */
9799 /* .. .. reg_phy_wr_data_slave_force = 0x0 */
9800 /* .. .. ==> 0XF8006180[10:10] = 0x00000000U */
9801 /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
9802 /* .. .. reg_phy_wr_data_slave_delay = 0x0 */
9803 /* .. .. ==> 0XF8006180[19:11] = 0x00000000U */
9804 /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
9805 /* .. .. */
9806 EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000BCU),
9807 /* .. .. reg_phy_wr_data_slave_ratio = 0xbc */
9808 /* .. .. ==> 0XF8006184[9:0] = 0x000000BCU */
9809 /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU */
9810 /* .. .. reg_phy_wr_data_slave_force = 0x0 */
9811 /* .. .. ==> 0XF8006184[10:10] = 0x00000000U */
9812 /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
9813 /* .. .. reg_phy_wr_data_slave_delay = 0x0 */
9814 /* .. .. ==> 0XF8006184[19:11] = 0x00000000U */
9815 /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
9816 /* .. .. */
9817 EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000BCU),
9818 /* .. .. reg_phy_wr_data_slave_ratio = 0xb5 */
9819 /* .. .. ==> 0XF8006188[9:0] = 0x000000B5U */
9820 /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000B5U */
9821 /* .. .. reg_phy_wr_data_slave_force = 0x0 */
9822 /* .. .. ==> 0XF8006188[10:10] = 0x00000000U */
9823 /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
9824 /* .. .. reg_phy_wr_data_slave_delay = 0x0 */
9825 /* .. .. ==> 0XF8006188[19:11] = 0x00000000U */
9826 /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
9827 /* .. .. */
9828 EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000B5U),
9829 /* .. .. reg_phy_loopback = 0x0 */
9830 /* .. .. ==> 0XF8006190[0:0] = 0x00000000U */
9831 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
9832 /* .. .. reg_phy_bl2 = 0x0 */
9833 /* .. .. ==> 0XF8006190[1:1] = 0x00000000U */
9834 /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
9835 /* .. .. reg_phy_at_spd_atpg = 0x0 */
9836 /* .. .. ==> 0XF8006190[2:2] = 0x00000000U */
9837 /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
9838 /* .. .. reg_phy_bist_enable = 0x0 */
9839 /* .. .. ==> 0XF8006190[3:3] = 0x00000000U */
9840 /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
9841 /* .. .. reg_phy_bist_force_err = 0x0 */
9842 /* .. .. ==> 0XF8006190[4:4] = 0x00000000U */
9843 /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
9844 /* .. .. reg_phy_bist_mode = 0x0 */
9845 /* .. .. ==> 0XF8006190[6:5] = 0x00000000U */
9846 /* .. .. ==> MASK : 0x00000060U VAL : 0x00000000U */
9847 /* .. .. reg_phy_invert_clkout = 0x1 */
9848 /* .. .. ==> 0XF8006190[7:7] = 0x00000001U */
9849 /* .. .. ==> MASK : 0x00000080U VAL : 0x00000080U */
9850 /* .. .. reg_phy_all_dq_mpr_rd_resp = 0x0 */
9851 /* .. .. ==> 0XF8006190[8:8] = 0x00000000U */
9852 /* .. .. ==> MASK : 0x00000100U VAL : 0x00000000U */
9853 /* .. .. reg_phy_sel_logic = 0x0 */
9854 /* .. .. ==> 0XF8006190[9:9] = 0x00000000U */
9855 /* .. .. ==> MASK : 0x00000200U VAL : 0x00000000U */
9856 /* .. .. reg_phy_ctrl_slave_ratio = 0x100 */
9857 /* .. .. ==> 0XF8006190[19:10] = 0x00000100U */
9858 /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U */
9859 /* .. .. reg_phy_ctrl_slave_force = 0x0 */
9860 /* .. .. ==> 0XF8006190[20:20] = 0x00000000U */
9861 /* .. .. ==> MASK : 0x00100000U VAL : 0x00000000U */
9862 /* .. .. reg_phy_ctrl_slave_delay = 0x0 */
9863 /* .. .. ==> 0XF8006190[27:21] = 0x00000000U */
9864 /* .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U */
9865 /* .. .. reg_phy_use_rank0_delays = 0x1 */
9866 /* .. .. ==> 0XF8006190[28:28] = 0x00000001U */
9867 /* .. .. ==> MASK : 0x10000000U VAL : 0x10000000U */
9868 /* .. .. reg_phy_lpddr = 0x0 */
9869 /* .. .. ==> 0XF8006190[29:29] = 0x00000000U */
9870 /* .. .. ==> MASK : 0x20000000U VAL : 0x00000000U */
9871 /* .. .. reg_phy_cmd_latency = 0x0 */
9872 /* .. .. ==> 0XF8006190[30:30] = 0x00000000U */
9873 /* .. .. ==> MASK : 0x40000000U VAL : 0x00000000U */
9874 /* .. .. reg_phy_int_lpbk = 0x0 */
9875 /* .. .. ==> 0XF8006190[31:31] = 0x00000000U */
9876 /* .. .. ==> MASK : 0x80000000U VAL : 0x00000000U */
9877 /* .. .. */
9878 EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU, 0x10040080U),
9879 /* .. .. reg_phy_wr_rl_delay = 0x2 */
9880 /* .. .. ==> 0XF8006194[4:0] = 0x00000002U */
9881 /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U */
9882 /* .. .. reg_phy_rd_rl_delay = 0x4 */
9883 /* .. .. ==> 0XF8006194[9:5] = 0x00000004U */
9884 /* .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U */
9885 /* .. .. reg_phy_dll_lock_diff = 0xf */
9886 /* .. .. ==> 0XF8006194[13:10] = 0x0000000FU */
9887 /* .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U */
9888 /* .. .. reg_phy_use_wr_level = 0x1 */
9889 /* .. .. ==> 0XF8006194[14:14] = 0x00000001U */
9890 /* .. .. ==> MASK : 0x00004000U VAL : 0x00004000U */
9891 /* .. .. reg_phy_use_rd_dqs_gate_level = 0x1 */
9892 /* .. .. ==> 0XF8006194[15:15] = 0x00000001U */
9893 /* .. .. ==> MASK : 0x00008000U VAL : 0x00008000U */
9894 /* .. .. reg_phy_use_rd_data_eye_level = 0x1 */
9895 /* .. .. ==> 0XF8006194[16:16] = 0x00000001U */
9896 /* .. .. ==> MASK : 0x00010000U VAL : 0x00010000U */
9897 /* .. .. reg_phy_dis_calib_rst = 0x0 */
9898 /* .. .. ==> 0XF8006194[17:17] = 0x00000000U */
9899 /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
9900 /* .. .. reg_phy_ctrl_slave_delay = 0x0 */
9901 /* .. .. ==> 0XF8006194[19:18] = 0x00000000U */
9902 /* .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U */
9903 /* .. .. */
9904 EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FC82U),
9905 /* .. .. reg_arb_page_addr_mask = 0x0 */
9906 /* .. .. ==> 0XF8006204[31:0] = 0x00000000U */
9907 /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */
9908 /* .. .. */
9909 EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U),
9910 /* .. .. reg_arb_pri_wr_portn = 0x3ff */
9911 /* .. .. ==> 0XF8006208[9:0] = 0x000003FFU */
9912 /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
9913 /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
9914 /* .. .. ==> 0XF8006208[16:16] = 0x00000000U */
9915 /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
9916 /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
9917 /* .. .. ==> 0XF8006208[17:17] = 0x00000000U */
9918 /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
9919 /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
9920 /* .. .. ==> 0XF8006208[18:18] = 0x00000000U */
9921 /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
9922 /* .. .. reg_arb_dis_rmw_portn = 0x1 */
9923 /* .. .. ==> 0XF8006208[19:19] = 0x00000001U */
9924 /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */
9925 /* .. .. */
9926 EMIT_MASKWRITE(0XF8006208, 0x000F03FFU, 0x000803FFU),
9927 /* .. .. reg_arb_pri_wr_portn = 0x3ff */
9928 /* .. .. ==> 0XF800620C[9:0] = 0x000003FFU */
9929 /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
9930 /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
9931 /* .. .. ==> 0XF800620C[16:16] = 0x00000000U */
9932 /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
9933 /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
9934 /* .. .. ==> 0XF800620C[17:17] = 0x00000000U */
9935 /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
9936 /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
9937 /* .. .. ==> 0XF800620C[18:18] = 0x00000000U */
9938 /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
9939 /* .. .. reg_arb_dis_rmw_portn = 0x1 */
9940 /* .. .. ==> 0XF800620C[19:19] = 0x00000001U */
9941 /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */
9942 /* .. .. */
9943 EMIT_MASKWRITE(0XF800620C, 0x000F03FFU, 0x000803FFU),
9944 /* .. .. reg_arb_pri_wr_portn = 0x3ff */
9945 /* .. .. ==> 0XF8006210[9:0] = 0x000003FFU */
9946 /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
9947 /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
9948 /* .. .. ==> 0XF8006210[16:16] = 0x00000000U */
9949 /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
9950 /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
9951 /* .. .. ==> 0XF8006210[17:17] = 0x00000000U */
9952 /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
9953 /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
9954 /* .. .. ==> 0XF8006210[18:18] = 0x00000000U */
9955 /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
9956 /* .. .. reg_arb_dis_rmw_portn = 0x1 */
9957 /* .. .. ==> 0XF8006210[19:19] = 0x00000001U */
9958 /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */
9959 /* .. .. */
9960 EMIT_MASKWRITE(0XF8006210, 0x000F03FFU, 0x000803FFU),
9961 /* .. .. reg_arb_pri_wr_portn = 0x3ff */
9962 /* .. .. ==> 0XF8006214[9:0] = 0x000003FFU */
9963 /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
9964 /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
9965 /* .. .. ==> 0XF8006214[16:16] = 0x00000000U */
9966 /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
9967 /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
9968 /* .. .. ==> 0XF8006214[17:17] = 0x00000000U */
9969 /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
9970 /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
9971 /* .. .. ==> 0XF8006214[18:18] = 0x00000000U */
9972 /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
9973 /* .. .. reg_arb_dis_rmw_portn = 0x1 */
9974 /* .. .. ==> 0XF8006214[19:19] = 0x00000001U */
9975 /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */
9976 /* .. .. */
9977 EMIT_MASKWRITE(0XF8006214, 0x000F03FFU, 0x000803FFU),
9978 /* .. .. reg_arb_pri_rd_portn = 0x3ff */
9979 /* .. .. ==> 0XF8006218[9:0] = 0x000003FFU */
9980 /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
9981 /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
9982 /* .. .. ==> 0XF8006218[16:16] = 0x00000000U */
9983 /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
9984 /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
9985 /* .. .. ==> 0XF8006218[17:17] = 0x00000000U */
9986 /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
9987 /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
9988 /* .. .. ==> 0XF8006218[18:18] = 0x00000000U */
9989 /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
9990 /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
9991 /* .. .. ==> 0XF8006218[19:19] = 0x00000000U */
9992 /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */
9993 /* .. .. */
9994 EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU),
9995 /* .. .. reg_arb_pri_rd_portn = 0x3ff */
9996 /* .. .. ==> 0XF800621C[9:0] = 0x000003FFU */
9997 /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
9998 /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
9999 /* .. .. ==> 0XF800621C[16:16] = 0x00000000U */
10000 /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
10001 /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
10002 /* .. .. ==> 0XF800621C[17:17] = 0x00000000U */
10003 /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
10004 /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
10005 /* .. .. ==> 0XF800621C[18:18] = 0x00000000U */
10006 /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
10007 /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
10008 /* .. .. ==> 0XF800621C[19:19] = 0x00000000U */
10009 /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */
10010 /* .. .. */
10011 EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU),
10012 /* .. .. reg_arb_pri_rd_portn = 0x3ff */
10013 /* .. .. ==> 0XF8006220[9:0] = 0x000003FFU */
10014 /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
10015 /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
10016 /* .. .. ==> 0XF8006220[16:16] = 0x00000000U */
10017 /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
10018 /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
10019 /* .. .. ==> 0XF8006220[17:17] = 0x00000000U */
10020 /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
10021 /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
10022 /* .. .. ==> 0XF8006220[18:18] = 0x00000000U */
10023 /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
10024 /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
10025 /* .. .. ==> 0XF8006220[19:19] = 0x00000000U */
10026 /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */
10027 /* .. .. */
10028 EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU),
10029 /* .. .. reg_arb_pri_rd_portn = 0x3ff */
10030 /* .. .. ==> 0XF8006224[9:0] = 0x000003FFU */
10031 /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
10032 /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
10033 /* .. .. ==> 0XF8006224[16:16] = 0x00000000U */
10034 /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
10035 /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
10036 /* .. .. ==> 0XF8006224[17:17] = 0x00000000U */
10037 /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
10038 /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
10039 /* .. .. ==> 0XF8006224[18:18] = 0x00000000U */
10040 /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
10041 /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
10042 /* .. .. ==> 0XF8006224[19:19] = 0x00000000U */
10043 /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */
10044 /* .. .. */
10045 EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU),
10046 /* .. .. reg_ddrc_lpddr2 = 0x0 */
10047 /* .. .. ==> 0XF80062A8[0:0] = 0x00000000U */
10048 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
10049 /* .. .. reg_ddrc_per_bank_refresh = 0x0 */
10050 /* .. .. ==> 0XF80062A8[1:1] = 0x00000000U */
10051 /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
10052 /* .. .. reg_ddrc_derate_enable = 0x0 */
10053 /* .. .. ==> 0XF80062A8[2:2] = 0x00000000U */
10054 /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
10055 /* .. .. reg_ddrc_mr4_margin = 0x0 */
10056 /* .. .. ==> 0XF80062A8[11:4] = 0x00000000U */
10057 /* .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U */
10058 /* .. .. */
10059 EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U, 0x00000000U),
10060 /* .. .. reg_ddrc_mr4_read_interval = 0x0 */
10061 /* .. .. ==> 0XF80062AC[31:0] = 0x00000000U */
10062 /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */
10063 /* .. .. */
10064 EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U),
10065 /* .. .. reg_ddrc_min_stable_clock_x1 = 0x5 */
10066 /* .. .. ==> 0XF80062B0[3:0] = 0x00000005U */
10067 /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U */
10068 /* .. .. reg_ddrc_idle_after_reset_x32 = 0x12 */
10069 /* .. .. ==> 0XF80062B0[11:4] = 0x00000012U */
10070 /* .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U */
10071 /* .. .. reg_ddrc_t_mrw = 0x5 */
10072 /* .. .. ==> 0XF80062B0[21:12] = 0x00000005U */
10073 /* .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U */
10074 /* .. .. */
10075 EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U),
10076 /* .. .. reg_ddrc_max_auto_init_x1024 = 0xa6 */
10077 /* .. .. ==> 0XF80062B4[7:0] = 0x000000A6U */
10078 /* .. .. ==> MASK : 0x000000FFU VAL : 0x000000A6U */
10079 /* .. .. reg_ddrc_dev_zqinit_x32 = 0x12 */
10080 /* .. .. ==> 0XF80062B4[17:8] = 0x00000012U */
10081 /* .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U */
10082 /* .. .. */
10083 EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A6U),
10084 /* .. .. START: POLL ON DCI STATUS */
10085 /* .. .. DONE = 1 */
10086 /* .. .. ==> 0XF8000B74[13:13] = 0x00000001U */
10087 /* .. .. ==> MASK : 0x00002000U VAL : 0x00002000U */
10088 /* .. .. */
10089 EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
10090 /* .. .. FINISH: POLL ON DCI STATUS */
10091 /* .. .. START: UNLOCK DDR */
10092 /* .. .. reg_ddrc_soft_rstb = 0x1 */
10093 /* .. .. ==> 0XF8006000[0:0] = 0x00000001U */
10094 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
10095 /* .. .. reg_ddrc_powerdown_en = 0x0 */
10096 /* .. .. ==> 0XF8006000[1:1] = 0x00000000U */
10097 /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
10098 /* .. .. reg_ddrc_data_bus_width = 0x0 */
10099 /* .. .. ==> 0XF8006000[3:2] = 0x00000000U */
10100 /* .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U */
10101 /* .. .. reg_ddrc_burst8_refresh = 0x0 */
10102 /* .. .. ==> 0XF8006000[6:4] = 0x00000000U */
10103 /* .. .. ==> MASK : 0x00000070U VAL : 0x00000000U */
10104 /* .. .. reg_ddrc_rdwr_idle_gap = 1 */
10105 /* .. .. ==> 0XF8006000[13:7] = 0x00000001U */
10106 /* .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U */
10107 /* .. .. reg_ddrc_dis_rd_bypass = 0x0 */
10108 /* .. .. ==> 0XF8006000[14:14] = 0x00000000U */
10109 /* .. .. ==> MASK : 0x00004000U VAL : 0x00000000U */
10110 /* .. .. reg_ddrc_dis_act_bypass = 0x0 */
10111 /* .. .. ==> 0XF8006000[15:15] = 0x00000000U */
10112 /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */
10113 /* .. .. reg_ddrc_dis_auto_refresh = 0x0 */
10114 /* .. .. ==> 0XF8006000[16:16] = 0x00000000U */
10115 /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
10116 /* .. .. */
10117 EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U),
10118 /* .. .. FINISH: UNLOCK DDR */
10119 /* .. .. START: CHECK DDR STATUS */
10120 /* .. .. ddrc_reg_operating_mode = 1 */
10121 /* .. .. ==> 0XF8006054[2:0] = 0x00000001U */
10122 /* .. .. ==> MASK : 0x00000007U VAL : 0x00000001U */
10123 /* .. .. */
10124 EMIT_MASKPOLL(0XF8006054, 0x00000007U),
10125 /* .. .. FINISH: CHECK DDR STATUS */
10126 /* .. FINISH: DDR INITIALIZATION */
10127 /* FINISH: top */
10128 /* */
10129 EMIT_EXIT(),
10130
10131 /* */
10132};
10133
10134unsigned long ps7_mio_init_data_1_0[] = {
10135 /* START: top */
10136 /* .. START: SLCR SETTINGS */
10137 /* .. UNLOCK_KEY = 0XDF0D */
10138 /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
10139 /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */
10140 /* .. */
10141 EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
10142 /* .. FINISH: SLCR SETTINGS */
10143 /* .. START: OCM REMAPPING */
10144 /* .. VREF_EN = 0x1 */
10145 /* .. ==> 0XF8000B00[0:0] = 0x00000001U */
10146 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
10147 /* .. VREF_PULLUP_EN = 0x0 */
10148 /* .. ==> 0XF8000B00[1:1] = 0x00000000U */
10149 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
10150 /* .. CLK_PULLUP_EN = 0x0 */
10151 /* .. ==> 0XF8000B00[8:8] = 0x00000000U */
10152 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
10153 /* .. SRSTN_PULLUP_EN = 0x0 */
10154 /* .. ==> 0XF8000B00[9:9] = 0x00000000U */
10155 /* .. ==> MASK : 0x00000200U VAL : 0x00000000U */
10156 /* .. */
10157 EMIT_MASKWRITE(0XF8000B00, 0x00000303U, 0x00000001U),
10158 /* .. FINISH: OCM REMAPPING */
10159 /* .. START: DDRIOB SETTINGS */
10160 /* .. INP_POWER = 0x0 */
10161 /* .. ==> 0XF8000B40[0:0] = 0x00000000U */
10162 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
10163 /* .. INP_TYPE = 0x0 */
10164 /* .. ==> 0XF8000B40[2:1] = 0x00000000U */
10165 /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */
10166 /* .. DCI_UPDATE = 0x0 */
10167 /* .. ==> 0XF8000B40[3:3] = 0x00000000U */
10168 /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
10169 /* .. TERM_EN = 0x0 */
10170 /* .. ==> 0XF8000B40[4:4] = 0x00000000U */
10171 /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */
10172 /* .. DCR_TYPE = 0x0 */
10173 /* .. ==> 0XF8000B40[6:5] = 0x00000000U */
10174 /* .. ==> MASK : 0x00000060U VAL : 0x00000000U */
10175 /* .. IBUF_DISABLE_MODE = 0x0 */
10176 /* .. ==> 0XF8000B40[7:7] = 0x00000000U */
10177 /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
10178 /* .. TERM_DISABLE_MODE = 0x0 */
10179 /* .. ==> 0XF8000B40[8:8] = 0x00000000U */
10180 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
10181 /* .. OUTPUT_EN = 0x3 */
10182 /* .. ==> 0XF8000B40[10:9] = 0x00000003U */
10183 /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
10184 /* .. PULLUP_EN = 0x0 */
10185 /* .. ==> 0XF8000B40[11:11] = 0x00000000U */
10186 /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
10187 /* .. */
10188 EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U),
10189 /* .. INP_POWER = 0x0 */
10190 /* .. ==> 0XF8000B44[0:0] = 0x00000000U */
10191 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
10192 /* .. INP_TYPE = 0x0 */
10193 /* .. ==> 0XF8000B44[2:1] = 0x00000000U */
10194 /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */
10195 /* .. DCI_UPDATE = 0x0 */
10196 /* .. ==> 0XF8000B44[3:3] = 0x00000000U */
10197 /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
10198 /* .. TERM_EN = 0x0 */
10199 /* .. ==> 0XF8000B44[4:4] = 0x00000000U */
10200 /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */
10201 /* .. DCR_TYPE = 0x0 */
10202 /* .. ==> 0XF8000B44[6:5] = 0x00000000U */
10203 /* .. ==> MASK : 0x00000060U VAL : 0x00000000U */
10204 /* .. IBUF_DISABLE_MODE = 0x0 */
10205 /* .. ==> 0XF8000B44[7:7] = 0x00000000U */
10206 /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
10207 /* .. TERM_DISABLE_MODE = 0x0 */
10208 /* .. ==> 0XF8000B44[8:8] = 0x00000000U */
10209 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
10210 /* .. OUTPUT_EN = 0x3 */
10211 /* .. ==> 0XF8000B44[10:9] = 0x00000003U */
10212 /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
10213 /* .. PULLUP_EN = 0x0 */
10214 /* .. ==> 0XF8000B44[11:11] = 0x00000000U */
10215 /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
10216 /* .. */
10217 EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U),
10218 /* .. INP_POWER = 0x0 */
10219 /* .. ==> 0XF8000B48[0:0] = 0x00000000U */
10220 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
10221 /* .. INP_TYPE = 0x1 */
10222 /* .. ==> 0XF8000B48[2:1] = 0x00000001U */
10223 /* .. ==> MASK : 0x00000006U VAL : 0x00000002U */
10224 /* .. DCI_UPDATE = 0x0 */
10225 /* .. ==> 0XF8000B48[3:3] = 0x00000000U */
10226 /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
10227 /* .. TERM_EN = 0x1 */
10228 /* .. ==> 0XF8000B48[4:4] = 0x00000001U */
10229 /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */
10230 /* .. DCR_TYPE = 0x3 */
10231 /* .. ==> 0XF8000B48[6:5] = 0x00000003U */
10232 /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */
10233 /* .. IBUF_DISABLE_MODE = 0 */
10234 /* .. ==> 0XF8000B48[7:7] = 0x00000000U */
10235 /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
10236 /* .. TERM_DISABLE_MODE = 0 */
10237 /* .. ==> 0XF8000B48[8:8] = 0x00000000U */
10238 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
10239 /* .. OUTPUT_EN = 0x3 */
10240 /* .. ==> 0XF8000B48[10:9] = 0x00000003U */
10241 /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
10242 /* .. PULLUP_EN = 0x0 */
10243 /* .. ==> 0XF8000B48[11:11] = 0x00000000U */
10244 /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
10245 /* .. */
10246 EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U),
10247 /* .. INP_POWER = 0x0 */
10248 /* .. ==> 0XF8000B4C[0:0] = 0x00000000U */
10249 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
10250 /* .. INP_TYPE = 0x1 */
10251 /* .. ==> 0XF8000B4C[2:1] = 0x00000001U */
10252 /* .. ==> MASK : 0x00000006U VAL : 0x00000002U */
10253 /* .. DCI_UPDATE = 0x0 */
10254 /* .. ==> 0XF8000B4C[3:3] = 0x00000000U */
10255 /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
10256 /* .. TERM_EN = 0x1 */
10257 /* .. ==> 0XF8000B4C[4:4] = 0x00000001U */
10258 /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */
10259 /* .. DCR_TYPE = 0x3 */
10260 /* .. ==> 0XF8000B4C[6:5] = 0x00000003U */
10261 /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */
10262 /* .. IBUF_DISABLE_MODE = 0 */
10263 /* .. ==> 0XF8000B4C[7:7] = 0x00000000U */
10264 /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
10265 /* .. TERM_DISABLE_MODE = 0 */
10266 /* .. ==> 0XF8000B4C[8:8] = 0x00000000U */
10267 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
10268 /* .. OUTPUT_EN = 0x3 */
10269 /* .. ==> 0XF8000B4C[10:9] = 0x00000003U */
10270 /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
10271 /* .. PULLUP_EN = 0x0 */
10272 /* .. ==> 0XF8000B4C[11:11] = 0x00000000U */
10273 /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
10274 /* .. */
10275 EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U),
10276 /* .. INP_POWER = 0x0 */
10277 /* .. ==> 0XF8000B50[0:0] = 0x00000000U */
10278 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
10279 /* .. INP_TYPE = 0x2 */
10280 /* .. ==> 0XF8000B50[2:1] = 0x00000002U */
10281 /* .. ==> MASK : 0x00000006U VAL : 0x00000004U */
10282 /* .. DCI_UPDATE = 0x0 */
10283 /* .. ==> 0XF8000B50[3:3] = 0x00000000U */
10284 /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
10285 /* .. TERM_EN = 0x1 */
10286 /* .. ==> 0XF8000B50[4:4] = 0x00000001U */
10287 /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */
10288 /* .. DCR_TYPE = 0x3 */
10289 /* .. ==> 0XF8000B50[6:5] = 0x00000003U */
10290 /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */
10291 /* .. IBUF_DISABLE_MODE = 0 */
10292 /* .. ==> 0XF8000B50[7:7] = 0x00000000U */
10293 /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
10294 /* .. TERM_DISABLE_MODE = 0 */
10295 /* .. ==> 0XF8000B50[8:8] = 0x00000000U */
10296 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
10297 /* .. OUTPUT_EN = 0x3 */
10298 /* .. ==> 0XF8000B50[10:9] = 0x00000003U */
10299 /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
10300 /* .. PULLUP_EN = 0x0 */
10301 /* .. ==> 0XF8000B50[11:11] = 0x00000000U */
10302 /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
10303 /* .. */
10304 EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U),
10305 /* .. INP_POWER = 0x0 */
10306 /* .. ==> 0XF8000B54[0:0] = 0x00000000U */
10307 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
10308 /* .. INP_TYPE = 0x2 */
10309 /* .. ==> 0XF8000B54[2:1] = 0x00000002U */
10310 /* .. ==> MASK : 0x00000006U VAL : 0x00000004U */
10311 /* .. DCI_UPDATE = 0x0 */
10312 /* .. ==> 0XF8000B54[3:3] = 0x00000000U */
10313 /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
10314 /* .. TERM_EN = 0x1 */
10315 /* .. ==> 0XF8000B54[4:4] = 0x00000001U */
10316 /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */
10317 /* .. DCR_TYPE = 0x3 */
10318 /* .. ==> 0XF8000B54[6:5] = 0x00000003U */
10319 /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */
10320 /* .. IBUF_DISABLE_MODE = 0 */
10321 /* .. ==> 0XF8000B54[7:7] = 0x00000000U */
10322 /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
10323 /* .. TERM_DISABLE_MODE = 0 */
10324 /* .. ==> 0XF8000B54[8:8] = 0x00000000U */
10325 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
10326 /* .. OUTPUT_EN = 0x3 */
10327 /* .. ==> 0XF8000B54[10:9] = 0x00000003U */
10328 /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
10329 /* .. PULLUP_EN = 0x0 */
10330 /* .. ==> 0XF8000B54[11:11] = 0x00000000U */
10331 /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
10332 /* .. */
10333 EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U),
10334 /* .. INP_POWER = 0x0 */
10335 /* .. ==> 0XF8000B58[0:0] = 0x00000000U */
10336 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
10337 /* .. INP_TYPE = 0x0 */
10338 /* .. ==> 0XF8000B58[2:1] = 0x00000000U */
10339 /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */
10340 /* .. DCI_UPDATE = 0x0 */
10341 /* .. ==> 0XF8000B58[3:3] = 0x00000000U */
10342 /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
10343 /* .. TERM_EN = 0x0 */
10344 /* .. ==> 0XF8000B58[4:4] = 0x00000000U */
10345 /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */
10346 /* .. DCR_TYPE = 0x0 */
10347 /* .. ==> 0XF8000B58[6:5] = 0x00000000U */
10348 /* .. ==> MASK : 0x00000060U VAL : 0x00000000U */
10349 /* .. IBUF_DISABLE_MODE = 0x0 */
10350 /* .. ==> 0XF8000B58[7:7] = 0x00000000U */
10351 /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
10352 /* .. TERM_DISABLE_MODE = 0x0 */
10353 /* .. ==> 0XF8000B58[8:8] = 0x00000000U */
10354 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
10355 /* .. OUTPUT_EN = 0x3 */
10356 /* .. ==> 0XF8000B58[10:9] = 0x00000003U */
10357 /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
10358 /* .. PULLUP_EN = 0x0 */
10359 /* .. ==> 0XF8000B58[11:11] = 0x00000000U */
10360 /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
10361 /* .. */
10362 EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U),
10363 /* .. DRIVE_P = 0x1c */
10364 /* .. ==> 0XF8000B5C[6:0] = 0x0000001CU */
10365 /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */
10366 /* .. DRIVE_N = 0xc */
10367 /* .. ==> 0XF8000B5C[13:7] = 0x0000000CU */
10368 /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */
10369 /* .. SLEW_P = 0x3 */
10370 /* .. ==> 0XF8000B5C[18:14] = 0x00000003U */
10371 /* .. ==> MASK : 0x0007C000U VAL : 0x0000C000U */
10372 /* .. SLEW_N = 0x3 */
10373 /* .. ==> 0XF8000B5C[23:19] = 0x00000003U */
10374 /* .. ==> MASK : 0x00F80000U VAL : 0x00180000U */
10375 /* .. GTL = 0x0 */
10376 /* .. ==> 0XF8000B5C[26:24] = 0x00000000U */
10377 /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */
10378 /* .. RTERM = 0x0 */
10379 /* .. ==> 0XF8000B5C[31:27] = 0x00000000U */
10380 /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */
10381 /* .. */
10382 EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
10383 /* .. DRIVE_P = 0x1c */
10384 /* .. ==> 0XF8000B60[6:0] = 0x0000001CU */
10385 /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */
10386 /* .. DRIVE_N = 0xc */
10387 /* .. ==> 0XF8000B60[13:7] = 0x0000000CU */
10388 /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */
10389 /* .. SLEW_P = 0x6 */
10390 /* .. ==> 0XF8000B60[18:14] = 0x00000006U */
10391 /* .. ==> MASK : 0x0007C000U VAL : 0x00018000U */
10392 /* .. SLEW_N = 0x1f */
10393 /* .. ==> 0XF8000B60[23:19] = 0x0000001FU */
10394 /* .. ==> MASK : 0x00F80000U VAL : 0x00F80000U */
10395 /* .. GTL = 0x0 */
10396 /* .. ==> 0XF8000B60[26:24] = 0x00000000U */
10397 /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */
10398 /* .. RTERM = 0x0 */
10399 /* .. ==> 0XF8000B60[31:27] = 0x00000000U */
10400 /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */
10401 /* .. */
10402 EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
10403 /* .. DRIVE_P = 0x1c */
10404 /* .. ==> 0XF8000B64[6:0] = 0x0000001CU */
10405 /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */
10406 /* .. DRIVE_N = 0xc */
10407 /* .. ==> 0XF8000B64[13:7] = 0x0000000CU */
10408 /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */
10409 /* .. SLEW_P = 0x6 */
10410 /* .. ==> 0XF8000B64[18:14] = 0x00000006U */
10411 /* .. ==> MASK : 0x0007C000U VAL : 0x00018000U */
10412 /* .. SLEW_N = 0x1f */
10413 /* .. ==> 0XF8000B64[23:19] = 0x0000001FU */
10414 /* .. ==> MASK : 0x00F80000U VAL : 0x00F80000U */
10415 /* .. GTL = 0x0 */
10416 /* .. ==> 0XF8000B64[26:24] = 0x00000000U */
10417 /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */
10418 /* .. RTERM = 0x0 */
10419 /* .. ==> 0XF8000B64[31:27] = 0x00000000U */
10420 /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */
10421 /* .. */
10422 EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
10423 /* .. DRIVE_P = 0x1c */
10424 /* .. ==> 0XF8000B68[6:0] = 0x0000001CU */
10425 /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */
10426 /* .. DRIVE_N = 0xc */
10427 /* .. ==> 0XF8000B68[13:7] = 0x0000000CU */
10428 /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */
10429 /* .. SLEW_P = 0x6 */
10430 /* .. ==> 0XF8000B68[18:14] = 0x00000006U */
10431 /* .. ==> MASK : 0x0007C000U VAL : 0x00018000U */
10432 /* .. SLEW_N = 0x1f */
10433 /* .. ==> 0XF8000B68[23:19] = 0x0000001FU */
10434 /* .. ==> MASK : 0x00F80000U VAL : 0x00F80000U */
10435 /* .. GTL = 0x0 */
10436 /* .. ==> 0XF8000B68[26:24] = 0x00000000U */
10437 /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */
10438 /* .. RTERM = 0x0 */
10439 /* .. ==> 0XF8000B68[31:27] = 0x00000000U */
10440 /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */
10441 /* .. */
10442 EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
10443 /* .. VREF_INT_EN = 0x0 */
10444 /* .. ==> 0XF8000B6C[0:0] = 0x00000000U */
10445 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
10446 /* .. VREF_SEL = 0x0 */
10447 /* .. ==> 0XF8000B6C[4:1] = 0x00000000U */
10448 /* .. ==> MASK : 0x0000001EU VAL : 0x00000000U */
10449 /* .. VREF_EXT_EN = 0x3 */
10450 /* .. ==> 0XF8000B6C[6:5] = 0x00000003U */
10451 /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */
10452 /* .. VREF_PULLUP_EN = 0x0 */
10453 /* .. ==> 0XF8000B6C[8:7] = 0x00000000U */
10454 /* .. ==> MASK : 0x00000180U VAL : 0x00000000U */
10455 /* .. REFIO_EN = 0x1 */
10456 /* .. ==> 0XF8000B6C[9:9] = 0x00000001U */
10457 /* .. ==> MASK : 0x00000200U VAL : 0x00000200U */
10458 /* .. REFIO_PULLUP_EN = 0x0 */
10459 /* .. ==> 0XF8000B6C[12:12] = 0x00000000U */
10460 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
10461 /* .. DRST_B_PULLUP_EN = 0x0 */
10462 /* .. ==> 0XF8000B6C[13:13] = 0x00000000U */
10463 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
10464 /* .. CKE_PULLUP_EN = 0x0 */
10465 /* .. ==> 0XF8000B6C[14:14] = 0x00000000U */
10466 /* .. ==> MASK : 0x00004000U VAL : 0x00000000U */
10467 /* .. */
10468 EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU, 0x00000260U),
10469 /* .. .. START: ASSERT RESET */
10470 /* .. .. RESET = 1 */
10471 /* .. .. ==> 0XF8000B70[0:0] = 0x00000001U */
10472 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
10473 /* .. .. VRN_OUT = 0x1 */
10474 /* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */
10475 /* .. .. ==> MASK : 0x00000020U VAL : 0x00000020U */
10476 /* .. .. */
10477 EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000021U),
10478 /* .. .. FINISH: ASSERT RESET */
10479 /* .. .. START: DEASSERT RESET */
10480 /* .. .. RESET = 0 */
10481 /* .. .. ==> 0XF8000B70[0:0] = 0x00000000U */
10482 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
10483 /* .. .. VRN_OUT = 0x1 */
10484 /* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */
10485 /* .. .. ==> MASK : 0x00000020U VAL : 0x00000020U */
10486 /* .. .. */
10487 EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U),
10488 /* .. .. FINISH: DEASSERT RESET */
10489 /* .. .. RESET = 0x1 */
10490 /* .. .. ==> 0XF8000B70[0:0] = 0x00000001U */
10491 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
10492 /* .. .. ENABLE = 0x1 */
10493 /* .. .. ==> 0XF8000B70[1:1] = 0x00000001U */
10494 /* .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */
10495 /* .. .. VRP_TRI = 0x0 */
10496 /* .. .. ==> 0XF8000B70[2:2] = 0x00000000U */
10497 /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
10498 /* .. .. VRN_TRI = 0x0 */
10499 /* .. .. ==> 0XF8000B70[3:3] = 0x00000000U */
10500 /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
10501 /* .. .. VRP_OUT = 0x0 */
10502 /* .. .. ==> 0XF8000B70[4:4] = 0x00000000U */
10503 /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
10504 /* .. .. VRN_OUT = 0x1 */
10505 /* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */
10506 /* .. .. ==> MASK : 0x00000020U VAL : 0x00000020U */
10507 /* .. .. NREF_OPT1 = 0x0 */
10508 /* .. .. ==> 0XF8000B70[7:6] = 0x00000000U */
10509 /* .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U */
10510 /* .. .. NREF_OPT2 = 0x0 */
10511 /* .. .. ==> 0XF8000B70[10:8] = 0x00000000U */
10512 /* .. .. ==> MASK : 0x00000700U VAL : 0x00000000U */
10513 /* .. .. NREF_OPT4 = 0x1 */
10514 /* .. .. ==> 0XF8000B70[13:11] = 0x00000001U */
10515 /* .. .. ==> MASK : 0x00003800U VAL : 0x00000800U */
10516 /* .. .. PREF_OPT1 = 0x0 */
10517 /* .. .. ==> 0XF8000B70[16:14] = 0x00000000U */
10518 /* .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U */
10519 /* .. .. PREF_OPT2 = 0x0 */
10520 /* .. .. ==> 0XF8000B70[19:17] = 0x00000000U */
10521 /* .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U */
10522 /* .. .. UPDATE_CONTROL = 0x0 */
10523 /* .. .. ==> 0XF8000B70[20:20] = 0x00000000U */
10524 /* .. .. ==> MASK : 0x00100000U VAL : 0x00000000U */
10525 /* .. .. INIT_COMPLETE = 0x0 */
10526 /* .. .. ==> 0XF8000B70[21:21] = 0x00000000U */
10527 /* .. .. ==> MASK : 0x00200000U VAL : 0x00000000U */
10528 /* .. .. TST_CLK = 0x0 */
10529 /* .. .. ==> 0XF8000B70[22:22] = 0x00000000U */
10530 /* .. .. ==> MASK : 0x00400000U VAL : 0x00000000U */
10531 /* .. .. TST_HLN = 0x0 */
10532 /* .. .. ==> 0XF8000B70[23:23] = 0x00000000U */
10533 /* .. .. ==> MASK : 0x00800000U VAL : 0x00000000U */
10534 /* .. .. TST_HLP = 0x0 */
10535 /* .. .. ==> 0XF8000B70[24:24] = 0x00000000U */
10536 /* .. .. ==> MASK : 0x01000000U VAL : 0x00000000U */
10537 /* .. .. TST_RST = 0x0 */
10538 /* .. .. ==> 0XF8000B70[25:25] = 0x00000000U */
10539 /* .. .. ==> MASK : 0x02000000U VAL : 0x00000000U */
10540 /* .. .. INT_DCI_EN = 0x0 */
10541 /* .. .. ==> 0XF8000B70[26:26] = 0x00000000U */
10542 /* .. .. ==> MASK : 0x04000000U VAL : 0x00000000U */
10543 /* .. .. */
10544 EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU, 0x00000823U),
10545 /* .. FINISH: DDRIOB SETTINGS */
10546 /* .. START: MIO PROGRAMMING */
10547 /* .. TRI_ENABLE = 0 */
Michal Simek264065f2016-03-03 13:25:03 +0100[diff] [blame]10548 /* .. ==> 0XF8000700[0:0] = 0x00000000U */
10549 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
10550 /* .. L0_SEL = 0 */
10551 /* .. ==> 0XF8000700[1:1] = 0x00000000U */
10552 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
10553 /* .. L1_SEL = 0 */
10554 /* .. ==> 0XF8000700[2:2] = 0x00000000U */
10555 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
10556 /* .. L2_SEL = 0 */
10557 /* .. ==> 0XF8000700[4:3] = 0x00000000U */
10558 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
10559 /* .. L3_SEL = 0 */
10560 /* .. ==> 0XF8000700[7:5] = 0x00000000U */
10561 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
10562 /* .. Speed = 0 */
10563 /* .. ==> 0XF8000700[8:8] = 0x00000000U */
10564 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
10565 /* .. IO_Type = 3 */
10566 /* .. ==> 0XF8000700[11:9] = 0x00000003U */
10567 /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
10568 /* .. PULLUP = 1 */
10569 /* .. ==> 0XF8000700[12:12] = 0x00000001U */
10570 /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
10571 /* .. DisableRcvr = 0 */
10572 /* .. ==> 0XF8000700[13:13] = 0x00000000U */
10573 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
10574 /* .. */
10575 EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00001600U),
10576 /* .. TRI_ENABLE = 0 */
Nathan Rossi4eeed0e2015-11-24 19:34:09 +1000[diff] [blame]10577 /* .. ==> 0XF8000704[0:0] = 0x00000000U */
10578 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
10579 /* .. L0_SEL = 1 */
10580 /* .. ==> 0XF8000704[1:1] = 0x00000001U */
10581 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
10582 /* .. L1_SEL = 0 */
10583 /* .. ==> 0XF8000704[2:2] = 0x00000000U */
10584 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
10585 /* .. L2_SEL = 0 */
10586 /* .. ==> 0XF8000704[4:3] = 0x00000000U */
10587 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
10588 /* .. L3_SEL = 0 */
10589 /* .. ==> 0XF8000704[7:5] = 0x00000000U */
10590 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
10591 /* .. Speed = 1 */
10592 /* .. ==> 0XF8000704[8:8] = 0x00000001U */
10593 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
10594 /* .. IO_Type = 3 */
10595 /* .. ==> 0XF8000704[11:9] = 0x00000003U */
10596 /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
10597 /* .. PULLUP = 0 */
10598 /* .. ==> 0XF8000704[12:12] = 0x00000000U */
10599 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
10600 /* .. DisableRcvr = 0 */
10601 /* .. ==> 0XF8000704[13:13] = 0x00000000U */
10602 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
10603 /* .. */
10604 EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00000702U),
10605 /* .. TRI_ENABLE = 0 */
10606 /* .. ==> 0XF8000708[0:0] = 0x00000000U */
10607 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
10608 /* .. L0_SEL = 1 */
10609 /* .. ==> 0XF8000708[1:1] = 0x00000001U */
10610 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
10611 /* .. L1_SEL = 0 */
10612 /* .. ==> 0XF8000708[2:2] = 0x00000000U */
10613 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
10614 /* .. L2_SEL = 0 */
10615 /* .. ==> 0XF8000708[4:3] = 0x00000000U */
10616 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
10617 /* .. L3_SEL = 0 */
10618 /* .. ==> 0XF8000708[7:5] = 0x00000000U */
10619 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
10620 /* .. Speed = 1 */
10621 /* .. ==> 0XF8000708[8:8] = 0x00000001U */
10622 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
10623 /* .. IO_Type = 3 */
10624 /* .. ==> 0XF8000708[11:9] = 0x00000003U */
10625 /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
10626 /* .. PULLUP = 0 */
10627 /* .. ==> 0XF8000708[12:12] = 0x00000000U */
10628 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
10629 /* .. DisableRcvr = 0 */
10630 /* .. ==> 0XF8000708[13:13] = 0x00000000U */
10631 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
10632 /* .. */
10633 EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000702U),
10634 /* .. TRI_ENABLE = 0 */
10635 /* .. ==> 0XF800070C[0:0] = 0x00000000U */
10636 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
10637 /* .. L0_SEL = 1 */
10638 /* .. ==> 0XF800070C[1:1] = 0x00000001U */
10639 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
10640 /* .. L1_SEL = 0 */
10641 /* .. ==> 0XF800070C[2:2] = 0x00000000U */
10642 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
10643 /* .. L2_SEL = 0 */
10644 /* .. ==> 0XF800070C[4:3] = 0x00000000U */
10645 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
10646 /* .. L3_SEL = 0 */
10647 /* .. ==> 0XF800070C[7:5] = 0x00000000U */
10648 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
10649 /* .. Speed = 1 */
10650 /* .. ==> 0XF800070C[8:8] = 0x00000001U */
10651 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
10652 /* .. IO_Type = 3 */
10653 /* .. ==> 0XF800070C[11:9] = 0x00000003U */
10654 /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
10655 /* .. PULLUP = 0 */
10656 /* .. ==> 0XF800070C[12:12] = 0x00000000U */
10657 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
10658 /* .. DisableRcvr = 0 */
10659 /* .. ==> 0XF800070C[13:13] = 0x00000000U */
10660 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
10661 /* .. */
10662 EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000702U),
10663 /* .. TRI_ENABLE = 0 */
10664 /* .. ==> 0XF8000710[0:0] = 0x00000000U */
10665 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
10666 /* .. L0_SEL = 1 */
10667 /* .. ==> 0XF8000710[1:1] = 0x00000001U */
10668 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
10669 /* .. L1_SEL = 0 */
10670 /* .. ==> 0XF8000710[2:2] = 0x00000000U */
10671 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
10672 /* .. L2_SEL = 0 */
10673 /* .. ==> 0XF8000710[4:3] = 0x00000000U */
10674 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
10675 /* .. L3_SEL = 0 */
10676 /* .. ==> 0XF8000710[7:5] = 0x00000000U */
10677 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
10678 /* .. Speed = 1 */
10679 /* .. ==> 0XF8000710[8:8] = 0x00000001U */
10680 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
10681 /* .. IO_Type = 3 */
10682 /* .. ==> 0XF8000710[11:9] = 0x00000003U */
10683 /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
10684 /* .. PULLUP = 0 */
10685 /* .. ==> 0XF8000710[12:12] = 0x00000000U */
10686 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
10687 /* .. DisableRcvr = 0 */
10688 /* .. ==> 0XF8000710[13:13] = 0x00000000U */
10689 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
10690 /* .. */
10691 EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000702U),
10692 /* .. TRI_ENABLE = 0 */
10693 /* .. ==> 0XF8000714[0:0] = 0x00000000U */
10694 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
10695 /* .. L0_SEL = 1 */
10696 /* .. ==> 0XF8000714[1:1] = 0x00000001U */
10697 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
10698 /* .. L1_SEL = 0 */
10699 /* .. ==> 0XF8000714[2:2] = 0x00000000U */
10700 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
10701 /* .. L2_SEL = 0 */
10702 /* .. ==> 0XF8000714[4:3] = 0x00000000U */
10703 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
10704 /* .. L3_SEL = 0 */
10705 /* .. ==> 0XF8000714[7:5] = 0x00000000U */
10706 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
10707 /* .. Speed = 1 */
10708 /* .. ==> 0XF8000714[8:8] = 0x00000001U */
10709 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
10710 /* .. IO_Type = 3 */
10711 /* .. ==> 0XF8000714[11:9] = 0x00000003U */
10712 /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
10713 /* .. PULLUP = 0 */
10714 /* .. ==> 0XF8000714[12:12] = 0x00000000U */
10715 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
10716 /* .. DisableRcvr = 0 */
10717 /* .. ==> 0XF8000714[13:13] = 0x00000000U */
10718 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
10719 /* .. */
10720 EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000702U),
10721 /* .. TRI_ENABLE = 0 */
10722 /* .. ==> 0XF8000718[0:0] = 0x00000000U */
10723 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
10724 /* .. L0_SEL = 1 */
10725 /* .. ==> 0XF8000718[1:1] = 0x00000001U */
10726 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
10727 /* .. L1_SEL = 0 */
10728 /* .. ==> 0XF8000718[2:2] = 0x00000000U */
10729 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
10730 /* .. L2_SEL = 0 */
10731 /* .. ==> 0XF8000718[4:3] = 0x00000000U */
10732 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
10733 /* .. L3_SEL = 0 */
10734 /* .. ==> 0XF8000718[7:5] = 0x00000000U */
10735 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
10736 /* .. Speed = 1 */
10737 /* .. ==> 0XF8000718[8:8] = 0x00000001U */
10738 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
10739 /* .. IO_Type = 3 */
10740 /* .. ==> 0XF8000718[11:9] = 0x00000003U */
10741 /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
10742 /* .. PULLUP = 0 */
10743 /* .. ==> 0XF8000718[12:12] = 0x00000000U */
10744 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
10745 /* .. DisableRcvr = 0 */
10746 /* .. ==> 0XF8000718[13:13] = 0x00000000U */
10747 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
10748 /* .. */
10749 EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000702U),
10750 /* .. TRI_ENABLE = 0 */
Michal Simek264065f2016-03-03 13:25:03 +0100[diff] [blame]10751 /* .. ==> 0XF800071C[0:0] = 0x00000000U */
10752 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
10753 /* .. L0_SEL = 0 */
10754 /* .. ==> 0XF800071C[1:1] = 0x00000000U */
10755 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
10756 /* .. L1_SEL = 0 */
10757 /* .. ==> 0XF800071C[2:2] = 0x00000000U */
10758 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
10759 /* .. L2_SEL = 0 */
10760 /* .. ==> 0XF800071C[4:3] = 0x00000000U */
10761 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
10762 /* .. L3_SEL = 0 */
10763 /* .. ==> 0XF800071C[7:5] = 0x00000000U */
10764 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
10765 /* .. Speed = 0 */
10766 /* .. ==> 0XF800071C[8:8] = 0x00000000U */
10767 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
10768 /* .. IO_Type = 3 */
10769 /* .. ==> 0XF800071C[11:9] = 0x00000003U */
10770 /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
10771 /* .. PULLUP = 0 */
10772 /* .. ==> 0XF800071C[12:12] = 0x00000000U */
10773 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
10774 /* .. DisableRcvr = 0 */
10775 /* .. ==> 0XF800071C[13:13] = 0x00000000U */
10776 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
10777 /* .. */
10778 EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000600U),
10779 /* .. TRI_ENABLE = 0 */
10780 /* .. ==> 0XF8000720[0:0] = 0x00000000U */
10781 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
10782 /* .. L0_SEL = 1 */
10783 /* .. ==> 0XF8000720[1:1] = 0x00000001U */
10784 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
10785 /* .. L1_SEL = 0 */
10786 /* .. ==> 0XF8000720[2:2] = 0x00000000U */
10787 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
10788 /* .. L2_SEL = 0 */
10789 /* .. ==> 0XF8000720[4:3] = 0x00000000U */
10790 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
10791 /* .. L3_SEL = 0 */
10792 /* .. ==> 0XF8000720[7:5] = 0x00000000U */
10793 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
10794 /* .. Speed = 1 */
10795 /* .. ==> 0XF8000720[8:8] = 0x00000001U */
10796 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
10797 /* .. IO_Type = 3 */
10798 /* .. ==> 0XF8000720[11:9] = 0x00000003U */
10799 /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
10800 /* .. PULLUP = 0 */
10801 /* .. ==> 0XF8000720[12:12] = 0x00000000U */
10802 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
10803 /* .. DisableRcvr = 0 */
10804 /* .. ==> 0XF8000720[13:13] = 0x00000000U */
10805 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
10806 /* .. */
10807 EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000702U),
10808 /* .. TRI_ENABLE = 0 */
10809 /* .. ==> 0XF8000724[0:0] = 0x00000000U */
10810 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
10811 /* .. L0_SEL = 0 */
10812 /* .. ==> 0XF8000724[1:1] = 0x00000000U */
10813 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
10814 /* .. L1_SEL = 0 */
10815 /* .. ==> 0XF8000724[2:2] = 0x00000000U */
10816 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
10817 /* .. L2_SEL = 0 */
10818 /* .. ==> 0XF8000724[4:3] = 0x00000000U */
10819 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
10820 /* .. L3_SEL = 0 */
10821 /* .. ==> 0XF8000724[7:5] = 0x00000000U */
10822 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
10823 /* .. Speed = 0 */
10824 /* .. ==> 0XF8000724[8:8] = 0x00000000U */
10825 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
10826 /* .. IO_Type = 3 */
10827 /* .. ==> 0XF8000724[11:9] = 0x00000003U */
10828 /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
10829 /* .. PULLUP = 1 */
10830 /* .. ==> 0XF8000724[12:12] = 0x00000001U */
10831 /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
10832 /* .. DisableRcvr = 0 */
10833 /* .. ==> 0XF8000724[13:13] = 0x00000000U */
10834 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
10835 /* .. */
10836 EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00001600U),
10837 /* .. TRI_ENABLE = 0 */
10838 /* .. ==> 0XF8000728[0:0] = 0x00000000U */
10839 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
10840 /* .. L0_SEL = 0 */
10841 /* .. ==> 0XF8000728[1:1] = 0x00000000U */
10842 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
10843 /* .. L1_SEL = 0 */
10844 /* .. ==> 0XF8000728[2:2] = 0x00000000U */
10845 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
10846 /* .. L2_SEL = 0 */
10847 /* .. ==> 0XF8000728[4:3] = 0x00000000U */
10848 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
10849 /* .. L3_SEL = 0 */
10850 /* .. ==> 0XF8000728[7:5] = 0x00000000U */
10851 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
10852 /* .. Speed = 0 */
10853 /* .. ==> 0XF8000728[8:8] = 0x00000000U */
10854 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
10855 /* .. IO_Type = 3 */
10856 /* .. ==> 0XF8000728[11:9] = 0x00000003U */
10857 /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
10858 /* .. PULLUP = 1 */
10859 /* .. ==> 0XF8000728[12:12] = 0x00000001U */
10860 /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
10861 /* .. DisableRcvr = 0 */
10862 /* .. ==> 0XF8000728[13:13] = 0x00000000U */
10863 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
10864 /* .. */
10865 EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x00001600U),
10866 /* .. TRI_ENABLE = 0 */
10867 /* .. ==> 0XF800072C[0:0] = 0x00000000U */
10868 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
10869 /* .. L0_SEL = 0 */
10870 /* .. ==> 0XF800072C[1:1] = 0x00000000U */
10871 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
10872 /* .. L1_SEL = 0 */
10873 /* .. ==> 0XF800072C[2:2] = 0x00000000U */
10874 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
10875 /* .. L2_SEL = 0 */
10876 /* .. ==> 0XF800072C[4:3] = 0x00000000U */
10877 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
10878 /* .. L3_SEL = 0 */
10879 /* .. ==> 0XF800072C[7:5] = 0x00000000U */
10880 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
10881 /* .. Speed = 0 */
10882 /* .. ==> 0XF800072C[8:8] = 0x00000000U */
10883 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
10884 /* .. IO_Type = 3 */
10885 /* .. ==> 0XF800072C[11:9] = 0x00000003U */
10886 /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
10887 /* .. PULLUP = 1 */
10888 /* .. ==> 0XF800072C[12:12] = 0x00000001U */
10889 /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
10890 /* .. DisableRcvr = 0 */
10891 /* .. ==> 0XF800072C[13:13] = 0x00000000U */
10892 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
10893 /* .. */
10894 EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x00001600U),
10895 /* .. TRI_ENABLE = 0 */
10896 /* .. ==> 0XF8000730[0:0] = 0x00000000U */
10897 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
10898 /* .. L0_SEL = 0 */
10899 /* .. ==> 0XF8000730[1:1] = 0x00000000U */
10900 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
10901 /* .. L1_SEL = 0 */
10902 /* .. ==> 0XF8000730[2:2] = 0x00000000U */
10903 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
10904 /* .. L2_SEL = 0 */
10905 /* .. ==> 0XF8000730[4:3] = 0x00000000U */
10906 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
10907 /* .. L3_SEL = 0 */
10908 /* .. ==> 0XF8000730[7:5] = 0x00000000U */
10909 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
10910 /* .. Speed = 0 */
10911 /* .. ==> 0XF8000730[8:8] = 0x00000000U */
10912 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
10913 /* .. IO_Type = 3 */
10914 /* .. ==> 0XF8000730[11:9] = 0x00000003U */
10915 /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
10916 /* .. PULLUP = 1 */
10917 /* .. ==> 0XF8000730[12:12] = 0x00000001U */
10918 /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
10919 /* .. DisableRcvr = 0 */
10920 /* .. ==> 0XF8000730[13:13] = 0x00000000U */
10921 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
10922 /* .. */
10923 EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x00001600U),
10924 /* .. TRI_ENABLE = 0 */
10925 /* .. ==> 0XF8000734[0:0] = 0x00000000U */
10926 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
10927 /* .. L0_SEL = 0 */
10928 /* .. ==> 0XF8000734[1:1] = 0x00000000U */
10929 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
10930 /* .. L1_SEL = 0 */
10931 /* .. ==> 0XF8000734[2:2] = 0x00000000U */
10932 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
10933 /* .. L2_SEL = 0 */
10934 /* .. ==> 0XF8000734[4:3] = 0x00000000U */
10935 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
10936 /* .. L3_SEL = 0 */
10937 /* .. ==> 0XF8000734[7:5] = 0x00000000U */
10938 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
10939 /* .. Speed = 0 */
10940 /* .. ==> 0XF8000734[8:8] = 0x00000000U */
10941 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
10942 /* .. IO_Type = 3 */
10943 /* .. ==> 0XF8000734[11:9] = 0x00000003U */
10944 /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
10945 /* .. PULLUP = 1 */
10946 /* .. ==> 0XF8000734[12:12] = 0x00000001U */
10947 /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
10948 /* .. DisableRcvr = 0 */
10949 /* .. ==> 0XF8000734[13:13] = 0x00000000U */
10950 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
10951 /* .. */
10952 EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x00001600U),
10953 /* .. TRI_ENABLE = 0 */
10954 /* .. ==> 0XF8000738[0:0] = 0x00000000U */
10955 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
10956 /* .. L0_SEL = 0 */
10957 /* .. ==> 0XF8000738[1:1] = 0x00000000U */
10958 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
10959 /* .. L1_SEL = 0 */
10960 /* .. ==> 0XF8000738[2:2] = 0x00000000U */
10961 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
10962 /* .. L2_SEL = 0 */
10963 /* .. ==> 0XF8000738[4:3] = 0x00000000U */
10964 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
10965 /* .. L3_SEL = 0 */
10966 /* .. ==> 0XF8000738[7:5] = 0x00000000U */
10967 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
10968 /* .. Speed = 0 */
10969 /* .. ==> 0XF8000738[8:8] = 0x00000000U */
10970 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
10971 /* .. IO_Type = 3 */
10972 /* .. ==> 0XF8000738[11:9] = 0x00000003U */
10973 /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
10974 /* .. PULLUP = 1 */
10975 /* .. ==> 0XF8000738[12:12] = 0x00000001U */
10976 /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
10977 /* .. DisableRcvr = 0 */
10978 /* .. ==> 0XF8000738[13:13] = 0x00000000U */
10979 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
10980 /* .. */
10981 EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x00001600U),
10982 /* .. TRI_ENABLE = 0 */
10983 /* .. ==> 0XF800073C[0:0] = 0x00000000U */
10984 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
10985 /* .. L0_SEL = 0 */
10986 /* .. ==> 0XF800073C[1:1] = 0x00000000U */
10987 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
10988 /* .. L1_SEL = 0 */
10989 /* .. ==> 0XF800073C[2:2] = 0x00000000U */
10990 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
10991 /* .. L2_SEL = 0 */
10992 /* .. ==> 0XF800073C[4:3] = 0x00000000U */
10993 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
10994 /* .. L3_SEL = 0 */
10995 /* .. ==> 0XF800073C[7:5] = 0x00000000U */
10996 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
10997 /* .. Speed = 0 */
10998 /* .. ==> 0XF800073C[8:8] = 0x00000000U */
10999 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
11000 /* .. IO_Type = 3 */
11001 /* .. ==> 0XF800073C[11:9] = 0x00000003U */
11002 /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
11003 /* .. PULLUP = 1 */
11004 /* .. ==> 0XF800073C[12:12] = 0x00000001U */
11005 /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
11006 /* .. DisableRcvr = 0 */
11007 /* .. ==> 0XF800073C[13:13] = 0x00000000U */
11008 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
11009 /* .. */
11010 EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x00001600U),
11011 /* .. TRI_ENABLE = 0 */
Nathan Rossi4eeed0e2015-11-24 19:34:09 +1000[diff] [blame]11012 /* .. ==> 0XF8000740[0:0] = 0x00000000U */
11013 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
11014 /* .. L0_SEL = 1 */
11015 /* .. ==> 0XF8000740[1:1] = 0x00000001U */
11016 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
11017 /* .. L1_SEL = 0 */
11018 /* .. ==> 0XF8000740[2:2] = 0x00000000U */
11019 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
11020 /* .. L2_SEL = 0 */
11021 /* .. ==> 0XF8000740[4:3] = 0x00000000U */
11022 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
11023 /* .. L3_SEL = 0 */
11024 /* .. ==> 0XF8000740[7:5] = 0x00000000U */
11025 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
11026 /* .. Speed = 1 */
11027 /* .. ==> 0XF8000740[8:8] = 0x00000001U */
11028 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
11029 /* .. IO_Type = 4 */
11030 /* .. ==> 0XF8000740[11:9] = 0x00000004U */
11031 /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
11032 /* .. PULLUP = 0 */
11033 /* .. ==> 0XF8000740[12:12] = 0x00000000U */
11034 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
11035 /* .. DisableRcvr = 1 */
11036 /* .. ==> 0XF8000740[13:13] = 0x00000001U */
11037 /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
11038 /* .. */
11039 EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x00002902U),
11040 /* .. TRI_ENABLE = 0 */
11041 /* .. ==> 0XF8000744[0:0] = 0x00000000U */
11042 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
11043 /* .. L0_SEL = 1 */
11044 /* .. ==> 0XF8000744[1:1] = 0x00000001U */
11045 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
11046 /* .. L1_SEL = 0 */
11047 /* .. ==> 0XF8000744[2:2] = 0x00000000U */
11048 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
11049 /* .. L2_SEL = 0 */
11050 /* .. ==> 0XF8000744[4:3] = 0x00000000U */
11051 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
11052 /* .. L3_SEL = 0 */
11053 /* .. ==> 0XF8000744[7:5] = 0x00000000U */
11054 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
11055 /* .. Speed = 1 */
11056 /* .. ==> 0XF8000744[8:8] = 0x00000001U */
11057 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
11058 /* .. IO_Type = 4 */
11059 /* .. ==> 0XF8000744[11:9] = 0x00000004U */
11060 /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
11061 /* .. PULLUP = 0 */
11062 /* .. ==> 0XF8000744[12:12] = 0x00000000U */
11063 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
11064 /* .. DisableRcvr = 1 */
11065 /* .. ==> 0XF8000744[13:13] = 0x00000001U */
11066 /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
11067 /* .. */
11068 EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x00002902U),
11069 /* .. TRI_ENABLE = 0 */
11070 /* .. ==> 0XF8000748[0:0] = 0x00000000U */
11071 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
11072 /* .. L0_SEL = 1 */
11073 /* .. ==> 0XF8000748[1:1] = 0x00000001U */
11074 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
11075 /* .. L1_SEL = 0 */
11076 /* .. ==> 0XF8000748[2:2] = 0x00000000U */
11077 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
11078 /* .. L2_SEL = 0 */
11079 /* .. ==> 0XF8000748[4:3] = 0x00000000U */
11080 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
11081 /* .. L3_SEL = 0 */
11082 /* .. ==> 0XF8000748[7:5] = 0x00000000U */
11083 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
11084 /* .. Speed = 1 */
11085 /* .. ==> 0XF8000748[8:8] = 0x00000001U */
11086 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
11087 /* .. IO_Type = 4 */
11088 /* .. ==> 0XF8000748[11:9] = 0x00000004U */
11089 /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
11090 /* .. PULLUP = 0 */
11091 /* .. ==> 0XF8000748[12:12] = 0x00000000U */
11092 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
11093 /* .. DisableRcvr = 1 */
11094 /* .. ==> 0XF8000748[13:13] = 0x00000001U */
11095 /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
11096 /* .. */
11097 EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00002902U),
11098 /* .. TRI_ENABLE = 0 */
11099 /* .. ==> 0XF800074C[0:0] = 0x00000000U */
11100 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
11101 /* .. L0_SEL = 1 */
11102 /* .. ==> 0XF800074C[1:1] = 0x00000001U */
11103 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
11104 /* .. L1_SEL = 0 */
11105 /* .. ==> 0XF800074C[2:2] = 0x00000000U */
11106 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
11107 /* .. L2_SEL = 0 */
11108 /* .. ==> 0XF800074C[4:3] = 0x00000000U */
11109 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
11110 /* .. L3_SEL = 0 */
11111 /* .. ==> 0XF800074C[7:5] = 0x00000000U */
11112 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
11113 /* .. Speed = 1 */
11114 /* .. ==> 0XF800074C[8:8] = 0x00000001U */
11115 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
11116 /* .. IO_Type = 4 */
11117 /* .. ==> 0XF800074C[11:9] = 0x00000004U */
11118 /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
11119 /* .. PULLUP = 0 */
11120 /* .. ==> 0XF800074C[12:12] = 0x00000000U */
11121 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
11122 /* .. DisableRcvr = 1 */
11123 /* .. ==> 0XF800074C[13:13] = 0x00000001U */
11124 /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
11125 /* .. */
11126 EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00002902U),
11127 /* .. TRI_ENABLE = 0 */
11128 /* .. ==> 0XF8000750[0:0] = 0x00000000U */
11129 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
11130 /* .. L0_SEL = 1 */
11131 /* .. ==> 0XF8000750[1:1] = 0x00000001U */
11132 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
11133 /* .. L1_SEL = 0 */
11134 /* .. ==> 0XF8000750[2:2] = 0x00000000U */
11135 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
11136 /* .. L2_SEL = 0 */
11137 /* .. ==> 0XF8000750[4:3] = 0x00000000U */
11138 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
11139 /* .. L3_SEL = 0 */
11140 /* .. ==> 0XF8000750[7:5] = 0x00000000U */
11141 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
11142 /* .. Speed = 1 */
11143 /* .. ==> 0XF8000750[8:8] = 0x00000001U */
11144 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
11145 /* .. IO_Type = 4 */
11146 /* .. ==> 0XF8000750[11:9] = 0x00000004U */
11147 /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
11148 /* .. PULLUP = 0 */
11149 /* .. ==> 0XF8000750[12:12] = 0x00000000U */
11150 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
11151 /* .. DisableRcvr = 1 */
11152 /* .. ==> 0XF8000750[13:13] = 0x00000001U */
11153 /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
11154 /* .. */
11155 EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00002902U),
11156 /* .. TRI_ENABLE = 0 */
11157 /* .. ==> 0XF8000754[0:0] = 0x00000000U */
11158 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
11159 /* .. L0_SEL = 1 */
11160 /* .. ==> 0XF8000754[1:1] = 0x00000001U */
11161 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
11162 /* .. L1_SEL = 0 */
11163 /* .. ==> 0XF8000754[2:2] = 0x00000000U */
11164 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
11165 /* .. L2_SEL = 0 */
11166 /* .. ==> 0XF8000754[4:3] = 0x00000000U */
11167 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
11168 /* .. L3_SEL = 0 */
11169 /* .. ==> 0XF8000754[7:5] = 0x00000000U */
11170 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
11171 /* .. Speed = 1 */
11172 /* .. ==> 0XF8000754[8:8] = 0x00000001U */
11173 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
11174 /* .. IO_Type = 4 */
11175 /* .. ==> 0XF8000754[11:9] = 0x00000004U */
11176 /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
11177 /* .. PULLUP = 0 */
11178 /* .. ==> 0XF8000754[12:12] = 0x00000000U */
11179 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
11180 /* .. DisableRcvr = 1 */
11181 /* .. ==> 0XF8000754[13:13] = 0x00000001U */
11182 /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
11183 /* .. */
11184 EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00002902U),
11185 /* .. TRI_ENABLE = 1 */
11186 /* .. ==> 0XF8000758[0:0] = 0x00000001U */
11187 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
11188 /* .. L0_SEL = 1 */
11189 /* .. ==> 0XF8000758[1:1] = 0x00000001U */
11190 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
11191 /* .. L1_SEL = 0 */
11192 /* .. ==> 0XF8000758[2:2] = 0x00000000U */
11193 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
11194 /* .. L2_SEL = 0 */
11195 /* .. ==> 0XF8000758[4:3] = 0x00000000U */
11196 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
11197 /* .. L3_SEL = 0 */
11198 /* .. ==> 0XF8000758[7:5] = 0x00000000U */
11199 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
11200 /* .. Speed = 1 */
11201 /* .. ==> 0XF8000758[8:8] = 0x00000001U */
11202 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
11203 /* .. IO_Type = 4 */
11204 /* .. ==> 0XF8000758[11:9] = 0x00000004U */
11205 /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
11206 /* .. PULLUP = 0 */
11207 /* .. ==> 0XF8000758[12:12] = 0x00000000U */
11208 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
11209 /* .. DisableRcvr = 0 */
11210 /* .. ==> 0XF8000758[13:13] = 0x00000000U */
11211 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
11212 /* .. */
11213 EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00000903U),
11214 /* .. TRI_ENABLE = 1 */
11215 /* .. ==> 0XF800075C[0:0] = 0x00000001U */
11216 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
11217 /* .. L0_SEL = 1 */
11218 /* .. ==> 0XF800075C[1:1] = 0x00000001U */
11219 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
11220 /* .. L1_SEL = 0 */
11221 /* .. ==> 0XF800075C[2:2] = 0x00000000U */
11222 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
11223 /* .. L2_SEL = 0 */
11224 /* .. ==> 0XF800075C[4:3] = 0x00000000U */
11225 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
11226 /* .. L3_SEL = 0 */
11227 /* .. ==> 0XF800075C[7:5] = 0x00000000U */
11228 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
11229 /* .. Speed = 1 */
11230 /* .. ==> 0XF800075C[8:8] = 0x00000001U */
11231 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
11232 /* .. IO_Type = 4 */
11233 /* .. ==> 0XF800075C[11:9] = 0x00000004U */
11234 /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
11235 /* .. PULLUP = 0 */
11236 /* .. ==> 0XF800075C[12:12] = 0x00000000U */
11237 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
11238 /* .. DisableRcvr = 0 */
11239 /* .. ==> 0XF800075C[13:13] = 0x00000000U */
11240 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
11241 /* .. */
11242 EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00000903U),
11243 /* .. TRI_ENABLE = 1 */
11244 /* .. ==> 0XF8000760[0:0] = 0x00000001U */
11245 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
11246 /* .. L0_SEL = 1 */
11247 /* .. ==> 0XF8000760[1:1] = 0x00000001U */
11248 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
11249 /* .. L1_SEL = 0 */
11250 /* .. ==> 0XF8000760[2:2] = 0x00000000U */
11251 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
11252 /* .. L2_SEL = 0 */
11253 /* .. ==> 0XF8000760[4:3] = 0x00000000U */
11254 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
11255 /* .. L3_SEL = 0 */
11256 /* .. ==> 0XF8000760[7:5] = 0x00000000U */
11257 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
11258 /* .. Speed = 1 */
11259 /* .. ==> 0XF8000760[8:8] = 0x00000001U */
11260 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
11261 /* .. IO_Type = 4 */
11262 /* .. ==> 0XF8000760[11:9] = 0x00000004U */
11263 /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
11264 /* .. PULLUP = 0 */
11265 /* .. ==> 0XF8000760[12:12] = 0x00000000U */
11266 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
11267 /* .. DisableRcvr = 0 */
11268 /* .. ==> 0XF8000760[13:13] = 0x00000000U */
11269 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
11270 /* .. */
11271 EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00000903U),
11272 /* .. TRI_ENABLE = 1 */
11273 /* .. ==> 0XF8000764[0:0] = 0x00000001U */
11274 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
11275 /* .. L0_SEL = 1 */
11276 /* .. ==> 0XF8000764[1:1] = 0x00000001U */
11277 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
11278 /* .. L1_SEL = 0 */
11279 /* .. ==> 0XF8000764[2:2] = 0x00000000U */
11280 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
11281 /* .. L2_SEL = 0 */
11282 /* .. ==> 0XF8000764[4:3] = 0x00000000U */
11283 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
11284 /* .. L3_SEL = 0 */
11285 /* .. ==> 0XF8000764[7:5] = 0x00000000U */
11286 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
11287 /* .. Speed = 1 */
11288 /* .. ==> 0XF8000764[8:8] = 0x00000001U */
11289 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
11290 /* .. IO_Type = 4 */
11291 /* .. ==> 0XF8000764[11:9] = 0x00000004U */
11292 /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
11293 /* .. PULLUP = 0 */
11294 /* .. ==> 0XF8000764[12:12] = 0x00000000U */
11295 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
11296 /* .. DisableRcvr = 0 */
11297 /* .. ==> 0XF8000764[13:13] = 0x00000000U */
11298 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
11299 /* .. */
11300 EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00000903U),
11301 /* .. TRI_ENABLE = 1 */
11302 /* .. ==> 0XF8000768[0:0] = 0x00000001U */
11303 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
11304 /* .. L0_SEL = 1 */
11305 /* .. ==> 0XF8000768[1:1] = 0x00000001U */
11306 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
11307 /* .. L1_SEL = 0 */
11308 /* .. ==> 0XF8000768[2:2] = 0x00000000U */
11309 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
11310 /* .. L2_SEL = 0 */
11311 /* .. ==> 0XF8000768[4:3] = 0x00000000U */
11312 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
11313 /* .. L3_SEL = 0 */
11314 /* .. ==> 0XF8000768[7:5] = 0x00000000U */
11315 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
11316 /* .. Speed = 1 */
11317 /* .. ==> 0XF8000768[8:8] = 0x00000001U */
11318 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
11319 /* .. IO_Type = 4 */
11320 /* .. ==> 0XF8000768[11:9] = 0x00000004U */
11321 /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
11322 /* .. PULLUP = 0 */
11323 /* .. ==> 0XF8000768[12:12] = 0x00000000U */
11324 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
11325 /* .. DisableRcvr = 0 */
11326 /* .. ==> 0XF8000768[13:13] = 0x00000000U */
11327 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
11328 /* .. */
11329 EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00000903U),
11330 /* .. TRI_ENABLE = 1 */
11331 /* .. ==> 0XF800076C[0:0] = 0x00000001U */
11332 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
11333 /* .. L0_SEL = 1 */
11334 /* .. ==> 0XF800076C[1:1] = 0x00000001U */
11335 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
11336 /* .. L1_SEL = 0 */
11337 /* .. ==> 0XF800076C[2:2] = 0x00000000U */
11338 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
11339 /* .. L2_SEL = 0 */
11340 /* .. ==> 0XF800076C[4:3] = 0x00000000U */
11341 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
11342 /* .. L3_SEL = 0 */
11343 /* .. ==> 0XF800076C[7:5] = 0x00000000U */
11344 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
11345 /* .. Speed = 1 */
11346 /* .. ==> 0XF800076C[8:8] = 0x00000001U */
11347 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
11348 /* .. IO_Type = 4 */
11349 /* .. ==> 0XF800076C[11:9] = 0x00000004U */
11350 /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
11351 /* .. PULLUP = 0 */
11352 /* .. ==> 0XF800076C[12:12] = 0x00000000U */
11353 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
11354 /* .. DisableRcvr = 0 */
11355 /* .. ==> 0XF800076C[13:13] = 0x00000000U */
11356 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
11357 /* .. */
11358 EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00000903U),
11359 /* .. TRI_ENABLE = 0 */
11360 /* .. ==> 0XF8000770[0:0] = 0x00000000U */
11361 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
11362 /* .. L0_SEL = 0 */
11363 /* .. ==> 0XF8000770[1:1] = 0x00000000U */
11364 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
11365 /* .. L1_SEL = 1 */
11366 /* .. ==> 0XF8000770[2:2] = 0x00000001U */
11367 /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
11368 /* .. L2_SEL = 0 */
11369 /* .. ==> 0XF8000770[4:3] = 0x00000000U */
11370 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
11371 /* .. L3_SEL = 0 */
11372 /* .. ==> 0XF8000770[7:5] = 0x00000000U */
11373 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
11374 /* .. Speed = 1 */
11375 /* .. ==> 0XF8000770[8:8] = 0x00000001U */
11376 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
11377 /* .. IO_Type = 1 */
11378 /* .. ==> 0XF8000770[11:9] = 0x00000001U */
11379 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
11380 /* .. PULLUP = 0 */
11381 /* .. ==> 0XF8000770[12:12] = 0x00000000U */
11382 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
11383 /* .. DisableRcvr = 0 */
11384 /* .. ==> 0XF8000770[13:13] = 0x00000000U */
11385 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
11386 /* .. */
11387 EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00000304U),
11388 /* .. TRI_ENABLE = 1 */
11389 /* .. ==> 0XF8000774[0:0] = 0x00000001U */
11390 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
11391 /* .. L0_SEL = 0 */
11392 /* .. ==> 0XF8000774[1:1] = 0x00000000U */
11393 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
11394 /* .. L1_SEL = 1 */
11395 /* .. ==> 0XF8000774[2:2] = 0x00000001U */
11396 /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
11397 /* .. L2_SEL = 0 */
11398 /* .. ==> 0XF8000774[4:3] = 0x00000000U */
11399 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
11400 /* .. L3_SEL = 0 */
11401 /* .. ==> 0XF8000774[7:5] = 0x00000000U */
11402 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
11403 /* .. Speed = 1 */
11404 /* .. ==> 0XF8000774[8:8] = 0x00000001U */
11405 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
11406 /* .. IO_Type = 1 */
11407 /* .. ==> 0XF8000774[11:9] = 0x00000001U */
11408 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
11409 /* .. PULLUP = 0 */
11410 /* .. ==> 0XF8000774[12:12] = 0x00000000U */
11411 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
11412 /* .. DisableRcvr = 0 */
11413 /* .. ==> 0XF8000774[13:13] = 0x00000000U */
11414 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
11415 /* .. */
11416 EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00000305U),
11417 /* .. TRI_ENABLE = 0 */
11418 /* .. ==> 0XF8000778[0:0] = 0x00000000U */
11419 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
11420 /* .. L0_SEL = 0 */
11421 /* .. ==> 0XF8000778[1:1] = 0x00000000U */
11422 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
11423 /* .. L1_SEL = 1 */
11424 /* .. ==> 0XF8000778[2:2] = 0x00000001U */
11425 /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
11426 /* .. L2_SEL = 0 */
11427 /* .. ==> 0XF8000778[4:3] = 0x00000000U */
11428 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
11429 /* .. L3_SEL = 0 */
11430 /* .. ==> 0XF8000778[7:5] = 0x00000000U */
11431 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
11432 /* .. Speed = 1 */
11433 /* .. ==> 0XF8000778[8:8] = 0x00000001U */
11434 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
11435 /* .. IO_Type = 1 */
11436 /* .. ==> 0XF8000778[11:9] = 0x00000001U */
11437 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
11438 /* .. PULLUP = 0 */
11439 /* .. ==> 0XF8000778[12:12] = 0x00000000U */
11440 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
11441 /* .. DisableRcvr = 0 */
11442 /* .. ==> 0XF8000778[13:13] = 0x00000000U */
11443 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
11444 /* .. */
11445 EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00000304U),
11446 /* .. TRI_ENABLE = 1 */
11447 /* .. ==> 0XF800077C[0:0] = 0x00000001U */
11448 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
11449 /* .. L0_SEL = 0 */
11450 /* .. ==> 0XF800077C[1:1] = 0x00000000U */
11451 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
11452 /* .. L1_SEL = 1 */
11453 /* .. ==> 0XF800077C[2:2] = 0x00000001U */
11454 /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
11455 /* .. L2_SEL = 0 */
11456 /* .. ==> 0XF800077C[4:3] = 0x00000000U */
11457 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
11458 /* .. L3_SEL = 0 */
11459 /* .. ==> 0XF800077C[7:5] = 0x00000000U */
11460 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
11461 /* .. Speed = 1 */
11462 /* .. ==> 0XF800077C[8:8] = 0x00000001U */
11463 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
11464 /* .. IO_Type = 1 */
11465 /* .. ==> 0XF800077C[11:9] = 0x00000001U */
11466 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
11467 /* .. PULLUP = 0 */
11468 /* .. ==> 0XF800077C[12:12] = 0x00000000U */
11469 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
11470 /* .. DisableRcvr = 0 */
11471 /* .. ==> 0XF800077C[13:13] = 0x00000000U */
11472 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
11473 /* .. */
11474 EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00000305U),
11475 /* .. TRI_ENABLE = 0 */
11476 /* .. ==> 0XF8000780[0:0] = 0x00000000U */
11477 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
11478 /* .. L0_SEL = 0 */
11479 /* .. ==> 0XF8000780[1:1] = 0x00000000U */
11480 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
11481 /* .. L1_SEL = 1 */
11482 /* .. ==> 0XF8000780[2:2] = 0x00000001U */
11483 /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
11484 /* .. L2_SEL = 0 */
11485 /* .. ==> 0XF8000780[4:3] = 0x00000000U */
11486 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
11487 /* .. L3_SEL = 0 */
11488 /* .. ==> 0XF8000780[7:5] = 0x00000000U */
11489 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
11490 /* .. Speed = 1 */
11491 /* .. ==> 0XF8000780[8:8] = 0x00000001U */
11492 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
11493 /* .. IO_Type = 1 */
11494 /* .. ==> 0XF8000780[11:9] = 0x00000001U */
11495 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
11496 /* .. PULLUP = 0 */
11497 /* .. ==> 0XF8000780[12:12] = 0x00000000U */
11498 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
11499 /* .. DisableRcvr = 0 */
11500 /* .. ==> 0XF8000780[13:13] = 0x00000000U */
11501 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
11502 /* .. */
11503 EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00000304U),
11504 /* .. TRI_ENABLE = 0 */
11505 /* .. ==> 0XF8000784[0:0] = 0x00000000U */
11506 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
11507 /* .. L0_SEL = 0 */
11508 /* .. ==> 0XF8000784[1:1] = 0x00000000U */
11509 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
11510 /* .. L1_SEL = 1 */
11511 /* .. ==> 0XF8000784[2:2] = 0x00000001U */
11512 /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
11513 /* .. L2_SEL = 0 */
11514 /* .. ==> 0XF8000784[4:3] = 0x00000000U */
11515 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
11516 /* .. L3_SEL = 0 */
11517 /* .. ==> 0XF8000784[7:5] = 0x00000000U */
11518 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
11519 /* .. Speed = 1 */
11520 /* .. ==> 0XF8000784[8:8] = 0x00000001U */
11521 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
11522 /* .. IO_Type = 1 */
11523 /* .. ==> 0XF8000784[11:9] = 0x00000001U */
11524 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
11525 /* .. PULLUP = 0 */
11526 /* .. ==> 0XF8000784[12:12] = 0x00000000U */
11527 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
11528 /* .. DisableRcvr = 0 */
11529 /* .. ==> 0XF8000784[13:13] = 0x00000000U */
11530 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
11531 /* .. */
11532 EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00000304U),
11533 /* .. TRI_ENABLE = 0 */
11534 /* .. ==> 0XF8000788[0:0] = 0x00000000U */
11535 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
11536 /* .. L0_SEL = 0 */
11537 /* .. ==> 0XF8000788[1:1] = 0x00000000U */
11538 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
11539 /* .. L1_SEL = 1 */
11540 /* .. ==> 0XF8000788[2:2] = 0x00000001U */
11541 /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
11542 /* .. L2_SEL = 0 */
11543 /* .. ==> 0XF8000788[4:3] = 0x00000000U */
11544 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
11545 /* .. L3_SEL = 0 */
11546 /* .. ==> 0XF8000788[7:5] = 0x00000000U */
11547 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
11548 /* .. Speed = 1 */
11549 /* .. ==> 0XF8000788[8:8] = 0x00000001U */
11550 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
11551 /* .. IO_Type = 1 */
11552 /* .. ==> 0XF8000788[11:9] = 0x00000001U */
11553 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
11554 /* .. PULLUP = 0 */
11555 /* .. ==> 0XF8000788[12:12] = 0x00000000U */
11556 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
11557 /* .. DisableRcvr = 0 */
11558 /* .. ==> 0XF8000788[13:13] = 0x00000000U */
11559 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
11560 /* .. */
11561 EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00000304U),
11562 /* .. TRI_ENABLE = 0 */
11563 /* .. ==> 0XF800078C[0:0] = 0x00000000U */
11564 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
11565 /* .. L0_SEL = 0 */
11566 /* .. ==> 0XF800078C[1:1] = 0x00000000U */
11567 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
11568 /* .. L1_SEL = 1 */
11569 /* .. ==> 0XF800078C[2:2] = 0x00000001U */
11570 /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
11571 /* .. L2_SEL = 0 */
11572 /* .. ==> 0XF800078C[4:3] = 0x00000000U */
11573 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
11574 /* .. L3_SEL = 0 */
11575 /* .. ==> 0XF800078C[7:5] = 0x00000000U */
11576 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
11577 /* .. Speed = 1 */
11578 /* .. ==> 0XF800078C[8:8] = 0x00000001U */
11579 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
11580 /* .. IO_Type = 1 */
11581 /* .. ==> 0XF800078C[11:9] = 0x00000001U */
11582 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
11583 /* .. PULLUP = 0 */
11584 /* .. ==> 0XF800078C[12:12] = 0x00000000U */
11585 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
11586 /* .. DisableRcvr = 0 */
11587 /* .. ==> 0XF800078C[13:13] = 0x00000000U */
11588 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
11589 /* .. */
11590 EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00000304U),
11591 /* .. TRI_ENABLE = 1 */
11592 /* .. ==> 0XF8000790[0:0] = 0x00000001U */
11593 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
11594 /* .. L0_SEL = 0 */
11595 /* .. ==> 0XF8000790[1:1] = 0x00000000U */
11596 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
11597 /* .. L1_SEL = 1 */
11598 /* .. ==> 0XF8000790[2:2] = 0x00000001U */
11599 /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
11600 /* .. L2_SEL = 0 */
11601 /* .. ==> 0XF8000790[4:3] = 0x00000000U */
11602 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
11603 /* .. L3_SEL = 0 */
11604 /* .. ==> 0XF8000790[7:5] = 0x00000000U */
11605 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
11606 /* .. Speed = 1 */
11607 /* .. ==> 0XF8000790[8:8] = 0x00000001U */
11608 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
11609 /* .. IO_Type = 1 */
11610 /* .. ==> 0XF8000790[11:9] = 0x00000001U */
11611 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
11612 /* .. PULLUP = 0 */
11613 /* .. ==> 0XF8000790[12:12] = 0x00000000U */
11614 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
11615 /* .. DisableRcvr = 0 */
11616 /* .. ==> 0XF8000790[13:13] = 0x00000000U */
11617 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
11618 /* .. */
11619 EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00000305U),
11620 /* .. TRI_ENABLE = 0 */
11621 /* .. ==> 0XF8000794[0:0] = 0x00000000U */
11622 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
11623 /* .. L0_SEL = 0 */
11624 /* .. ==> 0XF8000794[1:1] = 0x00000000U */
11625 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
11626 /* .. L1_SEL = 1 */
11627 /* .. ==> 0XF8000794[2:2] = 0x00000001U */
11628 /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
11629 /* .. L2_SEL = 0 */
11630 /* .. ==> 0XF8000794[4:3] = 0x00000000U */
11631 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
11632 /* .. L3_SEL = 0 */
11633 /* .. ==> 0XF8000794[7:5] = 0x00000000U */
11634 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
11635 /* .. Speed = 1 */
11636 /* .. ==> 0XF8000794[8:8] = 0x00000001U */
11637 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
11638 /* .. IO_Type = 1 */
11639 /* .. ==> 0XF8000794[11:9] = 0x00000001U */
11640 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
11641 /* .. PULLUP = 0 */
11642 /* .. ==> 0XF8000794[12:12] = 0x00000000U */
11643 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
11644 /* .. DisableRcvr = 0 */
11645 /* .. ==> 0XF8000794[13:13] = 0x00000000U */
11646 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
11647 /* .. */
11648 EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00000304U),
11649 /* .. TRI_ENABLE = 0 */
11650 /* .. ==> 0XF8000798[0:0] = 0x00000000U */
11651 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
11652 /* .. L0_SEL = 0 */
11653 /* .. ==> 0XF8000798[1:1] = 0x00000000U */
11654 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
11655 /* .. L1_SEL = 1 */
11656 /* .. ==> 0XF8000798[2:2] = 0x00000001U */
11657 /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
11658 /* .. L2_SEL = 0 */
11659 /* .. ==> 0XF8000798[4:3] = 0x00000000U */
11660 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
11661 /* .. L3_SEL = 0 */
11662 /* .. ==> 0XF8000798[7:5] = 0x00000000U */
11663 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
11664 /* .. Speed = 1 */
11665 /* .. ==> 0XF8000798[8:8] = 0x00000001U */
11666 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
11667 /* .. IO_Type = 1 */
11668 /* .. ==> 0XF8000798[11:9] = 0x00000001U */
11669 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
11670 /* .. PULLUP = 0 */
11671 /* .. ==> 0XF8000798[12:12] = 0x00000000U */
11672 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
11673 /* .. DisableRcvr = 0 */
11674 /* .. ==> 0XF8000798[13:13] = 0x00000000U */
11675 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
11676 /* .. */
11677 EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00000304U),
11678 /* .. TRI_ENABLE = 0 */
11679 /* .. ==> 0XF800079C[0:0] = 0x00000000U */
11680 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
11681 /* .. L0_SEL = 0 */
11682 /* .. ==> 0XF800079C[1:1] = 0x00000000U */
11683 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
11684 /* .. L1_SEL = 1 */
11685 /* .. ==> 0XF800079C[2:2] = 0x00000001U */
11686 /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
11687 /* .. L2_SEL = 0 */
11688 /* .. ==> 0XF800079C[4:3] = 0x00000000U */
11689 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
11690 /* .. L3_SEL = 0 */
11691 /* .. ==> 0XF800079C[7:5] = 0x00000000U */
11692 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
11693 /* .. Speed = 1 */
11694 /* .. ==> 0XF800079C[8:8] = 0x00000001U */
11695 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
11696 /* .. IO_Type = 1 */
11697 /* .. ==> 0XF800079C[11:9] = 0x00000001U */
11698 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
11699 /* .. PULLUP = 0 */
11700 /* .. ==> 0XF800079C[12:12] = 0x00000000U */
11701 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
11702 /* .. DisableRcvr = 0 */
11703 /* .. ==> 0XF800079C[13:13] = 0x00000000U */
11704 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
11705 /* .. */
11706 EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00000304U),
11707 /* .. TRI_ENABLE = 0 */
11708 /* .. ==> 0XF80007A0[0:0] = 0x00000000U */
11709 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
11710 /* .. L0_SEL = 0 */
11711 /* .. ==> 0XF80007A0[1:1] = 0x00000000U */
11712 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
11713 /* .. L1_SEL = 0 */
11714 /* .. ==> 0XF80007A0[2:2] = 0x00000000U */
11715 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
11716 /* .. L2_SEL = 0 */
11717 /* .. ==> 0XF80007A0[4:3] = 0x00000000U */
11718 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
11719 /* .. L3_SEL = 4 */
11720 /* .. ==> 0XF80007A0[7:5] = 0x00000004U */
11721 /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
11722 /* .. Speed = 1 */
11723 /* .. ==> 0XF80007A0[8:8] = 0x00000001U */
11724 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
11725 /* .. IO_Type = 1 */
11726 /* .. ==> 0XF80007A0[11:9] = 0x00000001U */
11727 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
11728 /* .. PULLUP = 0 */
11729 /* .. ==> 0XF80007A0[12:12] = 0x00000000U */
11730 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
11731 /* .. DisableRcvr = 0 */
11732 /* .. ==> 0XF80007A0[13:13] = 0x00000000U */
11733 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
11734 /* .. */
11735 EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00000380U),
11736 /* .. TRI_ENABLE = 0 */
11737 /* .. ==> 0XF80007A4[0:0] = 0x00000000U */
11738 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
11739 /* .. L0_SEL = 0 */
11740 /* .. ==> 0XF80007A4[1:1] = 0x00000000U */
11741 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
11742 /* .. L1_SEL = 0 */
11743 /* .. ==> 0XF80007A4[2:2] = 0x00000000U */
11744 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
11745 /* .. L2_SEL = 0 */
11746 /* .. ==> 0XF80007A4[4:3] = 0x00000000U */
11747 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
11748 /* .. L3_SEL = 4 */
11749 /* .. ==> 0XF80007A4[7:5] = 0x00000004U */
11750 /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
11751 /* .. Speed = 1 */
11752 /* .. ==> 0XF80007A4[8:8] = 0x00000001U */
11753 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
11754 /* .. IO_Type = 1 */
11755 /* .. ==> 0XF80007A4[11:9] = 0x00000001U */
11756 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
11757 /* .. PULLUP = 0 */
11758 /* .. ==> 0XF80007A4[12:12] = 0x00000000U */
11759 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
11760 /* .. DisableRcvr = 0 */
11761 /* .. ==> 0XF80007A4[13:13] = 0x00000000U */
11762 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
11763 /* .. */
11764 EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00000380U),
11765 /* .. TRI_ENABLE = 0 */
11766 /* .. ==> 0XF80007A8[0:0] = 0x00000000U */
11767 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
11768 /* .. L0_SEL = 0 */
11769 /* .. ==> 0XF80007A8[1:1] = 0x00000000U */
11770 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
11771 /* .. L1_SEL = 0 */
11772 /* .. ==> 0XF80007A8[2:2] = 0x00000000U */
11773 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
11774 /* .. L2_SEL = 0 */
11775 /* .. ==> 0XF80007A8[4:3] = 0x00000000U */
11776 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
11777 /* .. L3_SEL = 4 */
11778 /* .. ==> 0XF80007A8[7:5] = 0x00000004U */
11779 /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
11780 /* .. Speed = 1 */
11781 /* .. ==> 0XF80007A8[8:8] = 0x00000001U */
11782 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
11783 /* .. IO_Type = 1 */
11784 /* .. ==> 0XF80007A8[11:9] = 0x00000001U */
11785 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
11786 /* .. PULLUP = 0 */
11787 /* .. ==> 0XF80007A8[12:12] = 0x00000000U */
11788 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
11789 /* .. DisableRcvr = 0 */
11790 /* .. ==> 0XF80007A8[13:13] = 0x00000000U */
11791 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
11792 /* .. */
11793 EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00000380U),
11794 /* .. TRI_ENABLE = 0 */
11795 /* .. ==> 0XF80007AC[0:0] = 0x00000000U */
11796 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
11797 /* .. L0_SEL = 0 */
11798 /* .. ==> 0XF80007AC[1:1] = 0x00000000U */
11799 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
11800 /* .. L1_SEL = 0 */
11801 /* .. ==> 0XF80007AC[2:2] = 0x00000000U */
11802 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
11803 /* .. L2_SEL = 0 */
11804 /* .. ==> 0XF80007AC[4:3] = 0x00000000U */
11805 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
11806 /* .. L3_SEL = 4 */
11807 /* .. ==> 0XF80007AC[7:5] = 0x00000004U */
11808 /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
11809 /* .. Speed = 1 */
11810 /* .. ==> 0XF80007AC[8:8] = 0x00000001U */
11811 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
11812 /* .. IO_Type = 1 */
11813 /* .. ==> 0XF80007AC[11:9] = 0x00000001U */
11814 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
11815 /* .. PULLUP = 0 */
11816 /* .. ==> 0XF80007AC[12:12] = 0x00000000U */
11817 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
11818 /* .. DisableRcvr = 0 */
11819 /* .. ==> 0XF80007AC[13:13] = 0x00000000U */
11820 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
11821 /* .. */
11822 EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00000380U),
11823 /* .. TRI_ENABLE = 0 */
11824 /* .. ==> 0XF80007B0[0:0] = 0x00000000U */
11825 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
11826 /* .. L0_SEL = 0 */
11827 /* .. ==> 0XF80007B0[1:1] = 0x00000000U */
11828 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
11829 /* .. L1_SEL = 0 */
11830 /* .. ==> 0XF80007B0[2:2] = 0x00000000U */
11831 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
11832 /* .. L2_SEL = 0 */
11833 /* .. ==> 0XF80007B0[4:3] = 0x00000000U */
11834 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
11835 /* .. L3_SEL = 4 */
11836 /* .. ==> 0XF80007B0[7:5] = 0x00000004U */
11837 /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
11838 /* .. Speed = 1 */
11839 /* .. ==> 0XF80007B0[8:8] = 0x00000001U */
11840 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
11841 /* .. IO_Type = 1 */
11842 /* .. ==> 0XF80007B0[11:9] = 0x00000001U */
11843 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
11844 /* .. PULLUP = 0 */
11845 /* .. ==> 0XF80007B0[12:12] = 0x00000000U */
11846 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
11847 /* .. DisableRcvr = 0 */
11848 /* .. ==> 0XF80007B0[13:13] = 0x00000000U */
11849 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
11850 /* .. */
11851 EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00000380U),
11852 /* .. TRI_ENABLE = 0 */
11853 /* .. ==> 0XF80007B4[0:0] = 0x00000000U */
11854 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
11855 /* .. L0_SEL = 0 */
11856 /* .. ==> 0XF80007B4[1:1] = 0x00000000U */
11857 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
11858 /* .. L1_SEL = 0 */
11859 /* .. ==> 0XF80007B4[2:2] = 0x00000000U */
11860 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
11861 /* .. L2_SEL = 0 */
11862 /* .. ==> 0XF80007B4[4:3] = 0x00000000U */
11863 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
11864 /* .. L3_SEL = 4 */
11865 /* .. ==> 0XF80007B4[7:5] = 0x00000004U */
11866 /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
11867 /* .. Speed = 1 */
11868 /* .. ==> 0XF80007B4[8:8] = 0x00000001U */
11869 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
11870 /* .. IO_Type = 1 */
11871 /* .. ==> 0XF80007B4[11:9] = 0x00000001U */
11872 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
11873 /* .. PULLUP = 0 */
11874 /* .. ==> 0XF80007B4[12:12] = 0x00000000U */
11875 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
11876 /* .. DisableRcvr = 0 */
11877 /* .. ==> 0XF80007B4[13:13] = 0x00000000U */
11878 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
11879 /* .. */
11880 EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00000380U),
Michal Simek264065f2016-03-03 13:25:03 +0100[diff] [blame]11881 /* .. TRI_ENABLE = 0 */
11882 /* .. ==> 0XF80007B8[0:0] = 0x00000000U */
11883 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
11884 /* .. L0_SEL = 0 */
11885 /* .. ==> 0XF80007B8[1:1] = 0x00000000U */
11886 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
11887 /* .. L1_SEL = 0 */
11888 /* .. ==> 0XF80007B8[2:2] = 0x00000000U */
11889 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
11890 /* .. L2_SEL = 0 */
11891 /* .. ==> 0XF80007B8[4:3] = 0x00000000U */
11892 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
11893 /* .. L3_SEL = 0 */
11894 /* .. ==> 0XF80007B8[7:5] = 0x00000000U */
11895 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
11896 /* .. Speed = 0 */
11897 /* .. ==> 0XF80007B8[8:8] = 0x00000000U */
11898 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
11899 /* .. IO_Type = 1 */
11900 /* .. ==> 0XF80007B8[11:9] = 0x00000001U */
11901 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
11902 /* .. PULLUP = 1 */
11903 /* .. ==> 0XF80007B8[12:12] = 0x00000001U */
11904 /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
11905 /* .. DisableRcvr = 0 */
11906 /* .. ==> 0XF80007B8[13:13] = 0x00000000U */
11907 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
11908 /* .. */
11909 EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00001200U),
Nathan Rossi4eeed0e2015-11-24 19:34:09 +1000[diff] [blame]11910 /* .. TRI_ENABLE = 1 */
11911 /* .. ==> 0XF80007BC[0:0] = 0x00000001U */
11912 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
11913 /* .. Speed = 0 */
11914 /* .. ==> 0XF80007BC[8:8] = 0x00000000U */
11915 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
11916 /* .. IO_Type = 1 */
11917 /* .. ==> 0XF80007BC[11:9] = 0x00000001U */
11918 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
11919 /* .. PULLUP = 0 */
11920 /* .. ==> 0XF80007BC[12:12] = 0x00000000U */
11921 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
11922 /* .. DisableRcvr = 0 */
11923 /* .. ==> 0XF80007BC[13:13] = 0x00000000U */
11924 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
11925 /* .. */
11926 EMIT_MASKWRITE(0XF80007BC, 0x00003F01U, 0x00000201U),
11927 /* .. TRI_ENABLE = 0 */
11928 /* .. ==> 0XF80007C0[0:0] = 0x00000000U */
11929 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
11930 /* .. L0_SEL = 0 */
11931 /* .. ==> 0XF80007C0[1:1] = 0x00000000U */
11932 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
11933 /* .. L1_SEL = 0 */
11934 /* .. ==> 0XF80007C0[2:2] = 0x00000000U */
11935 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
11936 /* .. L2_SEL = 0 */
11937 /* .. ==> 0XF80007C0[4:3] = 0x00000000U */
11938 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
11939 /* .. L3_SEL = 7 */
11940 /* .. ==> 0XF80007C0[7:5] = 0x00000007U */
11941 /* .. ==> MASK : 0x000000E0U VAL : 0x000000E0U */
11942 /* .. Speed = 0 */
11943 /* .. ==> 0XF80007C0[8:8] = 0x00000000U */
11944 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
11945 /* .. IO_Type = 1 */
11946 /* .. ==> 0XF80007C0[11:9] = 0x00000001U */
11947 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
11948 /* .. PULLUP = 0 */
11949 /* .. ==> 0XF80007C0[12:12] = 0x00000000U */
11950 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
11951 /* .. DisableRcvr = 0 */
11952 /* .. ==> 0XF80007C0[13:13] = 0x00000000U */
11953 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
11954 /* .. */
11955 EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x000002E0U),
11956 /* .. TRI_ENABLE = 1 */
11957 /* .. ==> 0XF80007C4[0:0] = 0x00000001U */
11958 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
11959 /* .. L0_SEL = 0 */
11960 /* .. ==> 0XF80007C4[1:1] = 0x00000000U */
11961 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
11962 /* .. L1_SEL = 0 */
11963 /* .. ==> 0XF80007C4[2:2] = 0x00000000U */
11964 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
11965 /* .. L2_SEL = 0 */
11966 /* .. ==> 0XF80007C4[4:3] = 0x00000000U */
11967 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
11968 /* .. L3_SEL = 7 */
11969 /* .. ==> 0XF80007C4[7:5] = 0x00000007U */
11970 /* .. ==> MASK : 0x000000E0U VAL : 0x000000E0U */
11971 /* .. Speed = 0 */
11972 /* .. ==> 0XF80007C4[8:8] = 0x00000000U */
11973 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
11974 /* .. IO_Type = 1 */
11975 /* .. ==> 0XF80007C4[11:9] = 0x00000001U */
11976 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
11977 /* .. PULLUP = 0 */
11978 /* .. ==> 0XF80007C4[12:12] = 0x00000000U */
11979 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
11980 /* .. DisableRcvr = 0 */
11981 /* .. ==> 0XF80007C4[13:13] = 0x00000000U */
11982 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
11983 /* .. */
11984 EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x000002E1U),
11985 /* .. TRI_ENABLE = 0 */
Michal Simek264065f2016-03-03 13:25:03 +0100[diff] [blame]11986 /* .. ==> 0XF80007C8[0:0] = 0x00000000U */
11987 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
11988 /* .. L0_SEL = 0 */
11989 /* .. ==> 0XF80007C8[1:1] = 0x00000000U */
11990 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
11991 /* .. L1_SEL = 0 */
11992 /* .. ==> 0XF80007C8[2:2] = 0x00000000U */
11993 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
11994 /* .. L2_SEL = 0 */
11995 /* .. ==> 0XF80007C8[4:3] = 0x00000000U */
11996 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
11997 /* .. L3_SEL = 0 */
11998 /* .. ==> 0XF80007C8[7:5] = 0x00000000U */
11999 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
12000 /* .. Speed = 0 */
12001 /* .. ==> 0XF80007C8[8:8] = 0x00000000U */
12002 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
12003 /* .. IO_Type = 1 */
12004 /* .. ==> 0XF80007C8[11:9] = 0x00000001U */
12005 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
12006 /* .. PULLUP = 0 */
12007 /* .. ==> 0XF80007C8[12:12] = 0x00000000U */
12008 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
12009 /* .. DisableRcvr = 0 */
12010 /* .. ==> 0XF80007C8[13:13] = 0x00000000U */
12011 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
12012 /* .. */
12013 EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x00000200U),
12014 /* .. TRI_ENABLE = 0 */
12015 /* .. ==> 0XF80007CC[0:0] = 0x00000000U */
12016 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
12017 /* .. L0_SEL = 0 */
12018 /* .. ==> 0XF80007CC[1:1] = 0x00000000U */
12019 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
12020 /* .. L1_SEL = 0 */
12021 /* .. ==> 0XF80007CC[2:2] = 0x00000000U */
12022 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
12023 /* .. L2_SEL = 0 */
12024 /* .. ==> 0XF80007CC[4:3] = 0x00000000U */
12025 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
12026 /* .. L3_SEL = 0 */
12027 /* .. ==> 0XF80007CC[7:5] = 0x00000000U */
12028 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
12029 /* .. Speed = 0 */
12030 /* .. ==> 0XF80007CC[8:8] = 0x00000000U */
12031 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
12032 /* .. IO_Type = 1 */
12033 /* .. ==> 0XF80007CC[11:9] = 0x00000001U */
12034 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
12035 /* .. PULLUP = 0 */
12036 /* .. ==> 0XF80007CC[12:12] = 0x00000000U */
12037 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
12038 /* .. DisableRcvr = 0 */
12039 /* .. ==> 0XF80007CC[13:13] = 0x00000000U */
12040 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
12041 /* .. */
12042 EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x00000200U),
12043 /* .. TRI_ENABLE = 0 */
Nathan Rossi4eeed0e2015-11-24 19:34:09 +1000[diff] [blame]12044 /* .. ==> 0XF80007D0[0:0] = 0x00000000U */
12045 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
12046 /* .. L0_SEL = 0 */
12047 /* .. ==> 0XF80007D0[1:1] = 0x00000000U */
12048 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
12049 /* .. L1_SEL = 0 */
12050 /* .. ==> 0XF80007D0[2:2] = 0x00000000U */
12051 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
12052 /* .. L2_SEL = 0 */
12053 /* .. ==> 0XF80007D0[4:3] = 0x00000000U */
12054 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
12055 /* .. L3_SEL = 4 */
12056 /* .. ==> 0XF80007D0[7:5] = 0x00000004U */
12057 /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
12058 /* .. Speed = 0 */
12059 /* .. ==> 0XF80007D0[8:8] = 0x00000000U */
12060 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
12061 /* .. IO_Type = 1 */
12062 /* .. ==> 0XF80007D0[11:9] = 0x00000001U */
12063 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
12064 /* .. PULLUP = 0 */
12065 /* .. ==> 0XF80007D0[12:12] = 0x00000000U */
12066 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
12067 /* .. DisableRcvr = 0 */
12068 /* .. ==> 0XF80007D0[13:13] = 0x00000000U */
12069 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
12070 /* .. */
12071 EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00000280U),
12072 /* .. TRI_ENABLE = 0 */
12073 /* .. ==> 0XF80007D4[0:0] = 0x00000000U */
12074 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
12075 /* .. L0_SEL = 0 */
12076 /* .. ==> 0XF80007D4[1:1] = 0x00000000U */
12077 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
12078 /* .. L1_SEL = 0 */
12079 /* .. ==> 0XF80007D4[2:2] = 0x00000000U */
12080 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
12081 /* .. L2_SEL = 0 */
12082 /* .. ==> 0XF80007D4[4:3] = 0x00000000U */
12083 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
12084 /* .. L3_SEL = 4 */
12085 /* .. ==> 0XF80007D4[7:5] = 0x00000004U */
12086 /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
12087 /* .. Speed = 0 */
12088 /* .. ==> 0XF80007D4[8:8] = 0x00000000U */
12089 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
12090 /* .. IO_Type = 1 */
12091 /* .. ==> 0XF80007D4[11:9] = 0x00000001U */
12092 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
12093 /* .. PULLUP = 0 */
12094 /* .. ==> 0XF80007D4[12:12] = 0x00000000U */
12095 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
12096 /* .. DisableRcvr = 0 */
12097 /* .. ==> 0XF80007D4[13:13] = 0x00000000U */
12098 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
12099 /* .. */
12100 EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00000280U),
12101 /* .. SDIO0_WP_SEL = 55 */
12102 /* .. ==> 0XF8000830[5:0] = 0x00000037U */
12103 /* .. ==> MASK : 0x0000003FU VAL : 0x00000037U */
12104 /* .. SDIO0_CD_SEL = 47 */
12105 /* .. ==> 0XF8000830[21:16] = 0x0000002FU */
12106 /* .. ==> MASK : 0x003F0000U VAL : 0x002F0000U */
12107 /* .. */
12108 EMIT_MASKWRITE(0XF8000830, 0x003F003FU, 0x002F0037U),
12109 /* .. FINISH: MIO PROGRAMMING */
12110 /* .. START: LOCK IT BACK */
12111 /* .. LOCK_KEY = 0X767B */
12112 /* .. ==> 0XF8000004[15:0] = 0x0000767BU */
12113 /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */
12114 /* .. */
12115 EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
12116 /* .. FINISH: LOCK IT BACK */
12117 /* FINISH: top */
12118 /* */
12119 EMIT_EXIT(),
12120
12121 /* */
12122};
12123
12124unsigned long ps7_peripherals_init_data_1_0[] = {
12125 /* START: top */
12126 /* .. START: SLCR SETTINGS */
12127 /* .. UNLOCK_KEY = 0XDF0D */
12128 /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
12129 /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */
12130 /* .. */
12131 EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
12132 /* .. FINISH: SLCR SETTINGS */
12133 /* .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS */
12134 /* .. IBUF_DISABLE_MODE = 0x1 */
12135 /* .. ==> 0XF8000B48[7:7] = 0x00000001U */
12136 /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */
12137 /* .. TERM_DISABLE_MODE = 0x1 */
12138 /* .. ==> 0XF8000B48[8:8] = 0x00000001U */
12139 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
12140 /* .. */
12141 EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U),
12142 /* .. IBUF_DISABLE_MODE = 0x1 */
12143 /* .. ==> 0XF8000B4C[7:7] = 0x00000001U */
12144 /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */
12145 /* .. TERM_DISABLE_MODE = 0x1 */
12146 /* .. ==> 0XF8000B4C[8:8] = 0x00000001U */
12147 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
12148 /* .. */
12149 EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U),
12150 /* .. IBUF_DISABLE_MODE = 0x1 */
12151 /* .. ==> 0XF8000B50[7:7] = 0x00000001U */
12152 /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */
12153 /* .. TERM_DISABLE_MODE = 0x1 */
12154 /* .. ==> 0XF8000B50[8:8] = 0x00000001U */
12155 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
12156 /* .. */
12157 EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
12158 /* .. IBUF_DISABLE_MODE = 0x1 */
12159 /* .. ==> 0XF8000B54[7:7] = 0x00000001U */
12160 /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */
12161 /* .. TERM_DISABLE_MODE = 0x1 */
12162 /* .. ==> 0XF8000B54[8:8] = 0x00000001U */
12163 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
12164 /* .. */
12165 EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
12166 /* .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS */
12167 /* .. START: LOCK IT BACK */
12168 /* .. LOCK_KEY = 0X767B */
12169 /* .. ==> 0XF8000004[15:0] = 0x0000767BU */
12170 /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */
12171 /* .. */
12172 EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
12173 /* .. FINISH: LOCK IT BACK */
12174 /* .. START: SRAM/NOR SET OPMODE */
12175 /* .. FINISH: SRAM/NOR SET OPMODE */
12176 /* .. START: UART REGISTERS */
12177 /* .. BDIV = 0x6 */
12178 /* .. ==> 0XE0001034[7:0] = 0x00000006U */
12179 /* .. ==> MASK : 0x000000FFU VAL : 0x00000006U */
12180 /* .. */
12181 EMIT_MASKWRITE(0XE0001034, 0x000000FFU, 0x00000006U),
Michal Simek264065f2016-03-03 13:25:03 +0100[diff] [blame]12182 /* .. CD = 0x7c */
12183 /* .. ==> 0XE0001018[15:0] = 0x0000007CU */
12184 /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU */
Nathan Rossi4eeed0e2015-11-24 19:34:09 +1000[diff] [blame]12185 /* .. */
Michal Simek264065f2016-03-03 13:25:03 +0100[diff] [blame]12186 EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000007CU),
Nathan Rossi4eeed0e2015-11-24 19:34:09 +1000[diff] [blame]12187 /* .. STPBRK = 0x0 */
12188 /* .. ==> 0XE0001000[8:8] = 0x00000000U */
12189 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
12190 /* .. STTBRK = 0x0 */
12191 /* .. ==> 0XE0001000[7:7] = 0x00000000U */
12192 /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
12193 /* .. RSTTO = 0x0 */
12194 /* .. ==> 0XE0001000[6:6] = 0x00000000U */
12195 /* .. ==> MASK : 0x00000040U VAL : 0x00000000U */
12196 /* .. TXDIS = 0x0 */
12197 /* .. ==> 0XE0001000[5:5] = 0x00000000U */
12198 /* .. ==> MASK : 0x00000020U VAL : 0x00000000U */
12199 /* .. TXEN = 0x1 */
12200 /* .. ==> 0XE0001000[4:4] = 0x00000001U */
12201 /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */
12202 /* .. RXDIS = 0x0 */
12203 /* .. ==> 0XE0001000[3:3] = 0x00000000U */
12204 /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
12205 /* .. RXEN = 0x1 */
12206 /* .. ==> 0XE0001000[2:2] = 0x00000001U */
12207 /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
12208 /* .. TXRES = 0x1 */
12209 /* .. ==> 0XE0001000[1:1] = 0x00000001U */
12210 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
12211 /* .. RXRES = 0x1 */
12212 /* .. ==> 0XE0001000[0:0] = 0x00000001U */
12213 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
12214 /* .. */
12215 EMIT_MASKWRITE(0XE0001000, 0x000001FFU, 0x00000017U),
12216 /* .. IRMODE = 0x0 */
12217 /* .. ==> 0XE0001004[11:11] = 0x00000000U */
12218 /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
12219 /* .. UCLKEN = 0x0 */
12220 /* .. ==> 0XE0001004[10:10] = 0x00000000U */
12221 /* .. ==> MASK : 0x00000400U VAL : 0x00000000U */
12222 /* .. CHMODE = 0x0 */
12223 /* .. ==> 0XE0001004[9:8] = 0x00000000U */
12224 /* .. ==> MASK : 0x00000300U VAL : 0x00000000U */
12225 /* .. NBSTOP = 0x0 */
12226 /* .. ==> 0XE0001004[7:6] = 0x00000000U */
12227 /* .. ==> MASK : 0x000000C0U VAL : 0x00000000U */
12228 /* .. PAR = 0x4 */
12229 /* .. ==> 0XE0001004[5:3] = 0x00000004U */
12230 /* .. ==> MASK : 0x00000038U VAL : 0x00000020U */
12231 /* .. CHRL = 0x0 */
12232 /* .. ==> 0XE0001004[2:1] = 0x00000000U */
12233 /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */
12234 /* .. CLKS = 0x0 */
12235 /* .. ==> 0XE0001004[0:0] = 0x00000000U */
12236 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
12237 /* .. */
12238 EMIT_MASKWRITE(0XE0001004, 0x00000FFFU, 0x00000020U),
12239 /* .. FINISH: UART REGISTERS */
Nathan Rossi4eeed0e2015-11-24 19:34:09 +1000[diff] [blame]12240 /* .. START: QSPI REGISTERS */
12241 /* .. Holdb_dr = 1 */
12242 /* .. ==> 0XE000D000[19:19] = 0x00000001U */
12243 /* .. ==> MASK : 0x00080000U VAL : 0x00080000U */
12244 /* .. */
12245 EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U),
12246 /* .. FINISH: QSPI REGISTERS */
12247 /* .. START: PL POWER ON RESET REGISTERS */
12248 /* .. PCFG_POR_CNT_4K = 0 */
12249 /* .. ==> 0XF8007000[29:29] = 0x00000000U */
12250 /* .. ==> MASK : 0x20000000U VAL : 0x00000000U */
12251 /* .. */
12252 EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
12253 /* .. FINISH: PL POWER ON RESET REGISTERS */
12254 /* .. START: SMC TIMING CALCULATION REGISTER UPDATE */
12255 /* .. .. START: NAND SET CYCLE */
12256 /* .. .. FINISH: NAND SET CYCLE */
12257 /* .. .. START: OPMODE */
12258 /* .. .. FINISH: OPMODE */
12259 /* .. .. START: DIRECT COMMAND */
12260 /* .. .. FINISH: DIRECT COMMAND */
12261 /* .. .. START: SRAM/NOR CS0 SET CYCLE */
12262 /* .. .. FINISH: SRAM/NOR CS0 SET CYCLE */
12263 /* .. .. START: DIRECT COMMAND */
12264 /* .. .. FINISH: DIRECT COMMAND */
12265 /* .. .. START: NOR CS0 BASE ADDRESS */
12266 /* .. .. FINISH: NOR CS0 BASE ADDRESS */
12267 /* .. .. START: SRAM/NOR CS1 SET CYCLE */
12268 /* .. .. FINISH: SRAM/NOR CS1 SET CYCLE */
12269 /* .. .. START: DIRECT COMMAND */
12270 /* .. .. FINISH: DIRECT COMMAND */
12271 /* .. .. START: NOR CS1 BASE ADDRESS */
12272 /* .. .. FINISH: NOR CS1 BASE ADDRESS */
12273 /* .. .. START: USB RESET */
12274 /* .. .. .. START: USB0 RESET */
12275 /* .. .. .. .. START: DIR MODE BANK 0 */
12276 /* .. .. .. .. FINISH: DIR MODE BANK 0 */
12277 /* .. .. .. .. START: DIR MODE BANK 1 */
Michal Simek264065f2016-03-03 13:25:03 +0100[diff] [blame]12278 /* .. .. .. .. DIRECTION_1 = 0x4000 */
12279 /* .. .. .. .. ==> 0XE000A244[21:0] = 0x00004000U */
12280 /* .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U */
12281 /* .. .. .. .. */
12282 EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU, 0x00004000U),
Nathan Rossi4eeed0e2015-11-24 19:34:09 +1000[diff] [blame]12283 /* .. .. .. .. FINISH: DIR MODE BANK 1 */
12284 /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
12285 /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
12286 /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
12287 /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
12288 /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
Michal Simek264065f2016-03-03 13:25:03 +0100[diff] [blame]12289 /* .. .. .. .. MASK_1_LSW = 0xbfff */
12290 /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
12291 /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */
12292 /* .. .. .. .. DATA_1_LSW = 0x4000 */
12293 /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U */
12294 /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U */
12295 /* .. .. .. .. */
12296 EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U),
Nathan Rossi4eeed0e2015-11-24 19:34:09 +1000[diff] [blame]12297 /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
12298 /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
12299 /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
12300 /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
12301 /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
12302 /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
Michal Simek264065f2016-03-03 13:25:03 +0100[diff] [blame]12303 /* .. .. .. .. OP_ENABLE_1 = 0x4000 */
12304 /* .. .. .. .. ==> 0XE000A248[21:0] = 0x00004000U */
12305 /* .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U */
12306 /* .. .. .. .. */
12307 EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU, 0x00004000U),
Nathan Rossi4eeed0e2015-11-24 19:34:09 +1000[diff] [blame]12308 /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
12309 /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
12310 /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
12311 /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
12312 /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
12313 /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
Michal Simek264065f2016-03-03 13:25:03 +0100[diff] [blame]12314 /* .. .. .. .. MASK_1_LSW = 0xbfff */
12315 /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
12316 /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */
12317 /* .. .. .. .. DATA_1_LSW = 0x0 */
12318 /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U */
12319 /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U */
12320 /* .. .. .. .. */
12321 EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF0000U),
Nathan Rossi4eeed0e2015-11-24 19:34:09 +1000[diff] [blame]12322 /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
12323 /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
12324 /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
12325 /* .. .. .. .. START: ADD 1 MS DELAY */
12326 /* .. .. .. .. */
12327 EMIT_MASKDELAY(0XF8F00200, 1),
12328 /* .. .. .. .. FINISH: ADD 1 MS DELAY */
12329 /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
12330 /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
12331 /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
12332 /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
12333 /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
Michal Simek264065f2016-03-03 13:25:03 +0100[diff] [blame]12334 /* .. .. .. .. MASK_1_LSW = 0xbfff */
12335 /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
12336 /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */
12337 /* .. .. .. .. DATA_1_LSW = 0x4000 */
12338 /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U */
12339 /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U */
12340 /* .. .. .. .. */
12341 EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U),
Nathan Rossi4eeed0e2015-11-24 19:34:09 +1000[diff] [blame]12342 /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
12343 /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
12344 /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
12345 /* .. .. .. FINISH: USB0 RESET */
12346 /* .. .. .. START: USB1 RESET */
12347 /* .. .. .. .. START: DIR MODE BANK 0 */
12348 /* .. .. .. .. FINISH: DIR MODE BANK 0 */
12349 /* .. .. .. .. START: DIR MODE BANK 1 */
12350 /* .. .. .. .. FINISH: DIR MODE BANK 1 */
12351 /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
12352 /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
12353 /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
12354 /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
12355 /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
12356 /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
12357 /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
12358 /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
12359 /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
12360 /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
12361 /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
12362 /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
12363 /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
12364 /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
12365 /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
12366 /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
12367 /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
12368 /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
12369 /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
12370 /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
12371 /* .. .. .. .. START: ADD 1 MS DELAY */
12372 /* .. .. .. .. */
12373 EMIT_MASKDELAY(0XF8F00200, 1),
12374 /* .. .. .. .. FINISH: ADD 1 MS DELAY */
12375 /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
12376 /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
12377 /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
12378 /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
12379 /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
12380 /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
12381 /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
12382 /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
12383 /* .. .. .. FINISH: USB1 RESET */
12384 /* .. .. FINISH: USB RESET */
12385 /* .. .. START: ENET RESET */
12386 /* .. .. .. START: ENET0 RESET */
12387 /* .. .. .. .. START: DIR MODE BANK 0 */
12388 /* .. .. .. .. FINISH: DIR MODE BANK 0 */
12389 /* .. .. .. .. START: DIR MODE BANK 1 */
12390 /* .. .. .. .. FINISH: DIR MODE BANK 1 */
12391 /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
12392 /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
12393 /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
12394 /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
12395 /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
12396 /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
12397 /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
12398 /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
12399 /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
12400 /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
12401 /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
12402 /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
12403 /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
12404 /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
12405 /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
12406 /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
12407 /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
12408 /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
12409 /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
12410 /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
12411 /* .. .. .. .. START: ADD 1 MS DELAY */
12412 /* .. .. .. .. */
12413 EMIT_MASKDELAY(0XF8F00200, 1),
12414 /* .. .. .. .. FINISH: ADD 1 MS DELAY */
12415 /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
12416 /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
12417 /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
12418 /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
12419 /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
12420 /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
12421 /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
12422 /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
12423 /* .. .. .. FINISH: ENET0 RESET */
12424 /* .. .. .. START: ENET1 RESET */
12425 /* .. .. .. .. START: DIR MODE BANK 0 */
12426 /* .. .. .. .. FINISH: DIR MODE BANK 0 */
12427 /* .. .. .. .. START: DIR MODE BANK 1 */
12428 /* .. .. .. .. FINISH: DIR MODE BANK 1 */
12429 /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
12430 /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
12431 /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
12432 /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
12433 /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
12434 /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
12435 /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
12436 /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
12437 /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
12438 /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
12439 /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
12440 /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
12441 /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
12442 /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
12443 /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
12444 /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
12445 /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
12446 /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
12447 /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
12448 /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
12449 /* .. .. .. .. START: ADD 1 MS DELAY */
12450 /* .. .. .. .. */
12451 EMIT_MASKDELAY(0XF8F00200, 1),
12452 /* .. .. .. .. FINISH: ADD 1 MS DELAY */
12453 /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
12454 /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
12455 /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
12456 /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
12457 /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
12458 /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
12459 /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
12460 /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
12461 /* .. .. .. FINISH: ENET1 RESET */
12462 /* .. .. FINISH: ENET RESET */
12463 /* .. .. START: I2C RESET */
12464 /* .. .. .. START: I2C0 RESET */
12465 /* .. .. .. .. START: DIR MODE GPIO BANK0 */
12466 /* .. .. .. .. FINISH: DIR MODE GPIO BANK0 */
12467 /* .. .. .. .. START: DIR MODE GPIO BANK1 */
12468 /* .. .. .. .. FINISH: DIR MODE GPIO BANK1 */
12469 /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
12470 /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
12471 /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
12472 /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
12473 /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
12474 /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
12475 /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
12476 /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
12477 /* .. .. .. .. START: OUTPUT ENABLE */
12478 /* .. .. .. .. FINISH: OUTPUT ENABLE */
12479 /* .. .. .. .. START: OUTPUT ENABLE */
12480 /* .. .. .. .. FINISH: OUTPUT ENABLE */
12481 /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
12482 /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
12483 /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
12484 /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
12485 /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
12486 /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
12487 /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
12488 /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
12489 /* .. .. .. .. START: ADD 1 MS DELAY */
12490 /* .. .. .. .. */
12491 EMIT_MASKDELAY(0XF8F00200, 1),
12492 /* .. .. .. .. FINISH: ADD 1 MS DELAY */
12493 /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
12494 /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
12495 /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
12496 /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
12497 /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
12498 /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
12499 /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
12500 /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
12501 /* .. .. .. FINISH: I2C0 RESET */
12502 /* .. .. .. START: I2C1 RESET */
12503 /* .. .. .. .. START: DIR MODE GPIO BANK0 */
12504 /* .. .. .. .. FINISH: DIR MODE GPIO BANK0 */
12505 /* .. .. .. .. START: DIR MODE GPIO BANK1 */
12506 /* .. .. .. .. FINISH: DIR MODE GPIO BANK1 */
12507 /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
12508 /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
12509 /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
12510 /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
12511 /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
12512 /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
12513 /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
12514 /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
12515 /* .. .. .. .. START: OUTPUT ENABLE */
12516 /* .. .. .. .. FINISH: OUTPUT ENABLE */
12517 /* .. .. .. .. START: OUTPUT ENABLE */
12518 /* .. .. .. .. FINISH: OUTPUT ENABLE */
12519 /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
12520 /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
12521 /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
12522 /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
12523 /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
12524 /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
12525 /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
12526 /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
12527 /* .. .. .. .. START: ADD 1 MS DELAY */
12528 /* .. .. .. .. */
12529 EMIT_MASKDELAY(0XF8F00200, 1),
12530 /* .. .. .. .. FINISH: ADD 1 MS DELAY */
12531 /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
12532 /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
12533 /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
12534 /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
12535 /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
12536 /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
12537 /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
12538 /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
12539 /* .. .. .. FINISH: I2C1 RESET */
12540 /* .. .. FINISH: I2C RESET */
12541 /* .. .. START: NOR CHIP SELECT */
12542 /* .. .. .. START: DIR MODE BANK 0 */
12543 /* .. .. .. FINISH: DIR MODE BANK 0 */
12544 /* .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
12545 /* .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
12546 /* .. .. .. START: OUTPUT ENABLE BANK 0 */
12547 /* .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
12548 /* .. .. FINISH: NOR CHIP SELECT */
12549 /* .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE */
12550 /* FINISH: top */
12551 /* */
12552 EMIT_EXIT(),
12553
12554 /* */
12555};
12556
12557unsigned long ps7_post_config_1_0[] = {
12558 /* START: top */
12559 /* .. START: SLCR SETTINGS */
12560 /* .. UNLOCK_KEY = 0XDF0D */
12561 /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
12562 /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */
12563 /* .. */
12564 EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
12565 /* .. FINISH: SLCR SETTINGS */
12566 /* .. START: ENABLING LEVEL SHIFTER */
12567 /* .. USER_INP_ICT_EN_0 = 3 */
12568 /* .. ==> 0XF8000900[1:0] = 0x00000003U */
12569 /* .. ==> MASK : 0x00000003U VAL : 0x00000003U */
12570 /* .. USER_INP_ICT_EN_1 = 3 */
12571 /* .. ==> 0XF8000900[3:2] = 0x00000003U */
12572 /* .. ==> MASK : 0x0000000CU VAL : 0x0000000CU */
12573 /* .. */
12574 EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU),
12575 /* .. FINISH: ENABLING LEVEL SHIFTER */
Nathan Rossi4eeed0e2015-11-24 19:34:09 +1000[diff] [blame]12576 /* .. START: FPGA RESETS TO 0 */
12577 /* .. reserved_3 = 0 */
12578 /* .. ==> 0XF8000240[31:25] = 0x00000000U */
12579 /* .. ==> MASK : 0xFE000000U VAL : 0x00000000U */
12580 /* .. FPGA_ACP_RST = 0 */
12581 /* .. ==> 0XF8000240[24:24] = 0x00000000U */
12582 /* .. ==> MASK : 0x01000000U VAL : 0x00000000U */
12583 /* .. FPGA_AXDS3_RST = 0 */
12584 /* .. ==> 0XF8000240[23:23] = 0x00000000U */
12585 /* .. ==> MASK : 0x00800000U VAL : 0x00000000U */
12586 /* .. FPGA_AXDS2_RST = 0 */
12587 /* .. ==> 0XF8000240[22:22] = 0x00000000U */
12588 /* .. ==> MASK : 0x00400000U VAL : 0x00000000U */
12589 /* .. FPGA_AXDS1_RST = 0 */
12590 /* .. ==> 0XF8000240[21:21] = 0x00000000U */
12591 /* .. ==> MASK : 0x00200000U VAL : 0x00000000U */
12592 /* .. FPGA_AXDS0_RST = 0 */
12593 /* .. ==> 0XF8000240[20:20] = 0x00000000U */
12594 /* .. ==> MASK : 0x00100000U VAL : 0x00000000U */
12595 /* .. reserved_2 = 0 */
12596 /* .. ==> 0XF8000240[19:18] = 0x00000000U */
12597 /* .. ==> MASK : 0x000C0000U VAL : 0x00000000U */
12598 /* .. FSSW1_FPGA_RST = 0 */
12599 /* .. ==> 0XF8000240[17:17] = 0x00000000U */
12600 /* .. ==> MASK : 0x00020000U VAL : 0x00000000U */
12601 /* .. FSSW0_FPGA_RST = 0 */
12602 /* .. ==> 0XF8000240[16:16] = 0x00000000U */
12603 /* .. ==> MASK : 0x00010000U VAL : 0x00000000U */
12604 /* .. reserved_1 = 0 */
12605 /* .. ==> 0XF8000240[15:14] = 0x00000000U */
12606 /* .. ==> MASK : 0x0000C000U VAL : 0x00000000U */
12607 /* .. FPGA_FMSW1_RST = 0 */
12608 /* .. ==> 0XF8000240[13:13] = 0x00000000U */
12609 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
12610 /* .. FPGA_FMSW0_RST = 0 */
12611 /* .. ==> 0XF8000240[12:12] = 0x00000000U */
12612 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
12613 /* .. FPGA_DMA3_RST = 0 */
12614 /* .. ==> 0XF8000240[11:11] = 0x00000000U */
12615 /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
12616 /* .. FPGA_DMA2_RST = 0 */
12617 /* .. ==> 0XF8000240[10:10] = 0x00000000U */
12618 /* .. ==> MASK : 0x00000400U VAL : 0x00000000U */
12619 /* .. FPGA_DMA1_RST = 0 */
12620 /* .. ==> 0XF8000240[9:9] = 0x00000000U */
12621 /* .. ==> MASK : 0x00000200U VAL : 0x00000000U */
12622 /* .. FPGA_DMA0_RST = 0 */
12623 /* .. ==> 0XF8000240[8:8] = 0x00000000U */
12624 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
12625 /* .. reserved = 0 */
12626 /* .. ==> 0XF8000240[7:4] = 0x00000000U */
12627 /* .. ==> MASK : 0x000000F0U VAL : 0x00000000U */
12628 /* .. FPGA3_OUT_RST = 0 */
12629 /* .. ==> 0XF8000240[3:3] = 0x00000000U */
12630 /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
12631 /* .. FPGA2_OUT_RST = 0 */
12632 /* .. ==> 0XF8000240[2:2] = 0x00000000U */
12633 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
12634 /* .. FPGA1_OUT_RST = 0 */
12635 /* .. ==> 0XF8000240[1:1] = 0x00000000U */
12636 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
12637 /* .. FPGA0_OUT_RST = 0 */
12638 /* .. ==> 0XF8000240[0:0] = 0x00000000U */
12639 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
12640 /* .. */
12641 EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U),
12642 /* .. FINISH: FPGA RESETS TO 0 */
12643 /* .. START: AFI REGISTERS */
12644 /* .. .. START: AFI0 REGISTERS */
12645 /* .. .. FINISH: AFI0 REGISTERS */
12646 /* .. .. START: AFI1 REGISTERS */
12647 /* .. .. FINISH: AFI1 REGISTERS */
12648 /* .. .. START: AFI2 REGISTERS */
12649 /* .. .. FINISH: AFI2 REGISTERS */
12650 /* .. .. START: AFI3 REGISTERS */
12651 /* .. .. FINISH: AFI3 REGISTERS */
12652 /* .. FINISH: AFI REGISTERS */
12653 /* .. START: LOCK IT BACK */
12654 /* .. LOCK_KEY = 0X767B */
12655 /* .. ==> 0XF8000004[15:0] = 0x0000767BU */
12656 /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */
12657 /* .. */
12658 EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
12659 /* .. FINISH: LOCK IT BACK */
12660 /* FINISH: top */
12661 /* */
12662 EMIT_EXIT(),
12663
12664 /* */
12665};
12666
Nathan Rossi4eeed0e2015-11-24 19:34:09 +1000[diff] [blame]12667
12668#include "xil_io.h"
Nathan Rossi4eeed0e2015-11-24 19:34:09 +1000[diff] [blame]12669
12670unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
12671unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0;
12672unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0;
12673unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0;
12674unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
12675
12676int ps7_post_config(void)
12677{
12678 /* Get the PS_VERSION on run time */
12679 unsigned long si_ver = ps7GetSiliconVersion();
12680 int ret = -1;
12681 if (si_ver == PCW_SILICON_VERSION_1) {
12682 ret = ps7_config(ps7_post_config_1_0);
12683 if (ret != PS7_INIT_SUCCESS)
12684 return ret;
12685 } else if (si_ver == PCW_SILICON_VERSION_2) {
12686 ret = ps7_config(ps7_post_config_2_0);
12687 if (ret != PS7_INIT_SUCCESS)
12688 return ret;
12689 } else {
12690 ret = ps7_config(ps7_post_config_3_0);
12691 if (ret != PS7_INIT_SUCCESS)
12692 return ret;
12693 }
12694 return PS7_INIT_SUCCESS;
12695}
12696
Nathan Rossi4eeed0e2015-11-24 19:34:09 +1000[diff] [blame]12697int ps7_init(void)
12698{
12699 /* Get the PS_VERSION on run time */
12700 unsigned long si_ver = ps7GetSiliconVersion();
12701 int ret;
12702 /*int pcw_ver = 0; */
12703
12704 if (si_ver == PCW_SILICON_VERSION_1) {
12705 ps7_mio_init_data = ps7_mio_init_data_1_0;
12706 ps7_pll_init_data = ps7_pll_init_data_1_0;
12707 ps7_clock_init_data = ps7_clock_init_data_1_0;
12708 ps7_ddr_init_data = ps7_ddr_init_data_1_0;
12709 ps7_peripherals_init_data = ps7_peripherals_init_data_1_0;
12710 /*pcw_ver = 1; */
12711
12712 } else if (si_ver == PCW_SILICON_VERSION_2) {
12713 ps7_mio_init_data = ps7_mio_init_data_2_0;
12714 ps7_pll_init_data = ps7_pll_init_data_2_0;
12715 ps7_clock_init_data = ps7_clock_init_data_2_0;
12716 ps7_ddr_init_data = ps7_ddr_init_data_2_0;
12717 ps7_peripherals_init_data = ps7_peripherals_init_data_2_0;
12718 /*pcw_ver = 2; */
12719
12720 } else {
12721 ps7_mio_init_data = ps7_mio_init_data_3_0;
12722 ps7_pll_init_data = ps7_pll_init_data_3_0;
12723 ps7_clock_init_data = ps7_clock_init_data_3_0;
12724 ps7_ddr_init_data = ps7_ddr_init_data_3_0;
12725 ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
12726 /*pcw_ver = 3; */
12727 }
12728
12729 /* MIO init */
12730 ret = ps7_config(ps7_mio_init_data);
12731 if (ret != PS7_INIT_SUCCESS)
12732 return ret;
12733
12734 /* PLL init */
12735 ret = ps7_config(ps7_pll_init_data);
12736 if (ret != PS7_INIT_SUCCESS)
12737 return ret;
12738
12739 /* Clock init */
12740 ret = ps7_config(ps7_clock_init_data);
12741 if (ret != PS7_INIT_SUCCESS)
12742 return ret;
12743
12744 /* DDR init */
12745 ret = ps7_config(ps7_ddr_init_data);
12746 if (ret != PS7_INIT_SUCCESS)
12747 return ret;
12748
12749 /* Peripherals init */
12750 ret = ps7_config(ps7_peripherals_init_data);
12751 if (ret != PS7_INIT_SUCCESS)
12752 return ret;
12753 return PS7_INIT_SUCCESS;
12754}
12755