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Priyanka Jainfd45ca02018-11-28 13:04:27 +00001/* SPDX-License-Identifier: GPL-2.0+ */
2/*
Yangbo Lubb32e682021-06-03 10:51:19 +08003 * Copyright 2018-2021 NXP
Priyanka Jainfd45ca02018-11-28 13:04:27 +00004 */
5
6#ifndef __LX2_COMMON_H
7#define __LX2_COMMON_H
8
9#include <asm/arch/stream_id_lsch3.h>
10#include <asm/arch/config.h>
11#include <asm/arch/soc.h>
12
Priyanka Jainfd45ca02018-11-28 13:04:27 +000013#define CONFIG_FSL_MEMAC
14
15#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
16#define CONFIG_SYS_FLASH_BASE 0x20000000
17
Priyanka Jainfd45ca02018-11-28 13:04:27 +000018/* DDR */
Priyanka Jainfd45ca02018-11-28 13:04:27 +000019#define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */
20#define CONFIG_VERY_BIG_RAM
21#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
22#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
23#define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL
24#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 2
25#define CONFIG_SYS_SDRAM_SIZE 0x200000000UL
Priyanka Jainfd45ca02018-11-28 13:04:27 +000026#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
27#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
28#define SPD_EEPROM_ADDRESS1 0x51
29#define SPD_EEPROM_ADDRESS2 0x52
30#define SPD_EEPROM_ADDRESS3 0x53
31#define SPD_EEPROM_ADDRESS4 0x54
32#define SPD_EEPROM_ADDRESS5 0x55
33#define SPD_EEPROM_ADDRESS6 0x56
34#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
35#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
Priyanka Jainfd45ca02018-11-28 13:04:27 +000036#define CONFIG_SYS_MONITOR_LEN (936 * 1024)
37
38/* Miscellaneous configurable options */
Priyanka Jainfd45ca02018-11-28 13:04:27 +000039
40/* SMP Definitinos */
Michael Wallef056e0f2020-06-01 21:53:26 +020041#define CPU_RELEASE_ADDR secondary_boot_addr
Priyanka Jainfd45ca02018-11-28 13:04:27 +000042
43/* Generic Timer Definitions */
44/*
45 * This is not an accurate number. It is used in start.S. The frequency
46 * will be udpated later when get_bus_freq(0) is available.
47 */
48
49#define COUNTER_FREQUENCY 25000000 /* 25MHz */
50
Priyanka Jainfd45ca02018-11-28 13:04:27 +000051/* Serial Port */
Priyanka Jainfd45ca02018-11-28 13:04:27 +000052#define CONFIG_PL011_CLOCK (get_bus_freq(0) / 4)
53#define CONFIG_SYS_SERIAL0 0x21c0000
54#define CONFIG_SYS_SERIAL1 0x21d0000
55#define CONFIG_SYS_SERIAL2 0x21e0000
56#define CONFIG_SYS_SERIAL3 0x21f0000
57/*below might needs to be removed*/
58#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \
59 (void *)CONFIG_SYS_SERIAL1, \
60 (void *)CONFIG_SYS_SERIAL2, \
61 (void *)CONFIG_SYS_SERIAL3 }
Priyanka Jainfd45ca02018-11-28 13:04:27 +000062
63/* MC firmware */
64#define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000
65#define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000
66#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000
67#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000
68#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
69
Priyanka Jainfd45ca02018-11-28 13:04:27 +000070/*
71 * Carve out a DDR region which will not be used by u-boot/Linux
72 *
73 * It will be used by MC and Debug Server. The MC region must be
74 * 512MB aligned, so the min size to hide is 512MB.
75 */
76#ifdef CONFIG_FSL_MC_ENET
Meenakshi Aggarwal67f195c2019-02-27 14:41:02 +053077#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (256UL * 1024 * 1024)
Priyanka Jainfd45ca02018-11-28 13:04:27 +000078#endif
79
80/* I2C bus multiplexer */
81#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
82#define I2C_MUX_CH_DEFAULT 0x8
83
84/* RTC */
85#define RTC
86#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
87
88/* EEPROM */
Priyanka Jainfd45ca02018-11-28 13:04:27 +000089#define CONFIG_SYS_I2C_EEPROM_NXID
90#define CONFIG_SYS_EEPROM_BUS_NUM 0
Priyanka Jainfd45ca02018-11-28 13:04:27 +000091
92/* Qixis */
93#define CONFIG_FSL_QIXIS
94#define CONFIG_QIXIS_I2C_ACCESS
95#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
96
97/* PCI */
98#ifdef CONFIG_PCI
Priyanka Jainfd45ca02018-11-28 13:04:27 +000099#define CONFIG_PCI_SCAN_SHOW
100#endif
101
Priyanka Jainfd45ca02018-11-28 13:04:27 +0000102/* SATA */
103
104#ifdef CONFIG_SCSI
Priyanka Jainfd45ca02018-11-28 13:04:27 +0000105#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1
106#define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2
Priyanka Jainfd45ca02018-11-28 13:04:27 +0000107#endif
108
109/* USB */
Tom Rini8a091622021-07-09 10:11:55 -0400110#ifdef CONFIG_USB_HOST
Meenakshi Aggarwal8a03b0d2020-12-04 20:17:28 +0530111#ifndef CONFIG_TARGET_LX2162AQDS
Priyanka Jainfd45ca02018-11-28 13:04:27 +0000112#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
113#endif
Meenakshi Aggarwal8a03b0d2020-12-04 20:17:28 +0530114#endif
Priyanka Jainfd45ca02018-11-28 13:04:27 +0000115
Tom Rini8c70baa2021-12-14 13:36:40 -0500116#define COUNTER_FREQUENCY_REAL (get_board_sys_clk() / 4)
Priyanka Jainfd45ca02018-11-28 13:04:27 +0000117
118#define CONFIG_HWCONFIG
119#define HWCONFIG_BUFFER_SIZE 128
120
Priyanka Jainfd45ca02018-11-28 13:04:27 +0000121/* Monitor Command Prompt */
122#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
123#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
124 sizeof(CONFIG_SYS_PROMPT) + 16)
125#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */
Priyanka Jainfd45ca02018-11-28 13:04:27 +0000126#define CONFIG_SYS_MAXARGS 64 /* max command args */
127
128#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
129
130/* Initial environment variables */
Kuldeep Singh3e78c332020-03-12 15:13:00 +0530131#define XSPI_MC_INIT_CMD \
132 "sf probe 0:0 && " \
133 "sf read 0x80640000 0x640000 0x80000 && " \
Priyanka Jain5fde1642021-08-18 12:37:03 +0530134 "sf read $fdt_addr_r 0xf00000 0x100000 && " \
Kuldeep Singh3e78c332020-03-12 15:13:00 +0530135 "env exists secureboot && " \
136 "esbc_validate 0x80640000 && " \
137 "esbc_validate 0x80680000; " \
138 "sf read 0x80a00000 0xa00000 0x300000 && " \
139 "sf read 0x80e00000 0xe00000 0x100000; " \
140 "fsl_mc start mc 0x80a00000 0x80e00000\0"
Priyanka Jainfd45ca02018-11-28 13:04:27 +0000141
142#define SD_MC_INIT_CMD \
Pankaj Bansal1972a532019-07-17 10:33:54 +0000143 "mmc read 0x80a00000 0x5000 0x1200;" \
144 "mmc read 0x80e00000 0x7000 0x800;" \
Priyanka Jain5fde1642021-08-18 12:37:03 +0530145 "mmc read $fdt_addr_r 0x7800 0x800;" \
Udit Agarwalf34581e2018-12-14 04:43:32 +0000146 "env exists secureboot && " \
Priyanka Singhe29ef972020-01-22 10:31:22 +0000147 "mmc read 0x80640000 0x3200 0x20 && " \
148 "mmc read 0x80680000 0x3400 0x20 && " \
149 "esbc_validate 0x80640000 && " \
150 "esbc_validate 0x80680000 ;" \
Pankaj Bansal1972a532019-07-17 10:33:54 +0000151 "fsl_mc start mc 0x80a00000 0x80e00000\0"
Priyanka Jainfd45ca02018-11-28 13:04:27 +0000152
Meenakshi Aggarwale181a3d2020-04-27 19:56:40 +0530153#define SD2_MC_INIT_CMD \
154 "mmc dev 1; mmc read 0x80a00000 0x5000 0x1200;" \
155 "mmc read 0x80e00000 0x7000 0x800;" \
Priyanka Jain5fde1642021-08-18 12:37:03 +0530156 "mmc read $fdt_addr_r 0x7800 0x800;" \
Meenakshi Aggarwale181a3d2020-04-27 19:56:40 +0530157 "env exists secureboot && " \
158 "mmc read 0x80640000 0x3200 0x20 && " \
159 "mmc read 0x80680000 0x3400 0x20 && " \
160 "esbc_validate 0x80640000 && " \
161 "esbc_validate 0x80680000 ;" \
162 "fsl_mc start mc 0x80a00000 0x80e00000\0"
163
Priyanka Jain16744062019-01-24 05:22:18 +0000164#define EXTRA_ENV_SETTINGS \
165 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
166 "ramdisk_addr=0x800000\0" \
167 "ramdisk_size=0x2000000\0" \
168 "fdt_high=0xa0000000\0" \
169 "initrd_high=0xffffffffffffffff\0" \
170 "fdt_addr=0x64f00000\0" \
171 "kernel_start=0x1000000\0" \
Priyanka Singhe29ef972020-01-22 10:31:22 +0000172 "kernelheader_start=0x600000\0" \
Priyanka Jain16744062019-01-24 05:22:18 +0000173 "scriptaddr=0x80000000\0" \
174 "scripthdraddr=0x80080000\0" \
175 "fdtheader_addr_r=0x80100000\0" \
176 "kernelheader_addr_r=0x80200000\0" \
177 "kernel_addr_r=0x81000000\0" \
178 "kernelheader_size=0x40000\0" \
179 "fdt_addr_r=0x90000000\0" \
180 "load_addr=0xa0000000\0" \
181 "kernel_size=0x2800000\0" \
182 "kernel_addr_sd=0x8000\0" \
Priyanka Singhe29ef972020-01-22 10:31:22 +0000183 "kernelhdr_addr_sd=0x3000\0" \
Manish Tomarebef67f2020-11-05 14:08:56 +0530184 "kernel_size_sd=0x14000\0" \
Udit Agarwal11e1a572019-11-20 08:49:06 +0000185 "kernelhdr_size_sd=0x20\0" \
Priyanka Jain16744062019-01-24 05:22:18 +0000186 "console=ttyAMA0,38400n8\0" \
187 BOOTENV \
188 "mcmemsize=0x70000000\0" \
189 XSPI_MC_INIT_CMD \
Priyanka Jain16744062019-01-24 05:22:18 +0000190 "scan_dev_for_boot_part=" \
191 "part list ${devtype} ${devnum} devplist; " \
192 "env exists devplist || setenv devplist 1; " \
193 "for distro_bootpart in ${devplist}; do " \
194 "if fstype ${devtype} " \
195 "${devnum}:${distro_bootpart} " \
196 "bootfstype; then " \
197 "run scan_dev_for_boot; " \
198 "fi; " \
199 "done\0" \
Priyanka Jain16744062019-01-24 05:22:18 +0000200 "boot_a_script=" \
201 "load ${devtype} ${devnum}:${distro_bootpart} " \
202 "${scriptaddr} ${prefix}${script}; " \
203 "env exists secureboot && load ${devtype} " \
204 "${devnum}:${distro_bootpart} " \
205 "${scripthdraddr} ${prefix}${boot_script_hdr} " \
206 "&& esbc_validate ${scripthdraddr};" \
207 "source ${scriptaddr}\0"
208
209#define XSPI_NOR_BOOTCOMMAND \
Kuldeep Singh3e78c332020-03-12 15:13:00 +0530210 "sf probe 0:0; " \
211 "sf read 0x806c0000 0x6c0000 0x40000; " \
212 "env exists mcinitcmd && env exists secureboot" \
213 " && esbc_validate 0x806c0000; " \
214 "sf read 0x80d00000 0xd00000 0x100000; " \
Priyanka Jain16744062019-01-24 05:22:18 +0000215 "env exists mcinitcmd && " \
Kuldeep Singh3e78c332020-03-12 15:13:00 +0530216 "fsl_mc lazyapply dpl 0x80d00000; " \
Priyanka Jain16744062019-01-24 05:22:18 +0000217 "run distro_bootcmd;run xspi_bootcmd; " \
218 "env exists secureboot && esbc_halt;"
219
220#define SD_BOOTCOMMAND \
221 "env exists mcinitcmd && mmcinfo; " \
Pankaj Bansal1972a532019-07-17 10:33:54 +0000222 "mmc read 0x80d00000 0x6800 0x800; " \
Priyanka Jain16744062019-01-24 05:22:18 +0000223 "env exists mcinitcmd && env exists secureboot " \
Priyanka Singhe29ef972020-01-22 10:31:22 +0000224 " && mmc read 0x806C0000 0x3600 0x20 " \
225 "&& esbc_validate 0x806C0000;env exists mcinitcmd " \
Pankaj Bansal1972a532019-07-17 10:33:54 +0000226 "&& fsl_mc lazyapply dpl 0x80d00000;" \
Priyanka Jain16744062019-01-24 05:22:18 +0000227 "run distro_bootcmd;run sd_bootcmd;" \
228 "env exists secureboot && esbc_halt;"
229
Meenakshi Aggarwalbebebab2020-02-19 23:30:45 +0530230#define SD2_BOOTCOMMAND \
Meenakshi Aggarwale181a3d2020-04-27 19:56:40 +0530231 "mmc dev 1; env exists mcinitcmd && mmcinfo; " \
Meenakshi Aggarwalbebebab2020-02-19 23:30:45 +0530232 "mmc read 0x80d00000 0x6800 0x800; " \
233 "env exists mcinitcmd && env exists secureboot " \
Meenakshi Aggarwale181a3d2020-04-27 19:56:40 +0530234 " && mmc read 0x806C0000 0x3600 0x20 " \
235 "&& esbc_validate 0x806C0000;env exists mcinitcmd " \
Meenakshi Aggarwalbebebab2020-02-19 23:30:45 +0530236 "&& fsl_mc lazyapply dpl 0x80d00000;" \
237 "run distro_bootcmd;run sd2_bootcmd;" \
238 "env exists secureboot && esbc_halt;"
239
Daniel Klauerd7daa552022-02-09 15:53:41 +0100240#ifdef CONFIG_CMD_USB
241#define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0)
242#else
243#define BOOT_TARGET_DEVICES_USB(func)
244#endif
245
246#ifdef CONFIG_MMC
247#define BOOT_TARGET_DEVICES_MMC(func, instance) func(MMC, mmc, instance)
248#else
249#define BOOT_TARGET_DEVICES_MMC(func)
250#endif
251
252#ifdef CONFIG_SCSI
253#define BOOT_TARGET_DEVICES_SCSI(func) func(SCSI, scsi, 0)
254#else
255#define BOOT_TARGET_DEVICES_SCSI(func)
256#endif
257
258#ifdef CONFIG_CMD_DHCP
259#define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na)
260#else
261#define BOOT_TARGET_DEVICES_DHCP(func)
262#endif
263
Priyanka Jain16744062019-01-24 05:22:18 +0000264#define BOOT_TARGET_DEVICES(func) \
Daniel Klauerd7daa552022-02-09 15:53:41 +0100265 BOOT_TARGET_DEVICES_USB(func) \
266 BOOT_TARGET_DEVICES_MMC(func, 0) \
267 BOOT_TARGET_DEVICES_MMC(func, 1) \
268 BOOT_TARGET_DEVICES_SCSI(func) \
269 BOOT_TARGET_DEVICES_DHCP(func)
Priyanka Jain16744062019-01-24 05:22:18 +0000270#include <config_distro_bootcmd.h>
271
Priyanka Jainfd45ca02018-11-28 13:04:27 +0000272#endif /* __LX2_COMMON_H */