Marek Vasut | ae723e1 | 2012-08-26 15:19:06 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Generic bounce buffer implementation |
| 3 | * |
| 4 | * Copyright (C) 2012 Marek Vasut <marex@denx.de> |
| 5 | * |
Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 6 | * SPDX-License-Identifier: GPL-2.0+ |
Marek Vasut | ae723e1 | 2012-08-26 15:19:06 +0000 | [diff] [blame] | 7 | */ |
| 8 | |
| 9 | #ifndef __INCLUDE_BOUNCEBUF_H__ |
| 10 | #define __INCLUDE_BOUNCEBUF_H__ |
| 11 | |
Stephen Warren | 4a8629e | 2012-11-06 11:27:29 +0000 | [diff] [blame] | 12 | #include <linux/types.h> |
| 13 | |
Marek Vasut | ae723e1 | 2012-08-26 15:19:06 +0000 | [diff] [blame] | 14 | /* |
| 15 | * GEN_BB_READ -- Data are read from the buffer eg. by DMA hardware. |
| 16 | * The source buffer is copied into the bounce buffer (if unaligned, otherwise |
| 17 | * the source buffer is used directly) upon start() call, then the operation |
| 18 | * requiring the aligned transfer happens, then the bounce buffer is lost upon |
| 19 | * stop() call. |
| 20 | */ |
| 21 | #define GEN_BB_READ (1 << 0) |
| 22 | /* |
| 23 | * GEN_BB_WRITE -- Data are written into the buffer eg. by DMA hardware. |
| 24 | * The source buffer starts in an undefined state upon start() call, then the |
| 25 | * operation requiring the aligned transfer happens, then the bounce buffer is |
| 26 | * copied into the destination buffer (if unaligned, otherwise destination |
| 27 | * buffer is used directly) upon stop() call. |
| 28 | */ |
| 29 | #define GEN_BB_WRITE (1 << 1) |
| 30 | /* |
| 31 | * GEN_BB_RW -- Data are read and written into the buffer eg. by DMA hardware. |
| 32 | * The source buffer is copied into the bounce buffer (if unaligned, otherwise |
| 33 | * the source buffer is used directly) upon start() call, then the operation |
| 34 | * requiring the aligned transfer happens, then the bounce buffer is copied |
| 35 | * into the destination buffer (if unaligned, otherwise destination buffer is |
| 36 | * used directly) upon stop() call. |
| 37 | */ |
| 38 | #define GEN_BB_RW (GEN_BB_READ | GEN_BB_WRITE) |
| 39 | |
Stephen Warren | 4a8629e | 2012-11-06 11:27:29 +0000 | [diff] [blame] | 40 | struct bounce_buffer { |
| 41 | /* Copy of data parameter passed to start() */ |
| 42 | void *user_buffer; |
| 43 | /* |
| 44 | * DMA-aligned buffer. This field is always set to the value that |
| 45 | * should be used for DMA; either equal to .user_buffer, or to a |
| 46 | * freshly allocated aligned buffer. |
| 47 | */ |
| 48 | void *bounce_buffer; |
| 49 | /* Copy of len parameter passed to start() */ |
| 50 | size_t len; |
| 51 | /* DMA-aligned buffer length */ |
| 52 | size_t len_aligned; |
| 53 | /* Copy of flags parameter passed to start() */ |
| 54 | unsigned int flags; |
| 55 | }; |
| 56 | |
Marek Vasut | ae723e1 | 2012-08-26 15:19:06 +0000 | [diff] [blame] | 57 | /** |
| 58 | * bounce_buffer_start() -- Start the bounce buffer session |
Stephen Warren | 4a8629e | 2012-11-06 11:27:29 +0000 | [diff] [blame] | 59 | * state: stores state passed between bounce_buffer_{start,stop} |
Marek Vasut | ae723e1 | 2012-08-26 15:19:06 +0000 | [diff] [blame] | 60 | * data: pointer to buffer to be aligned |
| 61 | * len: length of the buffer |
Marek Vasut | ae723e1 | 2012-08-26 15:19:06 +0000 | [diff] [blame] | 62 | * flags: flags describing the transaction, see above. |
| 63 | */ |
Stephen Warren | 4a8629e | 2012-11-06 11:27:29 +0000 | [diff] [blame] | 64 | int bounce_buffer_start(struct bounce_buffer *state, void *data, |
| 65 | size_t len, unsigned int flags); |
Marek Vasut | ae723e1 | 2012-08-26 15:19:06 +0000 | [diff] [blame] | 66 | /** |
| 67 | * bounce_buffer_stop() -- Finish the bounce buffer session |
Stephen Warren | 4a8629e | 2012-11-06 11:27:29 +0000 | [diff] [blame] | 68 | * state: stores state passed between bounce_buffer_{start,stop} |
Marek Vasut | ae723e1 | 2012-08-26 15:19:06 +0000 | [diff] [blame] | 69 | */ |
Stephen Warren | 4a8629e | 2012-11-06 11:27:29 +0000 | [diff] [blame] | 70 | int bounce_buffer_stop(struct bounce_buffer *state); |
Marek Vasut | ae723e1 | 2012-08-26 15:19:06 +0000 | [diff] [blame] | 71 | |
| 72 | #endif |